Width, Switch and Interleave? -- WAS: Benefits of Linux/Alpha over Linux/x86?

["Bryan J. Smith" <b j smith ieee org>]

Re: Benefits of Linux/Alpha over Linux/x86? <- Width & Interleave

W Bauske wrote:
> Right. But, the XP1000 and UP2K both do 4 way DIMM interleave, which
> is really 8 way because a DIMM is already two way. Once you get to
> that point, how would you gain anymore performance? That would
> take another D-chip, if I remember the Alpha's chipset terminology.
> And, that is what makes the DS20/DP264 different from a UP2K
> since it does have two chips for accessing memory, but it also uses
> 16 DIMM slots, 8 for each chip.
> 
> Also, both XP1000 and UP2K do not require the DIMM's in between sets to
> be the same which to me, indicates the banks are quite separate. The
> only requirement is that each set of 4 is identical.
> 
> Also, if it were true 8 way improved speed, then how come the specs
> don't say that?

Okay, I think everyone is getting confused between Width, Switch and
Interleave.  First off, I am ** NO EXPERT HERE ** and I'm probably
not even using the correct terminology (please educated me ;-).  But
I'm going to take some guesses ... based largely on just my college
background (which doesn't really mean crap since I don't have any
real-world design experience with mainboards/chipset) and what I can
see from product spec sheets.

- Width (e.g, 64-bit, 128-bit, etc...)
  This is the largest common width between the CPU and memory,
  and I assume this is how mainboards are optimally designed.
  E.g., Slot-1/Slot-2/Socket-370 as well as Slot-A/Socket-A
  are all 64-bit width busses, so most of these mainboards
  use a 64-bit interconnect on the chipset between the CPUs
  and memory (1 DIMM).  Slot-B, on the otherhand, is a 128-bit
  width bus so I assume Alpha (future Athlon "Pro" too???) use a
  128bit interconnect on the chipset between the CPUs and
  and memory (2 DIMM).

- Switch (e.g., symmetric, point-to-point, NUMA, etc...)
  GTL+ (Slot-1/Slot-2/Socket-370) use a symmetric bus for multiple
  CPU and memory channels.  As such, only 1 CPU, 1 memory or 1 I/O
  channel can be communicating simultanously (???).  EV6 (Slot-A/
  Slot-B/Socket-A) uses a point-to-point bus so the chipset can
  handle multiple points on each talking to each other.  Curious
  as to how NUMA and point-to-point are similiar and different?

- Interleave (e.g. 2-way, 4-way, etc...)
  Interleave can be used on any bus to reduce latency and increase
  throughput.  Interleave involved changing the communication
between
  one node on the end of a symmetric or point-to-point bus between
  one similiar bank (e.g., from one bank of memory to another) in
  order to reduce latency and increase throughput.  By alterating
  banks every bus clock cycle (or set of clock ticks in a cycle),
  the latency of memory (usually much greater than a cycle of the
  bus clock) can be reduced, especially when different read requests
  are issued.  Secondly, in the case of non-synchronous memory
  especially (like FPM, EDO, etc...), interleaving can spead up
  transfers by interleaving bursts between banks of memory.

Again, I'm no expert and I'm just taking some guesses here.  But as
far as I can tell, the design of a mainboard/chipset is 3-fold over
these attributes.

-- TheBS

-- 
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