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Re: [dm-devel] [PATCHSET block#for-2.6.36-post] block: replace barrier with sequenced flush
- From: Christoph Hellwig <hch lst de>
- To: Tejun Heo <tj kernel org>
- Cc: tytso mit edu, linux-scsi vger kernel org, jaxboe fusionio com, jack suse cz, linux-kernel vger kernel org, swhiteho redhat com, linux-raid vger kernel org, linux-ide vger kernel org, dm-devel redhat com, James Bottomley suse de, konishi ryusuke lab ntt co jp, linux-fsdevel vger kernel org, vst vlnb net, Ric Wheeler <rwheeler redhat com>, Christoph Hellwig <hch lst de>, chris mason oracle com
- Subject: Re: [dm-devel] [PATCHSET block#for-2.6.36-post] block: replace barrier with sequenced flush
- Date: Mon, 23 Aug 2010 14:48:15 +0200
On Mon, Aug 23, 2010 at 02:30:33PM +0200, Tejun Heo wrote:
> It might be useful to give several example configurations with
> different cache configurations. I don't have much experience with
> battery backed arrays but aren't they suppose to report write through
> cache automatically?
They usually do. I have one that doesn't, but SYNCHRONIZE CACHE on
it is so fast that it effectively must be a no-op.
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