Evaluating Hardware/ Software Tradeoffs - Hardware extensions and the compilers that make them real

by Michael Tiemann, Gordon Irlam, Ian Lance-Taylor, Doug Evans, and Per Bothner

In January 2000, Cygnus was bought by Red Hat.

Content

  1. Extension models
  2. 16-/32-bit RISC
  3. MIPS-16
  4. Visual/Math ISAs
  5. Sun's Visual Instruction Set
  6. JAVA

Abstract

Introduction
Higher performance with more bang for the buck is today's microprocessor game. We have the architectural expertise and technology to design radically new microprocessors, to craft new and sophisticated ISAs (Instruction Set Architectures). But we don't. Instead, the trend is to extend existing ISAs, giving performance boosts to current microprocessors.

These extensions would be so much unused silicon if not for assembler and compiler support. It is the development software that ensures effective employment of new ISA features. It is the assemblers and compilers that make the hardware/software tradeoffs to make these extensions cost effective. Thus ISA extensions appear as software libraries or compiler enhancements for programmer and compiler use. Cygnus Solutions provides development tools and compilers for over 30 architectures and around 100 different microprocessors, a number of which incorporate ISA extensions.

ISA extensions combine the better of two worlds: using existing microprocessor architecture, and adding new high-performance processor technology to boost performance. Today's microprocessors represent large investments in development software, existing application and operating software, and a programmer/talent pool. For example if you have a project and you choose a 68K or a SPARC, you have a wide range of operating, development and application software available for use. New architectures need time to build up an equivalent software base.

Extensions let microprocessor architects incrementally add new technology as it comes on line. Some ISA extensions now emerging include:

  • Graphics/Math ISA Extensions
    These include Sun's UltraSPARC Visual Instruction Set (VIS), MIPS' MDMX, Intel's MMX, and others. These extensions use the floating-point registers (or registers that use that address space) and extend the Floating-Point Unit to do specialized graphics and math processing.
  • Dynamic 16-/32-bit RISC
    These extensions create an ISA subset of a 32-bit RISC, an ISA subset that fits in 16-bit instructions. However, it keeps the 32-bit datapath. This tactic cuts RISC code bloat, especially for code intensive applications but keeps 32-bit data processing capabilities. The dynamic part is that programs can switch from the 32-bit to 16-bit ISAs as needed while running. The code is compiled for mixed 16- or 32-bit ISA operation.
  • DSP Extensions
    DSPs have carved out a high performance, math intensive processing niche. These extensions model themselves after specialized DSP processors and add DSP-like operations to standard RISC architectures. These include adding MAC (multiply-accumulate) instructions and other interactive, math-oriented processing. Typical DSP applications iterate a series and find some cumulative result (SUM Xi*Yj for i, j) This approach is very useful for digitally processing analog signals and array/matrix processing.
  • Java Software Engine
    Java is a software extension to hardware. It creates a software compute engine, literally a JAVA virtual machine that executes JAVA instructions and object code. Java started out with a byte-code interpreter in its execution engine. Compiled versions of Java are emerging to deliver higher, C-level performance.

The GNU tools are highly modular and designed to support a wide range of architectures and processors. Figure 1 illustrates the GNU compiler/assembler/linker processing flow. It also shows where ISA extensions are added to the flow.

Figure1:  ISA extensions and compiler/assembler/linker flow from source code to an executable

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