Fwd: AMD x2 chips

[Mark Hahn]

> > no, just one IC.
> 
> One "die" -- but each CPU is an independent integrated circuit (IC).

the cores on AMD's dual-core chips are most definitely not 
independent ICs.

> > you mean in the trivial sense that each core is replicated?  sure.
> 
> I meant versus Intel who has to do additional bridging inside theirs.

the opposite is true: Intel's DC chips are much closer to being separate
ICs, since they're attached with even less bridging (present two bus loads,
for instance).

> > none:
> > http://multicore.amd.com/Products/AMD_Opteron_Overview.pdf
> > the chip is based on a crossbar-like arbiter that connects HT ports,
> > DRAM controller and the cores.  the latter connect together, apparently.
> > they might be different ports on the crossbar, but they're definitely
> > not using HT, since a DC chip is a single HT "node" for addressing purposes.
> 
> First off, that's _not_ a technical manual.

it meets your level of knowlege.  the diagram is the same one that AMD
has presented from the very beginning, always showing core-srq-xbar.
before DC, the srq seemed out-of-place.

> Secondly, AMD _does_ reference it's "Direct Connect Architecture" and
> other technologies.  It would _not_ surprise me if that Crossbar is
> _indeed_ just a HyperTransport interconnect -- or some kind of more
> primitive EV6 interconnect.
> 
> Remember, AMD is doing multi-_board_ with HyperTransport as well.
> Literally "daisy chaining" HyperTransport from each 4 CPU board to
> another over additional HyperTransport interconnects.

HT has never had a 4-CPU limit.  but perhaps you're confusing this with
Newisys's Horus.

> So what's to say they're not doing the same _inside_ each die?

so they're going to invent a whole new HT addressing scheme just so they can
do glueless HT within the chip?  that makes no sense.  it would be pointless 
and expensive generality.