rpms/kernel/FC-3 jwltest-tg3-3_25.patch, NONE, 1.1.2.1 jwltest-tg3-exp1.patch, NONE, 1.1.2.1 kernel-2.6.spec, 1.821.2.1, 1.821.2.2
fedora-cvs-commits at redhat.com
fedora-cvs-commits at redhat.com
Thu May 5 20:31:42 UTC 2005
Author: linville
Update of /cvs/dist/rpms/kernel/FC-3
In directory cvs.devel.redhat.com:/tmp/cvs-serv29948
Modified Files:
Tag: private-linville-fc3-jwltest-9-branch
kernel-2.6.spec
Added Files:
Tag: private-linville-fc3-jwltest-9-branch
jwltest-tg3-3_25.patch jwltest-tg3-exp1.patch
Log Message:
jwltest-tg3-3_25.patch:
tg3.c | 222 ++++++++++++++++++++++++++++++++++++++----------------------------
tg3.h | 4 +
2 files changed, 135 insertions(+), 91 deletions(-)
--- NEW FILE jwltest-tg3-3_25.patch ---
--- linux-2.6.11/drivers/net/tg3.c.orig 2005-05-05 16:06:28.371637050 -0400
+++ linux-2.6.11/drivers/net/tg3.c 2005-05-05 16:20:05.351798980 -0400
@@ -4,6 +4,7 @@
* Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem at redhat.com)
* Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik at pobox.com)
* Copyright (C) 2004 Sun Microsystems Inc.
+ * Copyright (C) 2005 Broadcom Corporation.
*
* Firmware is:
* Copyright (C) 2000-2003 Broadcom Corporation.
@@ -60,8 +61,8 @@
#define DRV_MODULE_NAME "tg3"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "3.23"
-#define DRV_MODULE_RELDATE "February 15, 2005"
+#define DRV_MODULE_VERSION "3.25"
+#define DRV_MODULE_RELDATE "March 24, 2005"
#define TG3_DEF_MAC_MODE 0
#define TG3_DEF_RX_MODE 0
@@ -103,9 +104,7 @@
* replace things like '% foo' with '& (foo - 1)'.
*/
#define TG3_RX_RCB_RING_SIZE(tp) \
- ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || \
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ? \
- 512 : 1024)
+ ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
#define TG3_TX_RING_SIZE 512
#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
@@ -469,8 +468,7 @@ static void tg3_switch_clocks(struct tg3
0x1f);
tp->pci_clock_ctrl = clock_ctrl;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
tw32_f(TG3PCI_CLOCK_CTRL,
clock_ctrl | CLOCK_CTRL_625_CORE);
@@ -872,6 +870,19 @@ out:
!tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
}
+
+ /* Set phy register 0x10 bit 0 to high fifo elasticity to support
+ * jumbo frames transmission.
+ */
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+ u32 phy_reg;
+
+ if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
+ tg3_writephy(tp, MII_TG3_EXT_CTRL,
+ phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
+ }
+
tg3_phy_set_wirespeed(tp);
return 0;
}
@@ -970,6 +981,7 @@ static int tg3_setup_phy(struct tg3 *, i
#define RESET_KIND_SUSPEND 2
static void tg3_write_sig_post_reset(struct tg3 *, int);
+static int tg3_halt_cpu(struct tg3 *, u32);
static int tg3_set_power_state(struct tg3 *tp, int state)
{
@@ -1094,8 +1106,7 @@ static int tg3_set_power_state(struct tg
CLOCK_CTRL_TXCLK_DISABLE |
CLOCK_CTRL_ALTCLK);
newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
- } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
newbits1 = CLOCK_CTRL_625_CORE;
newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
} else {
@@ -1109,8 +1120,7 @@ static int tg3_set_power_state(struct tg
tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
udelay(40);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
u32 newbits3;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
@@ -1130,6 +1140,17 @@ static int tg3_set_power_state(struct tg
tg3_frob_aux_power(tp);
+ /* Workaround for unstable PLL clock */
+ if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
+ (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
+ u32 val = tr32(0x7d00);
+
+ val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
+ tw32(0x7d00, val);
+ if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
+ tg3_halt_cpu(tp, RX_CPU_BASE);
+ }
+
/* Finally, set the new power state. */
pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
@@ -2449,8 +2470,7 @@ static int tg3_setup_phy(struct tg3 *tp,
(6 << TX_LENGTHS_IPG_SHIFT) |
(32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
if (netif_carrier_ok(tp->dev)) {
tw32(HOSTCC_STAT_COAL_TICKS,
DEFAULT_STAT_COAL_TICKS);
@@ -2893,7 +2913,13 @@ static irqreturn_t tg3_interrupt(int irq
spin_lock_irqsave(&tp->lock, flags);
- if (sblk->status & SD_STATUS_UPDATED) {
+ /* In INTx mode, it is possible for the interrupt to arrive at
+ * the CPU before the status block posted prior to the interrupt.
+ * Reading the PCI State register will confirm whether the
+ * interrupt is ours and will flush the status block.
+ */
+ if ((sblk->status & SD_STATUS_UPDATED) ||
+ !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
/*
* writing any value to intr-mbox-0 clears PCI INTA# and
* chip-internal interrupt pending events.
@@ -3018,6 +3044,7 @@ static int tigon3_4gb_hwbug_workaround(s
tp->tx_buffers[entry].skb = NULL;
}
entry = NEXT_TX(entry);
+ i++;
}
dev_kfree_skb(skb);
@@ -3111,6 +3138,14 @@ static int tg3_start_xmit(struct sk_buff
(mss = skb_shinfo(skb)->tso_size) != 0) {
int tcp_opt_len, ip_tcp_len;
+#if 0 /* Not in FC3... */
+ if (skb_header_cloned(skb) &&
+ pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
+ dev_kfree_skb(skb);
+ goto out_unlock;
+ }
+#endif
+
tcp_opt_len = ((skb->h.th->doff - 5) * 4);
ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
@@ -3563,8 +3598,7 @@ static int tg3_stop_block(struct tg3 *tp
unsigned int i;
u32 val;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
switch (ofs) {
case RCVLSC_MODE:
case DMAC_MODE:
@@ -3698,8 +3732,9 @@ static void tg3_nvram_unlock(struct tg3
/* tp->lock is held. */
static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
{
- tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
- NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
+ if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
+ tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
+ NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
switch (kind) {
@@ -3805,8 +3840,7 @@ static int tg3_chip_reset(struct tg3 *tp
}
}
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
tw32(GRC_MISC_CFG, val);
@@ -3903,19 +3937,20 @@ static int tg3_chip_reset(struct tg3 *tp
tw32_f(MAC_MODE, 0);
udelay(40);
- /* Wait for firmware initialization to complete. */
- for (i = 0; i < 100000; i++) {
- tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
- if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
- break;
- udelay(10);
- }
- if (i >= 100000 &&
- !(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
- printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
- "firmware will not restart magic=%08x\n",
- tp->dev->name, val);
- return -ENODEV;
+ if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
+ /* Wait for firmware initialization to complete. */
+ for (i = 0; i < 100000; i++) {
+ tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
+ if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
+ break;
+ udelay(10);
+ }
+ if (i >= 100000) {
+ printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
+ "firmware will not restart magic=%08x\n",
+ tp->dev->name, val);
+ return -ENODEV;
+ }
}
if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
@@ -4120,7 +4155,7 @@ static int tg3_halt_cpu(struct tg3 *tp,
int i;
if (offset == TX_CPU_BASE &&
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
+ (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
BUG();
if (offset == RX_CPU_BASE) {
@@ -4174,14 +4209,14 @@ static int tg3_load_firmware_cpu(struct
void (*write_op)(struct tg3 *, u32, u32);
if (cpu_base == TX_CPU_BASE &&
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
+ (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
"TX cpu firmware on %s which is 5705.\n",
tp->dev->name);
return -EINVAL;
}
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
write_op = tg3_write_mem;
else
write_op = tg3_write_indirect_reg32;
@@ -4921,8 +4956,7 @@ static void tg3_set_bdinfo(struct tg3 *t
(bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
maxlen_flags);
- if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
- (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750))
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
tg3_write_mem(tp,
(bdinfo_addr + TG3_BDINFO_NIC_ADDR),
nic_addr);
@@ -5100,8 +5134,7 @@ static int tg3_reset_hw(struct tg3 *tp)
/* Don't even try to program the JUMBO/MINI buffer descriptor
* configs on 5705.
*/
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
} else {
@@ -5133,8 +5166,7 @@ static int tg3_reset_hw(struct tg3 *tp)
/* There is only one send ring on 5705/5750, no need to explicitly
* disable the others.
*/
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
/* Clear out send RCB ring in SRAM. */
for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
@@ -5155,8 +5187,7 @@ static int tg3_reset_hw(struct tg3 *tp)
/* There is only one receive return ring on 5705/5750, no need
* to explicitly disable the others.
*/
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
i += TG3_BDINFO_SIZE) {
tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
@@ -5255,8 +5286,7 @@ static int tg3_reset_hw(struct tg3 *tp)
tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
tw32(HOSTCC_RXMAX_FRAMES, 1);
tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
tw32(HOSTCC_RXCOAL_TICK_INT, 0);
tw32(HOSTCC_TXCOAL_TICK_INT, 0);
}
@@ -5269,8 +5299,7 @@ static int tg3_reset_hw(struct tg3 *tp)
tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
((u64) tp->status_mapping & 0xffffffff));
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
/* Status/statistics block address. See tg3_timer,
* the tg3_periodic_fetch_stats call there, and
* tg3_get_stats to see how this works for 5705/5750 chips.
@@ -5289,8 +5318,7 @@ static int tg3_reset_hw(struct tg3 *tp)
tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
/* Clear statistics/status block in chip, and status block in ram. */
@@ -5317,8 +5345,7 @@ static int tg3_reset_hw(struct tg3 *tp)
tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
tr32(MAILBOX_INTERRUPT_0);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
udelay(40);
}
@@ -5365,8 +5392,7 @@ static int tg3_reset_hw(struct tg3 *tp)
udelay(40);
tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
@@ -5470,8 +5496,7 @@ static int tg3_reset_hw(struct tg3 *tp)
tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
limit = 8;
else
limit = 16;
@@ -5615,8 +5640,7 @@ static void tg3_timer(unsigned long __op
return;
}
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
tg3_periodic_fetch_stats(tp);
/* This part only runs once per second. */
@@ -6525,10 +6549,6 @@ static int tg3_get_settings(struct net_d
{
struct tg3 *tp = netdev_priv(dev);
- if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
- tp->link_config.phy_is_low_power)
- return -EAGAIN;
-
cmd->supported = (SUPPORTED_Autoneg);
if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
@@ -6545,8 +6565,10 @@ static int tg3_get_settings(struct net_d
cmd->supported |= SUPPORTED_FIBRE;
cmd->advertising = tp->link_config.advertising;
- cmd->speed = tp->link_config.active_speed;
- cmd->duplex = tp->link_config.active_duplex;
+ if (netif_running(dev)) {
+ cmd->speed = tp->link_config.active_speed;
+ cmd->duplex = tp->link_config.active_duplex;
+ }
cmd->port = 0;
cmd->phy_address = PHY_ADDR;
cmd->transceiver = 0;
@@ -6560,10 +6582,6 @@ static int tg3_set_settings(struct net_d
{
struct tg3 *tp = netdev_priv(dev);
- if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
- tp->link_config.phy_is_low_power)
- return -EAGAIN;
-
if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
/* These are the only valid advertisement bits allowed. */
if (cmd->autoneg == AUTONEG_ENABLE &&
@@ -6588,7 +6606,9 @@ static int tg3_set_settings(struct net_d
tp->link_config.duplex = cmd->duplex;
}
- tg3_setup_phy(tp, 1);
+ if (netif_running(dev))
+ tg3_setup_phy(tp, 1);
+
spin_unlock(&tp->tx_lock);
spin_unlock_irq(&tp->lock);
@@ -6668,6 +6688,9 @@ static int tg3_nway_reset(struct net_dev
u32 bmcr;
int r;
+ if (!netif_running(dev))
+ return -EAGAIN;
+
spin_lock_irq(&tp->lock);
r = -EINVAL;
tg3_readphy(tp, MII_BMCR, &bmcr);
@@ -6704,7 +6727,9 @@ static int tg3_set_ringparam(struct net_
(ering->tx_pending > TG3_TX_RING_SIZE - 1))
return -EINVAL;
- tg3_netif_stop(tp);
+ if (netif_running(dev))
+ tg3_netif_stop(tp);
+
spin_lock_irq(&tp->lock);
spin_lock(&tp->tx_lock);
@@ -6716,9 +6741,12 @@ static int tg3_set_ringparam(struct net_
tp->rx_jumbo_pending = ering->rx_jumbo_pending;
tp->tx_pending = ering->tx_pending;
- tg3_halt(tp);
- tg3_init_hw(tp);
- tg3_netif_start(tp);
+ if (netif_running(dev)) {
+ tg3_halt(tp);
+ tg3_init_hw(tp);
+ tg3_netif_start(tp);
+ }
+
spin_unlock(&tp->tx_lock);
spin_unlock_irq(&tp->lock);
@@ -6738,7 +6766,9 @@ static int tg3_set_pauseparam(struct net
{
struct tg3 *tp = netdev_priv(dev);
- tg3_netif_stop(tp);
+ if (netif_running(dev))
+ tg3_netif_stop(tp);
+
spin_lock_irq(&tp->lock);
spin_lock(&tp->tx_lock);
if (epause->autoneg)
@@ -6753,9 +6783,12 @@ static int tg3_set_pauseparam(struct net
tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
else
tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
- tg3_halt(tp);
- tg3_init_hw(tp);
- tg3_netif_start(tp);
+
+ if (netif_running(dev)) {
+ tg3_halt(tp);
+ tg3_init_hw(tp);
+ tg3_netif_start(tp);
+ }
spin_unlock(&tp->tx_lock);
spin_unlock_irq(&tp->lock);
@@ -7830,6 +7863,19 @@ static int __devinit tg3_is_sun_570X(str
static int __devinit tg3_get_invariants(struct tg3 *tp)
{
+ static struct pci_device_id write_reorder_chipsets[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82801AA_8) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82801AB_8) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82801BA_11) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82801BA_6) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_FE_GATE_700C) },
+ { },
+ };
u32 misc_ctrl_reg;
u32 cacheline_sz_reg;
u32 pci_state_reg, grc_misc_cfg;
@@ -7848,16 +7894,7 @@ static int __devinit tg3_get_invariants(
* every mailbox register write to force the writes to be
* posted to the chip in order.
*/
- if (pci_find_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_82801AA_8, NULL) ||
- pci_find_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_82801AB_8, NULL) ||
- pci_find_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_82801BA_11, NULL) ||
- pci_find_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_82801BA_6, NULL) ||
- pci_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_FE_GATE_700C, NULL))
+ if (pci_dev_present(write_reorder_chipsets))
tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
/* Force memory write invalidate off. If we leave it on,
@@ -7897,6 +7934,10 @@ static int __devinit tg3_get_invariants(
tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
+ if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
+ (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
+ tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
+
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
@@ -8784,8 +8825,7 @@ static int __devinit tg3_init_one(struct
goto err_out_iounmap;
}
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
tp->bufmgr_config.mbuf_read_dma_low_water =
DEFAULT_MB_RDMA_LOW_WATER_5705;
tp->bufmgr_config.mbuf_mac_rx_low_water =
@@ -8941,7 +8981,7 @@ static void __devexit tg3_remove_one(str
}
}
-static int tg3_suspend(struct pci_dev *pdev, u32 state)
+static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct net_device *dev = pci_get_drvdata(pdev);
struct tg3 *tp = netdev_priv(dev);
@@ -8968,7 +9008,7 @@ static int tg3_suspend(struct pci_dev *p
spin_unlock(&tp->tx_lock);
spin_unlock_irq(&tp->lock);
- err = tg3_set_power_state(tp, state);
+ err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
if (err) {
spin_lock_irq(&tp->lock);
spin_lock(&tp->tx_lock);
--- linux-2.6.11/drivers/net/tg3.h.orig 2005-05-05 16:16:46.723259950 -0400
+++ linux-2.6.11/drivers/net/tg3.h 2005-05-05 16:19:07.889454057 -0400
@@ -140,6 +140,8 @@
#define CHIPREV_5703_AX 0x10
#define CHIPREV_5704_AX 0x20
#define CHIPREV_5704_BX 0x21
+#define CHIPREV_5750_AX 0x40
+#define CHIPREV_5750_BX 0x41
#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
#define METAL_REV_A0 0x00
#define METAL_REV_A1 0x01
@@ -1516,6 +1518,7 @@
#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
+#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
#define MII_TG3_EXT_CTRL_TBI 0x8000
@@ -2110,6 +2113,7 @@ struct tg3 {
#define TG3_FLG2_FLASH 0x00008000
#define TG3_FLG2_HW_TSO 0x00010000
#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
+#define TG3_FLG2_5705_PLUS 0x00040000
u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3
jwltest-tg3-exp1.patch:
tg3.c | 124 +++++++++++++++++++++---------------------------------------------
1 files changed, 41 insertions(+), 83 deletions(-)
--- NEW FILE jwltest-tg3-exp1.patch ---
--- linux-2.6.11/drivers/net/tg3.c.orig 2005-05-05 16:25:35.383831880 -0400
+++ linux-2.6.11/drivers/net/tg3.c 2005-05-05 16:22:50.510796499 -0400
@@ -61,8 +61,8 @@
#define DRV_MODULE_NAME "tg3"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "3.25"
-#define DRV_MODULE_RELDATE "March 24, 2005"
+#define DRV_MODULE_VERSION "3.25.jwltest.9"
+#define DRV_MODULE_RELDATE "May 5, 2005"
#define TG3_DEF_MAC_MODE 0
#define TG3_DEF_RX_MODE 0
@@ -870,19 +870,6 @@ out:
!tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
}
-
- /* Set phy register 0x10 bit 0 to high fifo elasticity to support
- * jumbo frames transmission.
- */
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
- u32 phy_reg;
-
- if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
- tg3_writephy(tp, MII_TG3_EXT_CTRL,
- phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
- }
-
tg3_phy_set_wirespeed(tp);
return 0;
}
@@ -1140,17 +1127,6 @@ static int tg3_set_power_state(struct tg
tg3_frob_aux_power(tp);
- /* Workaround for unstable PLL clock */
- if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
- (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
- u32 val = tr32(0x7d00);
-
- val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
- tw32(0x7d00, val);
- if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
- tg3_halt_cpu(tp, RX_CPU_BASE);
- }
-
/* Finally, set the new power state. */
pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
@@ -2913,13 +2889,7 @@ static irqreturn_t tg3_interrupt(int irq
spin_lock_irqsave(&tp->lock, flags);
- /* In INTx mode, it is possible for the interrupt to arrive at
- * the CPU before the status block posted prior to the interrupt.
- * Reading the PCI State register will confirm whether the
- * interrupt is ours and will flush the status block.
- */
- if ((sblk->status & SD_STATUS_UPDATED) ||
- !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
+ if (sblk->status & SD_STATUS_UPDATED) {
/*
* writing any value to intr-mbox-0 clears PCI INTA# and
* chip-internal interrupt pending events.
@@ -3044,7 +3014,6 @@ static int tigon3_4gb_hwbug_workaround(s
tp->tx_buffers[entry].skb = NULL;
}
entry = NEXT_TX(entry);
- i++;
}
dev_kfree_skb(skb);
@@ -3732,9 +3701,8 @@ static void tg3_nvram_unlock(struct tg3
/* tp->lock is held. */
static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
{
- if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
- tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
- NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
+ tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
+ NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
switch (kind) {
@@ -3937,20 +3905,19 @@ static int tg3_chip_reset(struct tg3 *tp
tw32_f(MAC_MODE, 0);
udelay(40);
- if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
- /* Wait for firmware initialization to complete. */
- for (i = 0; i < 100000; i++) {
- tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
- if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
- break;
- udelay(10);
- }
- if (i >= 100000) {
- printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
- "firmware will not restart magic=%08x\n",
- tp->dev->name, val);
- return -ENODEV;
- }
+ /* Wait for firmware initialization to complete. */
+ for (i = 0; i < 100000; i++) {
+ tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
+ if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
+ break;
+ udelay(10);
+ }
+ if (i >= 100000 &&
+ !(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
+ printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
+ "firmware will not restart magic=%08x\n",
+ tp->dev->name, val);
+ return -ENODEV;
}
if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
@@ -4155,7 +4122,7 @@ static int tg3_halt_cpu(struct tg3 *tp,
int i;
if (offset == TX_CPU_BASE &&
- (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
BUG();
if (offset == RX_CPU_BASE) {
@@ -4209,14 +4176,14 @@ static int tg3_load_firmware_cpu(struct
void (*write_op)(struct tg3 *, u32, u32);
if (cpu_base == TX_CPU_BASE &&
- (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
"TX cpu firmware on %s which is 5705.\n",
tp->dev->name);
return -EINVAL;
}
- if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
write_op = tg3_write_mem;
else
write_op = tg3_write_indirect_reg32;
@@ -6549,6 +6516,10 @@ static int tg3_get_settings(struct net_d
{
struct tg3 *tp = netdev_priv(dev);
+ if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
+ tp->link_config.phy_is_low_power)
+ return -EAGAIN;
+
cmd->supported = (SUPPORTED_Autoneg);
if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
@@ -6565,10 +6536,8 @@ static int tg3_get_settings(struct net_d
cmd->supported |= SUPPORTED_FIBRE;
cmd->advertising = tp->link_config.advertising;
- if (netif_running(dev)) {
- cmd->speed = tp->link_config.active_speed;
- cmd->duplex = tp->link_config.active_duplex;
- }
+ cmd->speed = tp->link_config.active_speed;
+ cmd->duplex = tp->link_config.active_duplex;
cmd->port = 0;
cmd->phy_address = PHY_ADDR;
cmd->transceiver = 0;
@@ -6582,6 +6551,10 @@ static int tg3_set_settings(struct net_d
{
struct tg3 *tp = netdev_priv(dev);
+ if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
+ tp->link_config.phy_is_low_power)
+ return -EAGAIN;
+
if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
/* These are the only valid advertisement bits allowed. */
if (cmd->autoneg == AUTONEG_ENABLE &&
@@ -6606,9 +6579,7 @@ static int tg3_set_settings(struct net_d
tp->link_config.duplex = cmd->duplex;
}
- if (netif_running(dev))
- tg3_setup_phy(tp, 1);
-
+ tg3_setup_phy(tp, 1);
spin_unlock(&tp->tx_lock);
spin_unlock_irq(&tp->lock);
@@ -6688,9 +6659,6 @@ static int tg3_nway_reset(struct net_dev
u32 bmcr;
int r;
- if (!netif_running(dev))
- return -EAGAIN;
-
spin_lock_irq(&tp->lock);
r = -EINVAL;
tg3_readphy(tp, MII_BMCR, &bmcr);
@@ -6727,9 +6695,7 @@ static int tg3_set_ringparam(struct net_
(ering->tx_pending > TG3_TX_RING_SIZE - 1))
return -EINVAL;
- if (netif_running(dev))
- tg3_netif_stop(tp);
-
+ tg3_netif_stop(tp);
spin_lock_irq(&tp->lock);
spin_lock(&tp->tx_lock);
@@ -6741,12 +6707,9 @@ static int tg3_set_ringparam(struct net_
tp->rx_jumbo_pending = ering->rx_jumbo_pending;
tp->tx_pending = ering->tx_pending;
- if (netif_running(dev)) {
- tg3_halt(tp);
- tg3_init_hw(tp);
- tg3_netif_start(tp);
- }
-
+ tg3_halt(tp);
+ tg3_init_hw(tp);
+ tg3_netif_start(tp);
spin_unlock(&tp->tx_lock);
spin_unlock_irq(&tp->lock);
@@ -6766,9 +6729,7 @@ static int tg3_set_pauseparam(struct net
{
struct tg3 *tp = netdev_priv(dev);
- if (netif_running(dev))
- tg3_netif_stop(tp);
-
+ tg3_netif_stop(tp);
spin_lock_irq(&tp->lock);
spin_lock(&tp->tx_lock);
if (epause->autoneg)
@@ -6783,12 +6744,9 @@ static int tg3_set_pauseparam(struct net
tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
else
tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
-
- if (netif_running(dev)) {
- tg3_halt(tp);
- tg3_init_hw(tp);
- tg3_netif_start(tp);
- }
+ tg3_halt(tp);
+ tg3_init_hw(tp);
+ tg3_netif_start(tp);
spin_unlock(&tp->tx_lock);
spin_unlock_irq(&tp->lock);
@@ -8981,7 +8939,7 @@ static void __devexit tg3_remove_one(str
}
}
-static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
+static int tg3_suspend(struct pci_dev *pdev, u32 state)
{
struct net_device *dev = pci_get_drvdata(pdev);
struct tg3 *tp = netdev_priv(dev);
Index: kernel-2.6.spec
===================================================================
RCS file: /cvs/dist/rpms/kernel/FC-3/kernel-2.6.spec,v
retrieving revision 1.821.2.1
retrieving revision 1.821.2.2
diff -u -r1.821.2.1 -r1.821.2.2
--- kernel-2.6.spec 5 May 2005 20:13:34 -0000 1.821.2.1
+++ kernel-2.6.spec 5 May 2005 20:31:39 -0000 1.821.2.2
@@ -295,6 +295,8 @@
Patch1370: jwltest-e100-update-3_4_8-k2.patch
Patch1371: jwltest-ixgb-update-1_0_90-k2.patch
Patch1372: jwltest-ixgb-update-1_0_95-k2.patch
+Patch1373: jwltest-tg3-3_25.patch
+Patch1374: jwltest-tg3-exp1.patch
# USB bits
Patch1400: linux-2.6.10-usb-use_both_schemes.patch
@@ -600,6 +602,10 @@
%patch1371 -p1
# ixgb update to version 1.0.95-k2
%patch1372 -p1
+# tg3 update to 3.25
+%patch1373 -p1
+# tg3 -- experimental backtracking
+%patch1374 -p1
# USB Bits.
# Enable both old and new style USB initialisation.
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