rpms/oprofile/FC-5 oprofile-core.patch, NONE, 1.1 oprofile-core_2.patch, NONE, 1.1 oprofile.spec, 1.39, 1.40
fedora-cvs-commits at redhat.com
fedora-cvs-commits at redhat.com
Wed Dec 20 16:38:05 UTC 2006
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Author: wcohen
Update of /cvs/dist/rpms/oprofile/FC-5
In directory cvs.devel.redhat.com:/tmp/cvs-serv4541
Modified Files:
oprofile.spec
Added Files:
oprofile-core.patch oprofile-core_2.patch
Log Message:
Add Core and Core2 support. (#215729)
oprofile-core.patch:
events/Makefile.am | 1
events/i386/core/events | 115 ++++++++++++++++++++++++++++++++++++++++++++
events/i386/core/unit_masks | 67 +++++++++++++++++++++++++
libop/op_cpu_type.c | 1
libop/op_cpu_type.h | 1
libop/op_events.c | 1
module/x86/cpu_type.c | 4 +
utils/ophelp.c | 1
8 files changed, 191 insertions(+)
--- NEW FILE oprofile-core.patch ---
Index: events/Makefile.am
===================================================================
RCS file: /cvsroot/oprofile/oprofile/events/Makefile.am,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -r1.13 -r1.14
--- events/Makefile.am 22 Feb 2006 14:36:36 -0000 1.13
+++ events/Makefile.am 13 May 2006 13:55:02 -0000 1.14
@@ -11,6 +11,7 @@
i386/piii/events i386/piii/unit_masks \
i386/ppro/events i386/ppro/unit_masks \
i386/p6_mobile/events i386/p6_mobile/unit_masks \
+ i386/core/events i386/core/unit_masks \
ia64/ia64/events ia64/ia64/unit_masks \
ia64/itanium2/events ia64/itanium2/unit_masks \
ia64/itanium/events ia64/itanium/unit_masks \
Index: events/i386/core/events
===================================================================
RCS file: events/i386/core/events
diff -N events/i386/core/events
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ events/i386/core/events 13 May 2006 13:55:03 -0000 1.1
@@ -0,0 +1,115 @@
+# Core Solo / Duo events
+#
+# Architectural events
+#
+event:0x3c counters:0,1 um:nonhlt minimum:6000 name:CPU_CLK_UNHALTED : Unhalted clock cycles
+event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED : number of instructions retired
+event:0x2e counters:0,1 um:mesi minimum:6000 name:L2_RQSTS : number of L2 requests
+#
+# Model specific events
+#
+event:0x03 counters:0,1 um:zero minimum:500 name:LD_BLOCKS : number of store buffer blocks
+event:0x04 counters:0,1 um:zero minimum:500 name:SB_DRAINS : number of store buffer drain cycles
+event:0x05 counters:0,1 um:zero minimum:500 name:MISALIGN_MEM_REF : number of misaligned data memory references
+event:0x06 counters:0,1 um:zero minimum:500 name:SEGMENT_REG_LOADS : number of segment register loads
+event:0x07 counters:0,1 um:kni_prefetch minimum:500 name:EMON_KNI_PREF_DISPATCHED : number of SSE pre-fetch/weakly ordered insns retired
+event:0x10 counters:0 um:zero minimum:3000 name:FLOPS : number of computational FP operations executed
+event:0x11 counters:1 um:zero minimum:500 name:FP_ASSIST : number of FP exceptions handled by microcode
+event:0x12 counters:1 um:zero minimum:1000 name:MUL : number of multiplies
+event:0x13 counters:1 um:zero minimum:500 name:DIV : number of divides
+event:0x14 counters:0 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy
+event:0x21 counters:0,1 um:zero minimum:500 name:L2_ADS : number of L2 address strobes
+event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
+event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
+event:0x24 counters:0,1 um:zero minimum:500 name:L2_LINES_IN : number of allocated lines in L2
+event:0x25 counters:0,1 um:zero minimum:500 name:L2_M_LINES_INM : number of modified lines allocated in L2
+event:0x26 counters:0,1 um:zero minimum:500 name:L2_LINES_OUT : number of recovered lines from L2
+event:0x27 counters:0,1 um:zero minimum:500 name:L2_M_LINES_OUTM : number of modified lines removed from L2
+event:0x28 counters:0,1 um:mesi minimum:500 name:L2_IFETCH : number of L2 instruction fetches
+event:0x29 counters:0,1 um:mesi minimum:500 name:L2_LD : number of L2 data loads
+event:0x2a counters:0,1 um:mesi minimum:500 name:L2_ST : number of L2 data stores
+event:0x30 counters:0,1 um:mesi minimum:500 name:L2_REJECT_CYCLES : Cycles L2 is busy and rejecting new requests
+event:0x32 counters:0,1 um:mesi minimum:500 name:L2_NO_REQUEST_CYCLES : Cycles there is no request to access L2
+event:0x3a counters:0,1 um:est_trans minimum:500 name:EST_TRANS_ALL : Intel(tm) Enhanced SpeedStep(r) Technology transitions
+event:0x3b counters:0,1 um:xc0 minimum:500 name:THERMAL_TRIP : Duration in a thremal trip based on the current core clock
+event:0x40 counters:0,1 um:mesi minimum:500 name:DCACHE_CACHE_LD : L1 cacheable data read operations
+event:0x41 counters:0,1 um:mesi minimum:500 name:DCACHE_CACHE_ST : L1 cacheable data write operations
+event:0x42 counters:0,1 um:mesi minimum:500 name:DCACHE_CACHE_LOCK : L1 cacheable lock read operations to invalid state
+event:0x43 counters:0,1 um:one minimum:500 name:DATA_MEM_REFS : all L1 memory references, cachable and non
+event:0x44 counters:0,1 um:two minimum:500 name:DATA_MEM_CACHE_REFS : L1 data cacheable read and write operations
+event:0x45 counters:0,1 um:x0f minimum:500 name:DCACHE_REPL : L1 data cache line replacements
+event:0x46 counters:0,1 um:zero minimum:500 name:DCACHE_M_REPL : L1 data M-state cache line allocated
+event:0x47 counters:0,1 um:zero minimum:500 name:DCACHE_M_EVICT : L1 data M-state cache line evicted
+event:0x48 counters:0,1 um:dc_pend_miss minimum:500 name:DCACHE_PEND_MISS : Weighted cycles of L1 miss outstanding
+event:0x49 counters:0,1 um:zero minimum:500 name:DTLB_MISS : Data references that missed TLB
+event:0x4b counters:0,1 um:sse_miss minimum:500 name:SSE_PREF_MISS : SSE instructions that missed all caches
+event:0x4f counters:0,1 um:zero minimum:500 name:L1_PREF_REQ : L1 prefetch requests due to DCU cache misses
+#
+event:0x60 counters:0,1 um:zero minimum:500 name:BUS_REQ_OUTSTANDING : weighted number of outstanding bus requests
+event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : External bus cycles this processor is driving BNR pin
+event:0x62 counters:0,1 um:zero minimum:500 name:BUS_DRDY_CLOCKS : External bus cycles DRDY is asserted
+event:0x63 counters:0,1 um:zero minimum:500 name:BUS_LOCK_CLOCKS : External bus cycles LOCK is asserted
+event:0x64 counters:0,1 um:x40 minimum:500 name:BUS_DATA_RCV : External bus cycles this processor is receiving data
+event:0x65 counters:0,1 um:zero minimum:500 name:BUS_TRAN_BRD : number of burst read transactions
+event:0x66 counters:0,1 um:zero minimum:500 name:BUS_TRAN_RFO : number of completed read for ownership transactions
+event:0x67 counters:0,1 um:xc0 minimum:500 name:BUS_TRAN_WB : number of completed writeback transactions
+event:0x68 counters:0,1 um:zero minimum:500 name:BUS_TRAN_IFETCH : number of completed instruction fetch transactions
+event:0x69 counters:0,1 um:zero minimum:500 name:BUS_TRAN_INVAL : number of completed invalidate transactions
+event:0x6a counters:0,1 um:zero minimum:500 name:BUS_TRAN_PWR : number of completed partial write transactions
+event:0x6b counters:0,1 um:zero minimum:500 name:BUS_TRANS_P : number of completed partial transactions
+event:0x6c counters:0,1 um:zero minimum:500 name:BUS_TRANS_IO : number of completed I/O transactions
+event:0x6d counters:0,1 um:x20 minimum:500 name:BUS_TRANS_DEF : number of completed defer transactions
+event:0x6e counters:0,1 um:xc0 minimum:500 name:BUS_TRAN_BURST : number of completed burst transactions
+event:0x6f counters:0,1 um:xc0 minimum:500 name:BUS_TRAN_MEM : number of completed memory transactions
+event:0x70 counters:0,1 um:xc0 minimum:500 name:BUS_TRAN_ANY : number of any completed bus transactions
+event:0x77 counters:0,1 um:zero minimum:500 name:BUS_SNOOPS : External bus cycles
+event:0x78 counters:0,1 um:one minimum:500 name:DCU_SNOOP_TO_SHARE : DCU snoops to share-state L1 cache line due to L1 misses
+event:0x7d counters:0,1 um:zero minimum:500 name:BUS_NOT_IN_USE : Number of cycles there is no transaction from the core
+event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : Number of bus cycles during bus snoop stall
+event:0x80 counters:0,1 um:zero minimum:500 name:ICACHE_READS : number of instruction fetches
+event:0x81 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : number of instruction fetch misses
+event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
+event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
+event:0x88 counters:0,1 um:zero minimum:3000 name:BR_INST_EXEC : Branch instructions executed (not necessarily retired)
+event:0x89 counters:0,1 um:zero minimum:3000 name:BR_MISSP_EXEC : Branch instructions executed that were mispredicted at execution
+event:0x8a counters:0,1 um:zero minimum:3000 name:BR_BAC_MISSP_EXEC : Branch instructions executed that were mispredicted at Front End (BAC)
+event:0x8b counters:0,1 um:zero minimum:3000 name:BR_CND_EXEC : Conditional Branch instructions executed
+event:0x8c counters:0,1 um:zero minimum:3000 name:BR_CND_MISSP_EXEC : Conditional Branch instructions executed that were mispredicted
+event:0x8d counters:0,1 um:zero minimum:3000 name:BR_IND_EXEC : Indirect Branch instructions executed
+event:0x8e counters:0,1 um:zero minimum:3000 name:BR_IND_MISSP_EXEC : Indirect Branch instructions executed that were mispredicted
+event:0x8f counters:0,1 um:zero minimum:3000 name:BR_RET_EXEC : Return Branch instructions executed
+event:0x90 counters:0,1 um:zero minimum:3000 name:BR_RET_MISSP_EXEC : Return Branch instructions executed that were mispredicted at Execution
+event:0x91 counters:0,1 um:zero minimum:3000 name:BR_RET_BAC_MISSP_EXEC :Return Branch instructions executed that were mispredicted at Front End (BAC)
+event:0x92 counters:0,1 um:zero minimum:3000 name:BR_CALL_EXEC : CALL instruction executed
+event:0x93 counters:0,1 um:zero minimum:3000 name:BR_CALL_MISSP_EXEC : CALL instruction executed and miss predicted
+event:0x94 counters:0,1 um:zero minimum:3000 name:BR_IND_CALL_EXEC : Indirect CALL instruction executed
+event:0xa2 counters:0,1 um:zero minimum:500 name:RESOURCE_STALLS : cycles during resource related stalls
+event:0xb0 counters:0,1 um:zero minimum:500 name:MMX_INSTR_EXEC : number of MMX instructions executed (not MOVQ and MOVD)
+event:0xb1 counters:0,1 um:zero minimum:3000 name:SIMD_SAT_INSTR_EXEC : number of SIMD saturating instructions executed
+event:0xb3 counters:0,1 um:mmx_instr_type_exec minimum:3000 name:MMX_INSTR_TYPE_EXEC : number of MMX packing instructions
+event:0xc1 counters:0 um:zero minimum:3000 name:COMP_FLOP_RET : number of computational FP operations retired
+event:0xc2 counters:0,1 um:zero minimum:6000 name:UOPS_RETIRED : number of UOPs retired
+event:0xc3 counters:0,1 um:zero minimum:500 name:SMC_DETECTED : number of times self-modifying code condition is detected
+event:0xc4 counters:0,1 um:zero minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired
+event:0xc6 counters:0,1 um:zero minimum:500 name:CYCLES_INT_MASKED : cycles interrupts are disabled
+event:0xc7 counters:0,1 um:zero minimum:500 name:CYCLES_INT_PENDING_AND_MASKED : cycles interrupts are disabled with pending interrupts
+event:0xc8 counters:0,1 um:zero minimum:500 name:HW_INT_RX : number of hardware interrupts received
+event:0xc9 counters:0,1 um:zero minimum:500 name:BR_TAKEN_RETIRED : number of taken branches retired
+event:0xca counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_TAKEN_RET : number of taken mispredictions branches retired
+event:0xcc counters:0,1 um:mmx_trans minimum:3000 name:FP_MMX_TRANS : MMX-floating point transitions
+event:0xcd counters:0,1 um:zero minimum:500 name:MMX_ASSIST : number of EMMS instructions executed
+event:0xce counters:0,1 um:zero minimum:3000 name:MMX_INSTR_RET : number of MMX instructions retired
+event:0xd0 counters:0,1 um:zero minimum:6000 name:INST_DECODED : number of instructions decoded
+event:0xd7 counters:0,1 um:zero minimum:3000 name:ESP_UOPS : Number of ESP folding instructions decoded
+event:0xd8 counters:0,1 um:sse_sse2_inst_retired minimum:3000 name:EMON_SSE_SSE2_INST_RETIRED : Streaming SIMD Extensions Instructions Retired
+event:0xd9 counters:0,1 um:sse_sse2_inst_retired minimum:3000 name:EMON_SSE_SSE2_COMP_INST_RETIRED : Computational SSE Instructions Retired
+event:0xda counters:0,1 um:fused minimum:3000 name:EMON_FUSED_UOPS_RET : Number of retired fused micro-ops
+event:0xdb counters:0,1 um:zero minimum:3000 name:EMON_UNFUSION : Number of unfusion events in the ROB, happened on a FP exception to a fused uOp
+event:0xe0 counters:0,1 um:zero minimum:500 name:BR_INST_DECODED : number of branch instructions decoded
+event:0xe2 counters:0,1 um:zero minimum:500 name:BTB_MISSES : number of branches that miss the BTB
+event:0xe4 counters:0,1 um:zero minimum:500 name:BR_BOGUS : number of bogus branches
+event:0xe6 counters:0,1 um:zero minimum:500 name:BACLEARS : number of times BACLEAR is asserted
+event:0xf0 counters:0,1 um:zero minimum:3000 name:EMON_PREF_RQSTS_UP : Number of upward prefetches issued
+event:0xf8 counters:0,1 um:zero minimum:3000 name:EMON_PREF_RQSTS_DN : Number of downward prefetches issued
Index: events/i386/core/unit_masks
===================================================================
RCS file: events/i386/core/unit_masks
diff -N events/i386/core/unit_masks
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ events/i386/core/unit_masks 13 May 2006 13:55:03 -0000 1.1
@@ -0,0 +1,67 @@
+# Core Solo / Core Duo possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:one type:mandatory default:0x1
+ 0x1 No unit mask
+name:two type:mandatory default:0x2
+ 0x2 No unit mask
+name:x0f type:mandatory default:0xf
+ 0xf No unit mask
+name:x20 type:mandatory default:0x20
+ 0x20 No unit mask
+name:x40 type:mandatory default:0x40
+ 0x40 No unit mask
+name:xc0 type:mandatory default:0xc0
+ 0xc0 No unit mask
+name:nonhlt type:exclusive default:0x0
+ 0x0 Unhalted core cycles
+ 0x1 Unhalted bus cycles
+ 0x2 Unhalted bus cycles of this core while the other core is halted
+name:mesi type:bitmask default:0x0f
+ 0x08 (M)odified cache state
+ 0x04 (E)xclusive cache state
+ 0x02 (S)hared cache state
+ 0x01 (I)nvalid cache state
+ 0x0f All cache states
+ 0x10 HW prefetched line only
+ 0x20 all prefetched line w/o regarding mask 0x10.
+name:est_trans type:exclusive default:0x00
+ 0x00 any transitions
+ 0x10 Intel(tm) Enhanced SpeedStep(r) Technology frequency transitions
+ 0x20 any transactions
+name:kni_prefetch type:exclusive default:0x0
+ 0x00 prefetch NTA
+ 0x01 prefetch T1
+ 0x02 prefetch T2
+ 0x03 weakly-ordered stores
+# this bitmask can seems weirds but is correct, note there is no way to only
+# count scalar SIMD instructions
+name:sse_sse2_inst_retired type:exclusive default:0x0
+ 0x00 SSE Packed Single
+ 0x01 SSE Scalar-Single
+ 0x02 SSE2 Packed-Double
+ 0x03 SSE2 Scalar-Double
+name:mmx_instr_type_exec type:bitmask default:0x3f
+ 0x01 MMX packed multiplies
+ 0x02 MMX packed shifts
+ 0x04 MMX pack operations
+ 0x08 MMX unpack operations
+ 0x10 MMX packed logical
+ 0x20 MMX packed arithmetic
+ 0x3f all of the above
+name:mmx_trans type:exclusive default:0x0
+ 0x00 MMX->float operations
+ 0x01 float->MMX operations
+name:fused type:exclusive default:0x0
+ 0x00 All fused micro-ops
+ 0x01 Only load+Op micro-ops
+ 0x02 Only std+sta micro-ops
+name:dc_pend_miss type:exclusive default:0x0
+ 0x00 Weighted cycles
+ 0x01 Duration of cycles
+name:sse_miss type:exclusive default:0x0
+ 0x00 PREFETCHNTA
+ 0x01 PREFETCHT1
+ 0x02 PREFETCHT2
+ 0x03 SSE streaming store instructions
Index: libop/op_cpu_type.c
===================================================================
RCS file: /cvsroot/oprofile/oprofile/libop/op_cpu_type.c,v
retrieving revision 1.33
retrieving revision 1.34
diff -u -r1.33 -r1.34
--- libop/op_cpu_type.c 22 Feb 2006 14:36:40 -0000 1.33
+++ libop/op_cpu_type.c 13 May 2006 13:55:03 -0000 1.34
@@ -57,5 +57,6 @@
{ "NEC VR5500", "mips/vr5500", CPU_MIPS_VR5500, 2 },
{ "e500", "ppc/e500", CPU_PPC_E500, 4 },
+ { "Core Solo / Duo", "i386/core", CPU_CORE, 2 },
};
static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
Index: libop/op_cpu_type.h
===================================================================
RCS file: /cvsroot/oprofile/oprofile/libop/op_cpu_type.h,v
retrieving revision 1.26
retrieving revision 1.27
diff -u -r1.26 -r1.27
--- libop/op_cpu_type.h 22 Feb 2006 14:36:40 -0000 1.26
+++ libop/op_cpu_type.h 13 May 2006 13:55:03 -0000 1.27
@@ -53,5 +53,6 @@
CPU_MIPS_VR5500, /**< MIPS VR5500, VR5532 and VR7701 */
CPU_PPC_E500, /**< e500 */
+ CPU_CORE, /**< Core Solo / Duo series */
MAX_CPU_TYPE
} op_cpu;
Index: libop/op_events.c
===================================================================
RCS file: /cvsroot/oprofile/oprofile/libop/op_events.c,v
retrieving revision 1.69
retrieving revision 1.70
diff -u -r1.69 -r1.70
--- libop/op_events.c 22 Feb 2006 14:36:40 -0000 1.69
+++ libop/op_events.c 13 May 2006 13:55:03 -0000 1.70
@@ -743,6 +743,7 @@
case CPU_PII:
case CPU_PIII:
case CPU_P6_MOBILE:
+ case CPU_CORE:
case CPU_ATHLON:
case CPU_HAMMER:
descr->name = "CPU_CLK_UNHALTED";
Index: module/x86/cpu_type.c
===================================================================
RCS file: /cvsroot/oprofile/oprofile/module/x86/cpu_type.c,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -r1.18 -r1.19
--- module/x86/cpu_type.c 9 Aug 2005 11:26:06 -0000 1.18
+++ module/x86/cpu_type.c 13 May 2006 13:55:03 -0000 1.19
@@ -173,6 +173,10 @@
return CPU_RTC;
case 6:
/* A P6-class processor */
+ if (model == 14)
+ return CPU_CORE;
+ if (model > 0xd)
+ return CPU_RTC;
if (model > 5)
return CPU_PIII;
else if (model > 2)
Index: utils/ophelp.c
===================================================================
RCS file: /cvsroot/oprofile/oprofile/utils/ophelp.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -r1.5 -r1.6
--- utils/ophelp.c 22 Feb 2006 14:36:41 -0000 1.5
+++ utils/ophelp.c 13 May 2006 13:55:03 -0000 1.6
@@ -381,6 +381,7 @@
case CPU_P6_MOBILE:
case CPU_P4:
case CPU_P4_HT2:
+ case CPU_CORE:
printf("See Intel Architecture Developer's Manual Volume 3, Appendix A and\n"
"Intel Architecture Optimization Reference Manual (730795-001)\n\n");
break;
oprofile-core_2.patch:
events/Makefile.am | 1
events/i386/core_2/events | 133 ++++++++++++++++++++++++++++
events/i386/core_2/unit_masks | 197 ++++++++++++++++++++++++++++++++++++++++++
libop/op_cpu_type.c | 1
libop/op_cpu_type.h | 1
5 files changed, 333 insertions(+)
--- NEW FILE oprofile-core_2.patch ---
--- oprofile-0.8.1/libop/op_cpu_type.c.core2 2006-09-13 10:40:08.000000000 -0400
+++ oprofile-0.8.1/libop/op_cpu_type.c 2006-09-13 10:40:08.000000000 -0400
@@ -48,6 +48,7 @@
{ "ppc64 POWER5+", "ppc64/power5+", CPU_PPC64_POWER5p, 6 },
{ "ppc64 970", "ppc64/970", CPU_PPC64_970, 8 },
{ "Core Solo / Duo", "i386/core", CPU_CORE, 2 },
+ { "Core 2", "i386/core_2", CPU_CORE_2, 2 },
};
static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
--- oprofile-0.8.1/libop/op_cpu_type.h.core2 2006-09-13 10:40:08.000000000 -0400
+++ oprofile-0.8.1/libop/op_cpu_type.h 2006-09-13 10:40:08.000000000 -0400
@@ -44,6 +44,7 @@
CPU_PPC64_POWER5p, /**< ppc64 Power5+ family */
CPU_PPC64_970, /**< ppc64 970 family */
CPU_CORE, /**< Core Solo / Duo series */
+ CPU_CORE_2, /**< Intel Core 2 */
MAX_CPU_TYPE
} op_cpu;
--- oprofile-0.8.1/events/Makefile.am.core2 2006-09-13 10:40:08.000000000 -0400
+++ oprofile-0.8.1/events/Makefile.am 2006-09-13 10:40:08.000000000 -0400
@@ -5,6 +5,7 @@
alpha/ev6/events alpha/ev6/unit_masks \
alpha/pca56/events alpha/pca56/unit_masks \
i386/athlon/events i386/athlon/unit_masks \
+ i386/core_2/events i386/core_2/unit_masks \
i386/p4/events i386/p4-ht/events \
i386/p4-ht/unit_masks i386/p4/unit_masks \
i386/pii/events i386/pii/unit_masks \
--- /dev/null 2006-09-04 18:13:30.575848296 -0400
+++ oprofile-0.8.1/events/i386/core_2/events 2006-09-13 10:44:46.000000000 -0400
@@ -0,0 +1,133 @@
+# Core 2 events
+#
+# Architectural events
+#
+event:0x3c counters:0,1 um:nonhlt minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
+event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED.ANY_P : number of instructions retired
+event:0x2e counters:0,1 um:core_mesi minimum:6000 name:L2_RQSTS : number of L2 requests
+event:0x2e counters:0,1 um:x41 minimum:6000 name:L2_RQSTS.SELF.DEMAND.I_STATE_L2 : L2 cache demand requests from this core that missed the L2
+event:0x2e counters:0,1 um:x4f minimum:6000 name:L2_RQSTS.SELF.DEMAND.I_STATE : L2 cache demand requests from this core
+#
+# Model specific events
+#
+event:0x03 counters:0,1 um:load_block minimum:500 name:LOAD_BLOCK : events pertaining to loads
+event:0x04 counters:0,1 um:store_block minimum:500 name:STORE_BLOCK : events pertaining to stores
+event:0x05 counters:0,1 um:zero minimum:500 name:MISALIGN_MEM_REF : number of misaligned data memory references
+event:0x06 counters:0,1 um:zero minimum:500 name:SEGMENT_REG_LOADS : number of segment register loads
+event:0x07 counters:0,1 um:sse_prefetch minimum:500 name:SSE_PRE_EXEC : number of SSE pre-fetch/weakly ordered insns retired
+event:0x08 counters:0,1 um:dtlb_miss minimum:500 name:DTLB_MISSES : DTLB miss events
+event:0x09 counters:0,1 um:memory_dis minimum:1000 name:MEMORY_DISAMBIGUATION : Memory disambiguation reset cycles.
+event:0x0c counters:0,1 um:page_walks minimum:500 name:PAGE_WALKS : Page table walk events
+event:0x10 counters:0,1 um:zero minimum:3000 name:FLOPS : number of FP computational micro-ops executed
+event:0x11 counters:0,1 um:zero minimum:500 name:FP_ASSIST : number of FP assists
+event:0x12 counters:0,1 um:zero minimum:1000 name:MUL : number of multiplies
+event:0x13 counters:0,1 um:zero minimum:500 name:DIV : number of divides
+event:0x14 counters:0,1 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy
+event:0x18 counters:0,1 um:zero minimum:1000 name:IDLE_DURING_DIV : cycles divider is busy and all other execution units are idle.
+event:0x19 counters:0,1 um:delayed_bypass minimum:1000 name:DELAYED_BYPASS : Delayed bypass events
+event:0x21 counters:0,1 um:core minimum:500 name:L2_ADS : Cycles the L2 address bus is in use.
+event:0x23 counters:0,1 um:core minimum:500 name:L2_DBUS_BUSY_RD : Cycles the L2 transfers data to the core.
+event:0x24 counters:0,1 um:core_prefetch minimum:500 name:L2_LINES_IN : number of allocated lines in L2
+event:0x25 counters:0,1 um:core_prefetch minimum:500 name:L2_M_LINES_IN : number of modified lines allocated in L2
+event:0x26 counters:0,1 um:core_prefetch minimum:500 name:L2_LINES_OUT : number of recovered lines from L2
+event:0x27 counters:0,1 um:core_prefetch minimum:500 name:L2_M_LINES_OUT : number of modified lines removed from L2
+event:0x28 counters:0,1 um:core_mesi minimum:500 name:L2_IFETCH : number of L2 cacheable instruction fetches
+event:0x29 counters:0,1 um:core_prefetch_mesi minimum:500 name:L2_LD : number of L2 data loads
+event:0x2a counters:0,1 um:core_mesi minimum:500 name:L2_ST : number of L2 data stores
+event:0x2b counters:0,1 um:core_mesi minimum:500 name:L2_LOCK : number of locked L2 data accesses
+event:0x2e counters:0,1 um:core_prefetch_mesi minimum:500 name:L2_RQSTS : number of L2 cache requests
+event:0x30 counters:0,1 um:core_prefetch_mesi minimum:500 name:L2_REJECT_BUSQ : Rejected L2 cache requests
+event:0x32 counters:0,1 um:core minimum:500 name:L2_NO_REQ : Cycles no L2 cache requests are pending
+event:0x3a counters:0,1 um:zero minimum:500 name:EIST_TRANS_ALL : Intel(tm) Enhanced SpeedStep(r) Technology transitions
+event:0x3b counters:0,1 um:xc0 minimum:500 name:THERMAL_TRIP : Number of thermal trips
+event:0x40 counters:0,1 um:mesi minimum:500 name:L1D_CACHE_LD : L1 cacheable data read operations
+event:0x41 counters:0,1 um:mesi minimum:500 name:L1D_CACHE_ST : L1 cacheable data write operations
+event:0x42 counters:0,1 um:mesi minimum:500 name:L1D_CACHE_LOCK : L1 cacheable lock read operations
+event:0x42 counters:0,1 um:x10 minimum:500 name:L1D_CACHE_LOCK_DURATION : Duration of L1 data cacheable locked operations
+event:0x43 counters:0,1 um:x10 minimum:500 name:L1D_ALL_REF : All references to the L1 data cache
+event:0x43 counters:0,1 um:two minimum:500 name:L1D_ALL_CACHE_REF : L1 data cacheable reads and writes
+event:0x45 counters:0,1 um:x0f minimum:500 name:L1D_REPL : Cache lines allocated in the L1 data cache
+event:0x46 counters:0,1 um:zero minimum:500 name:L1D_M_REPL : Modified cache lines allocated in the L1 data cache
+event:0x47 counters:0,1 um:zero minimum:500 name:L1D_M_EVICT : Modified cache lines evicted from the L1 data cache
+event:0x48 counters:0,1 um:dc_pend_miss minimum:500 name:L1D_PEND_MISS : Weighted cycles of L1 miss outstanding
+event:0x49 counters:0,1 um:l1d_split minimum:500 name:L1D_SPLIT : Cache line split load/stores
+event:0x4b counters:0,1 um:sse_miss minimum:500 name:SSE_PREF_MISS : SSE instructions that missed all caches
+event:0x4c counters:0,1 um:zero minimum:500 name:LOAD_HIT_PRE : Load operations conflicting with a software prefetch to the same address
+event:0x4e counters:0,1 um:x10 minimum:500 name:L1D_PREFETCH : L1 data cache prefetch requests
+#
+event:0x60 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_REQ_OUTSTANDING : Outstanding cacheable data read bus requests duration
+event:0x61 counters:0,1 um:bus_agents minimum:500 name:BUS_BNR_DRV : Number of Bus Not Ready signals asserted
+event:0x62 counters:0,1 um:bus_agents minimum:500 name:BUS_DRDY_CLOCKS : Bus cycles when data is sent on the bus
+event:0x63 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_LOCK_CLOCKS : Bus cycles when a LOCK signal is asserted
+event:0x64 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_DATA_RCV : Bus cycles while processor receives data
+event:0x65 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_BRD : Burst read bus transactions
+event:0x66 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_RFO : number of completed read for ownership transactions
+event:0x67 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_WB : number of explicit writeback bus transactions
+event:0x68 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_IFETCH : number of instruction fetch transactions
+event:0x69 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_INVAL : number of invalidate transactions
+event:0x6a counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_PWR : number of partial write bus transactions
+event:0x6b counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRANS_P : number of partial bus transactions
+event:0x6c counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRANS_IO : number of I/O bus transactions
+event:0x6d counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRANS_DEF : number of completed defer transactions
+event:0x6e counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_BURST : number of completed burst transactions
+event:0x6f counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_MEM : number of completed memory transactions
+event:0x70 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_ANY : number of any completed bus transactions
+event:0x77 counters:0,1 um:bus_agents_and_snoop minimum:500 name:EXT_SNOOP : External snoops
+event:0x78 counters:0,1 um:core_and_snoop minimum:500 name:CMP_SNOOP : L1 data cache is snooped by other core
+event:0x7a counters:0,1 um:bus_agents minimum:500 name:BUS_HIT_DRV : HIT signal asserted
+event:0x7b counters:0,1 um:bus_agents minimum:500 name:BUS_HITM_DRV : HITM signal asserted
+event:0x7d counters:0,1 um:core minimum:500 name:BUSQ_EMPTY : Bus queue is empty
+event:0x7e counters:0,1 um:core_and_bus_agents minimum:500 name:SNOOP_STALL_DRV : Bus stalled for snoops
+event:0x7f counters:0,1 um:core minimum:500 name:BUS_IO_WAIT : IO requests waiting in the bus queue
+event:0x80 counters:0,1 um:zero minimum:500 name:L1I_READS : number of instruction fetches
+event:0x81 counters:0,1 um:zero minimum:500 name:L1I_MISSES : number of instruction fetch misses
+event:0x82 counters:0,1 um:itlb_miss minimum:500 name:ITLB : number of ITLB misses
+event:0x83 counters:0,1 um:two minimum:500 name:INST_QUEUE.FULL : cycles during which the instruction queue is full
+event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
+event:0x88 counters:0,1 um:zero minimum:3000 name:BR_INST_EXEC : Branch instructions executed (not necessarily retired)
+event:0x89 counters:0,1 um:zero minimum:3000 name:BR_MISSP_EXEC : Branch instructions executed that were mispredicted at execution
+event:0x8a counters:0,1 um:zero minimum:3000 name:BR_BAC_MISSP_EXEC : Branch instructions executed that were mispredicted at Front End (BAC)
+event:0x8b counters:0,1 um:zero minimum:3000 name:BR_CND_EXEC : Conditional Branch instructions executed
+event:0x8c counters:0,1 um:zero minimum:3000 name:BR_CND_MISSP_EXEC : Conditional Branch instructions executed that were mispredicted
+event:0x8d counters:0,1 um:zero minimum:3000 name:BR_IND_EXEC : Indirect Branch instructions executed
+event:0x8e counters:0,1 um:zero minimum:3000 name:BR_IND_MISSP_EXEC : Indirect Branch instructions executed that were mispredicted
+event:0x8f counters:0,1 um:zero minimum:3000 name:BR_RET_EXEC : Return Branch instructions executed
+event:0x90 counters:0,1 um:zero minimum:3000 name:BR_RET_MISSP_EXEC : Return Branch instructions executed that were mispredicted at Execution
+event:0x91 counters:0,1 um:zero minimum:3000 name:BR_RET_BAC_MISSP_EXEC :Return Branch instructions executed that were mispredicted at Front End (BAC)
+event:0x92 counters:0,1 um:zero minimum:3000 name:BR_CALL_EXEC : CALL instruction executed
+event:0x93 counters:0,1 um:zero minimum:3000 name:BR_CALL_MISSP_EXEC : CALL instruction executed and miss predicted
+event:0x94 counters:0,1 um:zero minimum:3000 name:BR_IND_CALL_EXEC : Indirect CALL instruction executed
+event:0x97 counters:0,1 um:zero minimum:3000 name:BR_TKN_BUBBLE_1 : Branch predicted taken with bubble 1
+event:0x98 counters:0,1 um:zero minimum:3000 name:BR_TKN_BUBBLE_2 : Branch predicted taken with bubble 2
+event:0xa0 counters:0,1 um:zero minimum:1000 name:RS_UOPS_DISPATCHED : Micro-ops dispatched for execution
+event:0xaa counters:0,1 um:macro_insts minimum:500 name:MACRO_INSTS : instructions decoded
+event:0xab counters:0,1 um:esp minimum:500 name:ESP : ESP register events
+event:0xb0 counters:0,1 um:zero minimum:500 name:SIMD_UOPS_EXEC : SIMD micro-ops executed (excluding stores)
+event:0xb1 counters:0,1 um:zero minimum:3000 name:SIMD_SAT_UOP_EXEC : number of SIMD saturating instructions executed
+event:0xb3 counters:0,1 um:simd_instr_type_exec minimum:3000 name:SIMD_UOP_TYPE_EXEC : number of SIMD packing instructions
+event:0xc0 counters:0,1 um:inst_retired minimum:6000 name:INST_RETIRED : number of instructions retired
+event:0xc1 counters:0,1 um:x87_ops_retired minimum:500 name:X87_OPS_RETIRED : number of computational FP operations retired
+event:0xc2 counters:0,1 um:uops_retired minimum:6000 name:UOPS_RETIRED : number of UOPs retired
+event:0xc3 counters:0,1 um:machine_nukes minimum:500 name:MACHINE_NUKES.SMC : number of pipeline flushing events
+event:0xc4 counters:0,1 um:br_inst_retired minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired (precise)
+event:0xc6 counters:0,1 um:cycles_int_masked minimum:500 name:CYCLES_INT_MASKED : cycles interrupts are disabled
+event:0xc7 counters:0,1 um:simd_inst_retired minimum:500 name:SIMD_INST_RETIRED : SSE/SSE2 instructions retired
+event:0xc8 counters:0,1 um:zero minimum:500 name:HW_INT_RCV : number of hardware interrupts received
+event:0xc9 counters:0,1 um:zero minimum:500 name:ITLB_MISS_RETIRED : Retired instructions that missed the ITLB
+event:0xca counters:0,1 um:simd_comp_inst_retired minimum:500 name:SIMD_COMP_INST_RETIRED : Retired computational SSE/SSE2 instructions
+event:0xcb counters:0,1 um:mem_load_retired minimum:500 name:MEM_LOAD_RETIRED : Retired loads
+event:0xcc counters:0,1 um:mmx_trans minimum:3000 name:FP_MMX_TRANS : MMX-floating point transitions
+event:0xcd counters:0,1 um:zero minimum:500 name:MMX_ASSIST : number of EMMS instructions executed
+event:0xce counters:0,1 um:zero minimum:500 name:SIMD_INSTR_RET : number of SIMD instructions retired
+event:0xcf counters:0,1 um:zero minimum:500 name:SIMD_SAT_INSTR_RET : number of saturated arithmetic instructions retired
+event:0xd2 counters:0,1 um:rat_stalls minimum:6000 name:RAT_STALLS : Partial register stall cycles
+event:0xd4 counters:0,1 um:seg_regs minimum:500 name:SEG_RENAME_STALLS : Segment rename stalls
+event:0xd5 counters:0,1 um:seg_regs minimum:500 name:SEG_RENAMES : Segment renames
+event:0xdc counters:0,1 um:resource_stalls minimum:3000 name:RESOURCE_STALLS : Cycles during which resource stalls occur
+event:0xe0 counters:0,1 um:zero minimum:500 name:BR_INST_DECODED : number of branch instructions decoded
+event:0xe4 counters:0,1 um:zero minimum:500 name:BR_BOGUS : number of bogus branches
+event:0xe6 counters:0,1 um:zero minimum:500 name:BACLEARS : number of times BACLEAR is asserted
+event:0xf0 counters:0,1 um:zero minimum:3000 name:PREF_RQSTS_UP : Number of upward prefetches issued
+event:0xf8 counters:0,1 um:zero minimum:3000 name:PREF_RQSTS_DN : Number of downward prefetches issued
--- /dev/null 2006-09-04 18:13:30.575848296 -0400
+++ oprofile-0.8.1/events/i386/core_2/unit_masks 2006-09-13 10:44:46.000000000 -0400
@@ -0,0 +1,197 @@
+# Core 2 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+#name:one type:mandatory default:0x1
+# 0x1 No unit mask
+name:two type:mandatory default:0x2
+ 0x2 No unit mask
+name:x0f type:mandatory default:0xf
+ 0xf No unit mask
+name:x10 type:mandatory default:0x10
+ 0x10 No unit mask
+#name:x20 type:mandatory default:0x20
+# 0x20 No unit mask
+#name:x40 type:mandatory default:0x40
+# 0x40 No unit mask
+name:x41 type:mandatory default:0x41
+ 0x41 No unit mask
+name:x4f type:mandatory default:0x4f
+ 0x4f No unit mask
+name:xc0 type:mandatory default:0xc0
+ 0xc0 No unit mask
+name:nonhlt type:exclusive default:0x0
+ 0x0 Unhalted core cycles
+ 0x1 Unhalted bus cycles
+ 0x2 Unhalted bus cycles of this core while the other core is halted
+name:mesi type:bitmask default:0x0f
+ 0x08 (M)ESI: Modified
+ 0x04 M(E)SI: Exclusive
+ 0x02 ME(S)I: Shared
+ 0x01 MES(I): Invalid
+name:sse_prefetch type:exclusive default:0x0
+ 0x00 prefetch NTA instructions executed.
+ 0x01 prefetch T1 instructions executed.
+ 0x02 prefetch T1 and T2 instructions executed.
+ 0x03 SSE weakly-ordered stores
+name:simd_instr_type_exec type:bitmask default:0x3f
+ 0x01 SIMD packed multiplies
+ 0x02 SIMD packed shifts
+ 0x04 SIMD pack operations
+ 0x08 SIMD unpack operations
+ 0x10 SIMD packed logical
+ 0x20 SIMD packed arithmetic
+ 0x3f all of the above
+name:mmx_trans type:exclusive default:0x0
+ 0x00 MMX->float operations
+ 0x01 float->MMX operations
+name:dc_pend_miss type:exclusive default:0x0
+ 0x00 Weighted cycles
+ 0x01 Duration of cycles
+name:sse_miss type:exclusive default:0x0
+ 0x00 PREFETCHNTA
+ 0x01 PREFETCHT0
+ 0x02 PREFETCHT1/PREFETCHT2
+name:load_block type:bitmask default:0x3e
+ 0x02 STA Loads blocked by a preceding store with unknown address.
+ 0x04 STD Loads blocked by a preceding store with unknown data.
+ 0x08 OVERLAP_STORE Loads that partially overlap an earlier store, or 4K aliased with a previous store.
+ 0x10 UNTIL_RETIRE Loads blocked until retirement.
+ 0x20 L1D Loads blocked by the L1 data cache.
+name:store_block type:bitmask default:0x0b
+ 0x01 SB_DRAIN_CYCLES Cycles while stores are blocked due to store buffer drain.
+ 0x02 ORDER Cycles while store is waiting for a preceding store to be globally observed.
+ 0x08 NOOP A store is blocked due to a conflict with an external or internal snoop.
+name:dtlb_miss type:bitmask default:0x0f
+ 0x01 ANY Memory accesses that missed the DTLB.
+ 0x02 MISS_LD DTLB misses due to load operations.
+ 0x04 L0_MISS_LD L0 DTLB misses due to load operations.
+ 0x08 MISS_ST TLB misses due to store operations.
+name:memory_dis type:exclusive default:0x01
+ 0x01 RESET Memory disambiguation reset cycles.
+ 0x02 SUCCESS Number of loads that were successfully disambiguated.
+name:page_walks type:exclusive default:0x02
+ 0x01 COUNT Number of page-walks executed.
+ 0x02 CYCLES Duration of page-walks in core cycles.
+name:delayed_bypass type:exclusive default:0x00
+ 0x00 FP Delayed bypass to FP operation.
+ 0x01 SIMD Delayed bypass to SIMD operation.
+ 0x02 LOAD Delayed bypass to load operation.
+name:core type:exclusive default:0x40
+ 0xc0 All cores
+ 0x40 This core
+name:core_prefetch type:bitmask default:0xf0
+ 0xc0 core: all cores
+ 0x40 core: this core
+ 0x30 prefetch: all inclusive
+ 0x10 prefetch: Hardware prefetch only
+ 0x00 prefetch: exclude hardware prefetch
+name:core_mesi type:bitmask default:0xcf
+ 0xc0 core: all cores
+ 0x40 core: this core
+ 0x08 (M)ESI: Modified
+ 0x04 M(E)SI: Exclusive
+ 0x02 ME(S)I: Shared
+ 0x01 MES(I): Invalid
+name:core_prefetch_mesi type:bitmask default:0xff
+ 0xc0 core: all cores
+ 0x40 core: this core
+ 0x30 prefetch: all inclusive
+ 0x10 prefetch: Hardware prefetch only
+ 0x00 prefetch: exclude hardware prefetch
+ 0x08 (M)ESI: Modified
+ 0x04 M(E)SI: Exclusive
+ 0x02 ME(S)I: Shared
+ 0x01 MES(I): Invalid
+name:l1d_split type:exclusive default:0x1
+ 0x1 split loads
+ 0x2 split stores
+name:bus_agents type:exclusive default:0x00
+ 0x00 this agent
+ 0x10 include all agents
+name:core_and_bus_agents type:bitmask default:0xc0
+ 0xc0 core: all cores
+ 0x40 core: this core
+ 0x00 bus: this agent
+ 0x10 bus: include all agents
+name:bus_agents_and_snoop type:bitmask default:0x13
+ 0x00 bus: this agent
+ 0x10 bus: include all agents
+ 0x01 snoop: CMP2I snoops
+ 0x02 snoop: CMP2S snoops
+name:core_and_snoop type:bitmask default:0xc0
+ 0xc0 core: all cores
+ 0x40 core: this core
+ 0x01 snoop: CMP2I snoops
+ 0x02 snoop: CMP2S snoops
+name:itlb_miss type:bitmask default:0x12
+ 0x02 ITLB small page misses
+ 0x10 ITLB large page misses
+ 0x40 ITLB flushes
+name:macro_insts type:bitmask default:0x09
+ 0x01 Instructions decoded
+ 0x08 CISC Instructions decoded
+name:esp type:bitmask default:0x01
+ 0x01 ESP register content synchronizations
+ 0x02 ESP register automatic additions
+name:inst_retired type:bitmask default:0x00
+ 0x00 Any
+ 0x01 Loads
+ 0x02 Stores
+ 0x04 Other
+name:x87_ops_retired type:exclusive default:0xfe
+ 0x01 FXCH instructions retired
+ 0xfe Retired floating-point computational operations (precise)
+name:uops_retired type:bitmask default:0x0f
+ 0x01 Fused load+op or load+indirect branch retired
+ 0x02 Fused store address + data retired
+ 0x04 Retired instruction pairs fused into one micro-op
+ 0x07 Fused micro-ops retired
+ 0x08 Non-fused micro-ops retired
+ 0x0f Micro-ops retired
+name:machine_nukes type:bitmask default:0x05
+ 0x01 Self-Modifying Code detected
+ 0x04 Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction
+name:br_inst_retired type:bitmask default:0xa
+ 0x01 predicted not-taken
+ 0x02 mispredicted not-taken
+ 0x04 predicted taken
+ 0x08 mispredicted taken
+name:cycles_int_masked type:exclusive default:0x02
+ 0x01 Interrupts disabled
+ 0x02 Interrupts pending and disabled
+name:simd_inst_retired type:bitmask default:0x1f
+ 0x01 Retired SSE packed-single instructions
+ 0x02 Retired SSE scalar-single instructions
+ 0x04 Retired SSE2 packed-double instructions
+ 0x08 Retired SSE2 scalar-double instructions
+ 0x10 Retired SSE2 vector integer instructions
+ 0x1f Retired Streaming SIMD instructions (precise event)
+name:simd_comp_inst_retired type:bitmask default:0xf
+ 0x01 Retired computational SSE packed-single instructions
+ 0x02 Retired computational SSE scalar-single instructions
+ 0x04 Retired computational SSE2 packed-double instructions
+ 0x08 Retired computational SSE2 scalar-double instructions
+name:mem_load_retired type:exclusive default:0x01
+ 0x01 Retired loads that miss the L1 data cache (precise event)
+ 0x02 L1 data cache line missed by retired loads (precise event)
+ 0x04 Retired loads that miss the L2 cache (precise event)
+ 0x08 L2 cache line missed by retired loads (precise event)
+ 0x10 Retired loads that miss the DTLB (precise event)
+name:rat_stalls type:bitmask default:0xf
+ 0x01 ROB read port
+ 0x02 Partial register
+ 0x04 Flag
+ 0x08 FPU status word
+ 0x0f All RAT
+name:seg_regs type:bitmask default:0x0f
+ 0x01 ES
+ 0x02 DS
+ 0x04 FS
+ 0x08 GS
+name:resource_stalls type:bitmask default:0x0f
+ 0x01 when the ROB is full
+ 0x02 during which the RS is full
+ 0x04 during which the pipeline has exceeded the load or store limit or is waiting to commit all stores
+ 0x08 due to FPU control word write
+ 0x10 due to branch misprediction
Index: oprofile.spec
===================================================================
RCS file: /cvs/dist/rpms/oprofile/FC-5/oprofile.spec,v
retrieving revision 1.39
retrieving revision 1.40
diff -u -r1.39 -r1.40
--- oprofile.spec 11 Feb 2006 04:54:35 -0000 1.39
+++ oprofile.spec 20 Dec 2006 16:38:03 -0000 1.40
@@ -1,10 +1,10 @@
%define DATE 200511111
%define oprofile_version 0.9.1
-%define oprofile_release 8
+%define oprofile_release 9
Summary: System wide profiler
Name: oprofile
Version: 0.9.1
-Release: %{oprofile_release}.1.1
+Release: %{oprofile_release}
License: GPL
Group: Development/System
#
@@ -19,6 +19,8 @@
#Patch80: oprofile-0.8.2-ppc64dot.patch
Patch81: oprofile-0.9.1-anon.patch
Patch82: oprofile_opcontrol.patch
+Patch85: oprofile-core.patch
+Patch86: oprofile-core_2.patch
URL: http://oprofile.sf.net
ExclusiveArch: %{ix86} ia64 x86_64 ppc ppc64 s390 s390x alpha alphaev6 sparc sparc64
@@ -58,6 +60,8 @@
#%patch80 -p1 -b .ppc64dot
%patch81 -p1 -b .anon
%patch82 -p1 -b .opcontrol
+%patch85 -p0 -b .core
+%patch86 -p1 -b .core2
./autogen.sh
@@ -163,6 +167,10 @@
/usr/share/oprofile/arm/xscale2/unit_masks
/usr/share/oprofile/i386/athlon/events
/usr/share/oprofile/i386/athlon/unit_masks
+/usr/share/oprofile/i386/core/events
+/usr/share/oprofile/i386/core/unit_masks
+/usr/share/oprofile/i386/core_2/events
+/usr/share/oprofile/i386/core_2/unit_masks
/usr/share/oprofile/i386/p4-ht/events
/usr/share/oprofile/i386/p4-ht/unit_masks
/usr/share/oprofile/i386/p4/events
@@ -233,6 +241,9 @@
%changelog
+* Wed Dec 20 2006 Will Cohen <wcohen at redhat.com> - 0.9.1-9
+- Add Core and Core2 support. (#215729)
+
* Fri Feb 10 2006 Jesse Keating <jkeating at redhat.com> - 0.9.1-8.1.1
- bump again for double-long bug on ppc(64)
- Previous message (by thread): rpms/evolution/devel evolution-2.8.0-fix-indic-printing.patch, 1.2, 1.3 evolution.spec, 1.219, 1.220
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