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rpms/valgrind/devel valgrind-3.1.0-amd64-highbase.patch, NONE, 1.1 valgrind-3.1.0-amd64-speedup.patch, NONE, 1.1 valgrind-3.1.0-valgrind_h.patch, NONE, 1.1 .cvsignore, 1.7, 1.8 sources, 1.7, 1.8 valgrind.spec, 1.24, 1.25 valgrind-3.0.1-amd64-highbase.patch, 1.1, NONE valgrind-3.0.1-amd64-speedup.patch, 1.1, NONE valgrind-3.0.1-amd64-syscalls.patch, 1.1, NONE valgrind-3.0.1-biarch-hack.patch, 1.1, NONE valgrind-3.0.1-valgrind_h.patch, 1.1, NONE



Author: jakub

Update of /cvs/dist/rpms/valgrind/devel
In directory cvs.devel.redhat.com:/tmp/cvs-serv17209/devel

Modified Files:
	.cvsignore sources valgrind.spec 
Added Files:
	valgrind-3.1.0-amd64-highbase.patch 
	valgrind-3.1.0-amd64-speedup.patch 
	valgrind-3.1.0-valgrind_h.patch 
Removed Files:
	valgrind-3.0.1-amd64-highbase.patch 
	valgrind-3.0.1-amd64-speedup.patch 
	valgrind-3.0.1-amd64-syscalls.patch 
	valgrind-3.0.1-biarch-hack.patch 
	valgrind-3.0.1-valgrind_h.patch 
Log Message:
auto-import valgrind-3.1.0-1 on branch devel from valgrind-3.1.0-1.src.rpm

valgrind-3.1.0-amd64-highbase.patch:
 Makefile.am            |    2 +-
 Makefile.flags.am      |    2 +-
 Makefile.in            |    2 +-
 Makefile.tool.am       |    2 +-
 addrcheck/Makefile.in  |    4 ++--
 auxprogs/Makefile.in   |    2 +-
 cachegrind/Makefile.in |    4 ++--
 configure              |   11 ++++++-----
 configure.in           |   11 ++++++-----
 coregrind/Makefile.am  |    4 ++--
 coregrind/Makefile.in  |    6 +++---
 coregrind/m_main.c     |    2 +-
 helgrind/Makefile.am   |    2 +-
 helgrind/Makefile.in   |    6 +++---
 lackey/Makefile.in     |    4 ++--
 massif/Makefile.am     |    2 +-
 massif/Makefile.in     |    6 +++---
 memcheck/Makefile.am   |    2 +-
 memcheck/Makefile.in   |    6 +++---
 none/Makefile.in       |    4 ++--
 20 files changed, 43 insertions(+), 41 deletions(-)

--- NEW FILE valgrind-3.1.0-amd64-highbase.patch ---
--- valgrind-3.1.0/configure.in.jj	2005-11-26 08:35:39.000000000 -0500
+++ valgrind-3.1.0/configure.in	2006-01-09 11:40:50.000000000 -0500
@@ -124,11 +124,12 @@ case "${host_cpu}" in
      x86_64) 
         AC_MSG_RESULT([ok (${host_cpu})])
         VG_ARCH="amd64"
-        # XXX: relocations under amd64's "small model" are 32-bit signed
-        # quantities; therefore going above 0x7fffffff doesn't work... this is
-        # a problem.
-        valt_load_address_normal="0x70000000"
-        valt_load_address_inner="0x60000000"
+        valt_load_address_normal="0x60b0000000"
+        valt_load_address_inner="0x60a0000000"
+        mkdir -p pie_crtfiles
+        cp -a `$CC -print-file-name=crtbeginS.o` pie_crtfiles/crtbegin.o
+        cp -a `$CC -print-file-name=crtendS.o` pie_crtfiles/crtend.o
+        cp -a `$CC -print-file-name=Scrt1.o` pie_crtfiles/crt1.o
         ;;
 
      powerpc*)
--- valgrind-3.1.0/coregrind/m_main.c.jj	2005-11-25 07:36:21.000000000 -0500
+++ valgrind-3.1.0/coregrind/m_main.c	2006-01-09 11:50:24.000000000 -0500
@@ -2810,7 +2810,7 @@ asm("\n"
     "\t.type _start,@function\n"
     "_start:\n"
     /* set up the new stack in %rdi */
-    "\tmovq  $vgPlain_interim_stack, %rdi\n"
+    "\tleaq  vgPlain_interim_stack(%rip), %rdi\n"
     "\taddq  $"VG_STRINGIFY(VG_STACK_GUARD_SZB)", %rdi\n"
     "\taddq  $"VG_STRINGIFY(VG_STACK_ACTIVE_SZB)", %rdi\n"
     "\tandq  $~15, %rdi\n"
--- valgrind-3.1.0/Makefile.tool.am.jj	2005-11-25 07:36:22.000000000 -0500
+++ valgrind-3.1.0/Makefile.tool.am	2006-01-09 11:40:50.000000000 -0500
@@ -53,7 +53,7 @@ TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDADD_AMD64_LINUX = $(COREGRIND_LIBS_AMD64_LINUX) $(TOOL_LDADD_COMMON)
 TOOL_LDFLAGS_AMD64_LINUX = \
-	$(TOOL_LDFLAGS_COMMON) -m64 \
+	$(TOOL_LDFLAGS_COMMON) -m64 -B$(top_builddir)/pie_crtfiles/ \
 	-Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
 
 TOOL_LDADD_PPC32_LINUX = $(COREGRIND_LIBS_PPC32_LINUX) $(TOOL_LDADD_COMMON)
--- valgrind-3.1.0/Makefile.flags.am.jj	2005-11-25 07:36:22.000000000 -0500
+++ valgrind-3.1.0/Makefile.flags.am	2006-01-09 11:40:50.000000000 -0500
@@ -8,7 +8,7 @@ AM_CFLAGS_X86_LINUX = $(WERROR) @FLAG_M3
 AM_CCASFLAGS_X86_LINUX = $(add_includes_x86_linux) @FLAG_M32@ -g
 
 AM_CPPFLAGS_AMD64_LINUX = $(add_includes_amd64_linux)
-AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer -fpie @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) -m64 -g
 
 AM_CPPFLAGS_PPC32_LINUX = $(add_includes_ppc32_linux)
--- valgrind-3.1.0/Makefile.am.jj	2005-11-25 07:36:22.000000000 -0500
+++ valgrind-3.1.0/Makefile.am	2006-01-09 12:04:55.000000000 -0500
@@ -178,7 +178,7 @@ valt_load_address_x86_linux.lds: Makefil
 	$(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
 		-e '1,/^=====\+$$/d' \
 		-e '/^=====\+$$/d' \
-		-e '/\. = 0x[0-9A-Fa-f]\+ + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
+		-e '/\. = 0x[0-9A-Fa-f]\+ + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/(valt_load_address \& 0xffffffff)/g' > $@ \
 	|| rm -f $@
 
 valt_load_address_amd64_linux.lds: Makefile
--- valgrind-3.1.0/coregrind/Makefile.am.jj	2006-01-09 12:03:01.000000000 -0500
+++ valgrind-3.1.0/coregrind/Makefile.am	2006-01-09 12:04:55.000000000 -0500
@@ -213,7 +213,7 @@ libreplacemalloc_toolpreload_x86_linux_a
 
 libreplacemalloc_toolpreload_amd64_linux_a_SOURCES = m_replacemalloc/vg_replace_malloc.c
 libreplacemalloc_toolpreload_amd64_linux_a_CPPFLAGS = $(AM_CPPFLAGS_AMD64_LINUX)
-libreplacemalloc_toolpreload_amd64_linux_a_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) -fpic -fno-omit-frame-pointer
+libreplacemalloc_toolpreload_amd64_linux_a_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) -fno-pie -fpic -fno-omit-frame-pointer
 
 libreplacemalloc_toolpreload_ppc32_linux_a_SOURCES = m_replacemalloc/vg_replace_malloc.c
 libreplacemalloc_toolpreload_ppc32_linux_a_CPPFLAGS = $(AM_CPPFLAGS_PPC32_LINUX)
@@ -239,7 +239,7 @@ vgpreload_core_x86_linux_so_LDFLAGS = $(
 
 vgpreload_core_amd64_linux_so_SOURCES = $(VGPRELOAD_CORE_SOURCES_COMMON)
 vgpreload_core_amd64_linux_so_CPPFLAGS = $(AM_CPPFLAGS_AMD64_LINUX)
-vgpreload_core_amd64_linux_so_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) $(AM_CFLAGS_PIC)
+vgpreload_core_amd64_linux_so_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) -fno-pie $(AM_CFLAGS_PIC)
 vgpreload_core_amd64_linux_so_LDFLAGS = $(PRELOAD_LDFLAGS_AMD64_LINUX)
 
 vgpreload_core_ppc32_linux_so_SOURCES = $(VGPRELOAD_CORE_SOURCES_COMMON)
--- valgrind-3.1.0/massif/Makefile.am.jj	2006-01-09 12:03:01.000000000 -0500
+++ valgrind-3.1.0/massif/Makefile.am	2006-01-09 12:04:55.000000000 -0500
@@ -23,7 +23,7 @@ vgpreload_massif_x86_linux_so_LDFLAGS   
 
 vgpreload_massif_amd64_linux_so_SOURCES      = 
 vgpreload_massif_amd64_linux_so_CPPFLAGS     = $(AM_CPPFLAGS_AMD64_LINUX)
-vgpreload_massif_amd64_linux_so_CFLAGS       = $(AM_CFLAGS_AMD64_LINUX) $(AM_CFLAGS_PIC)
+vgpreload_massif_amd64_linux_so_CFLAGS       = $(AM_CFLAGS_AMD64_LINUX) -fno-pie $(AM_CFLAGS_PIC)
 vgpreload_massif_amd64_linux_so_DEPENDENCIES = $(LIBREPLACEMALLOC_AMD64_LINUX)
 vgpreload_massif_amd64_linux_so_LDFLAGS      = \
 	$(PRELOAD_LDFLAGS_AMD64_LINUX) \
--- valgrind-3.1.0/memcheck/Makefile.am.jj	2006-01-09 12:03:01.000000000 -0500
+++ valgrind-3.1.0/memcheck/Makefile.am	2006-01-09 12:04:55.000000000 -0500
@@ -24,7 +24,7 @@ vgpreload_memcheck_x86_linux_so_LDFLAGS 
 
 vgpreload_memcheck_amd64_linux_so_SOURCES      = $(VGPRELOAD_MEMCHECK_SOURCES_COMMON)
 vgpreload_memcheck_amd64_linux_so_CPPFLAGS     = $(AM_CPPFLAGS_AMD64_LINUX)
-vgpreload_memcheck_amd64_linux_so_CFLAGS       = $(AM_CFLAGS_AMD64_LINUX) $(AM_CFLAGS_PIC) -O2
+vgpreload_memcheck_amd64_linux_so_CFLAGS       = $(AM_CFLAGS_AMD64_LINUX) -fno-pie $(AM_CFLAGS_PIC) -O2
 vgpreload_memcheck_amd64_linux_so_CCASFLAGS    = $(AM_CCASFLAGS_AMD64_LINUX)
 vgpreload_memcheck_amd64_linux_so_DEPENDENCIES = $(LIBREPLACEMALLOC_AMD64_LINUX)
 vgpreload_memcheck_amd64_linux_so_LDFLAGS      = \
--- valgrind-3.1.0/helgrind/Makefile.am.jj	2006-01-09 12:03:01.000000000 -0500
+++ valgrind-3.1.0/helgrind/Makefile.am	2006-01-09 12:04:55.000000000 -0500
@@ -21,7 +21,7 @@ vgpreload_helgrind_x86_linux_so_LDFLAGS 
 
 vgpreload_helgrind_amd64_linux_so_SOURCES      = 
 vgpreload_helgrind_amd64_linux_so_CPPFLAGS     = $(AM_CPPFLAGS_AMD64_LINUX)
-vgpreload_helgrind_amd64_linux_so_CFLAGS       = $(AM_CFLAGS_AMD64_LINUX) $(AM_CFLAGS_PIC)
+vgpreload_helgrind_amd64_linux_so_CFLAGS       = $(AM_CFLAGS_AMD64_LINUX) -fno-pie $(AM_CFLAGS_PIC)
 vgpreload_helgrind_amd64_linux_so_DEPENDENCIES = $(LIBREPLACEMALLOC_AMD64_LINUX)
 vgpreload_helgrind_amd64_linux_so_LDFLAGS      = \
 	$(PRELOAD_LDFLAGS_AMD64_LINUX) \
--- valgrind-3.1.0/addrcheck/Makefile.in.jj	2005-11-26 08:39:53.000000000 -0500
+++ valgrind-3.1.0/addrcheck/Makefile.in	2006-01-09 12:05:12.000000000 -0500
@@ -235,7 +235,7 @@ AM_CPPFLAGS_X86_LINUX = $(add_includes_x
 AM_CFLAGS_X86_LINUX = $(WERROR) @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_X86_LINUX = $(add_includes_x86_linux) @FLAG_M32@ -g
 AM_CPPFLAGS_AMD64_LINUX = $(add_includes_amd64_linux)
-AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer -fpie @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) -m64 -g
 AM_CPPFLAGS_PPC32_LINUX = $(add_includes_ppc32_linux)
 AM_CFLAGS_PPC32_LINUX = $(WERROR) $(AM_CFLAGS_BASE)
@@ -276,7 +276,7 @@ TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDADD_AMD64_LINUX = $(COREGRIND_LIBS_AMD64_LINUX) $(TOOL_LDADD_COMMON)
 TOOL_LDFLAGS_AMD64_LINUX = \
-	$(TOOL_LDFLAGS_COMMON) -m64 \
+	$(TOOL_LDFLAGS_COMMON) -m64 -B$(top_builddir)/pie_crtfiles/ \
 	-Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
 
 TOOL_LDADD_PPC32_LINUX = $(COREGRIND_LIBS_PPC32_LINUX) $(TOOL_LDADD_COMMON)
--- valgrind-3.1.0/lackey/Makefile.in.jj	2005-11-26 08:40:05.000000000 -0500
+++ valgrind-3.1.0/lackey/Makefile.in	2006-01-09 12:05:12.000000000 -0500
@@ -256,7 +256,7 @@ AM_CPPFLAGS_X86_LINUX = $(add_includes_x
 AM_CFLAGS_X86_LINUX = $(WERROR) @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_X86_LINUX = $(add_includes_x86_linux) @FLAG_M32@ -g
 AM_CPPFLAGS_AMD64_LINUX = $(add_includes_amd64_linux)
-AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer -fpie @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) -m64 -g
 AM_CPPFLAGS_PPC32_LINUX = $(add_includes_ppc32_linux)
 AM_CFLAGS_PPC32_LINUX = $(WERROR) $(AM_CFLAGS_BASE)
@@ -297,7 +297,7 @@ TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDADD_AMD64_LINUX = $(COREGRIND_LIBS_AMD64_LINUX) $(TOOL_LDADD_COMMON)
 TOOL_LDFLAGS_AMD64_LINUX = \
-	$(TOOL_LDFLAGS_COMMON) -m64 \
+	$(TOOL_LDFLAGS_COMMON) -m64 -B$(top_builddir)/pie_crtfiles/ \
 	-Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
 
 TOOL_LDADD_PPC32_LINUX = $(COREGRIND_LIBS_PPC32_LINUX) $(TOOL_LDADD_COMMON)
--- valgrind-3.1.0/coregrind/Makefile.in.jj	2005-11-26 08:40:02.000000000 -0500
+++ valgrind-3.1.0/coregrind/Makefile.in	2006-01-09 12:05:12.000000000 -0500
@@ -501,7 +501,7 @@ AM_CFLAGS_X86_LINUX = $(WERROR) @FLAG_M3
 AM_CCASFLAGS_X86_LINUX = $(add_includes_x86_linux) @FLAG_M32@ -g
 AM_CPPFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) \
 	-DVG_LIBDIR="\"$(valdir)"\"
-AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer -fpie @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) -m64 -g
 AM_CPPFLAGS_PPC32_LINUX = $(add_includes_ppc32_linux) \
 	-DVG_LIBDIR="\"$(valdir)"\"
@@ -683,7 +683,7 @@ libreplacemalloc_toolpreload_x86_linux_a
 libreplacemalloc_toolpreload_x86_linux_a_CFLAGS = $(AM_CFLAGS_X86_LINUX) -fpic -fno-omit-frame-pointer
 libreplacemalloc_toolpreload_amd64_linux_a_SOURCES = m_replacemalloc/vg_replace_malloc.c
 libreplacemalloc_toolpreload_amd64_linux_a_CPPFLAGS = $(AM_CPPFLAGS_AMD64_LINUX)
-libreplacemalloc_toolpreload_amd64_linux_a_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) -fpic -fno-omit-frame-pointer
+libreplacemalloc_toolpreload_amd64_linux_a_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) -fno-pie -fpic -fno-omit-frame-pointer
 libreplacemalloc_toolpreload_ppc32_linux_a_SOURCES = m_replacemalloc/vg_replace_malloc.c
 libreplacemalloc_toolpreload_ppc32_linux_a_CPPFLAGS = $(AM_CPPFLAGS_PPC32_LINUX)
 libreplacemalloc_toolpreload_ppc32_linux_a_CFLAGS = $(AM_CFLAGS_PPC32_LINUX) -fpic -fno-omit-frame-pointer
@@ -694,7 +694,7 @@ vgpreload_core_x86_linux_so_CFLAGS = $(A
 vgpreload_core_x86_linux_so_LDFLAGS = $(PRELOAD_LDFLAGS_X86_LINUX)
 vgpreload_core_amd64_linux_so_SOURCES = $(VGPRELOAD_CORE_SOURCES_COMMON)
 vgpreload_core_amd64_linux_so_CPPFLAGS = $(AM_CPPFLAGS_AMD64_LINUX)
-vgpreload_core_amd64_linux_so_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) $(AM_CFLAGS_PIC)
+vgpreload_core_amd64_linux_so_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) -fno-pie $(AM_CFLAGS_PIC)
 vgpreload_core_amd64_linux_so_LDFLAGS = $(PRELOAD_LDFLAGS_AMD64_LINUX)
 vgpreload_core_ppc32_linux_so_SOURCES = $(VGPRELOAD_CORE_SOURCES_COMMON)
 vgpreload_core_ppc32_linux_so_CPPFLAGS = $(AM_CPPFLAGS_PPC32_LINUX)
--- valgrind-3.1.0/none/Makefile.in.jj	2005-11-26 08:40:12.000000000 -0500
+++ valgrind-3.1.0/none/Makefile.in	2006-01-09 12:05:12.000000000 -0500
@@ -256,7 +256,7 @@ AM_CPPFLAGS_X86_LINUX = $(add_includes_x
 AM_CFLAGS_X86_LINUX = $(WERROR) @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_X86_LINUX = $(add_includes_x86_linux) @FLAG_M32@ -g
 AM_CPPFLAGS_AMD64_LINUX = $(add_includes_amd64_linux)
-AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer -fpie @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) -m64 -g
 AM_CPPFLAGS_PPC32_LINUX = $(add_includes_ppc32_linux)
 AM_CFLAGS_PPC32_LINUX = $(WERROR) $(AM_CFLAGS_BASE)
@@ -297,7 +297,7 @@ TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDADD_AMD64_LINUX = $(COREGRIND_LIBS_AMD64_LINUX) $(TOOL_LDADD_COMMON)
 TOOL_LDFLAGS_AMD64_LINUX = \
-	$(TOOL_LDFLAGS_COMMON) -m64 \
+	$(TOOL_LDFLAGS_COMMON) -m64 -B$(top_builddir)/pie_crtfiles/ \
 	-Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
 
 TOOL_LDADD_PPC32_LINUX = $(COREGRIND_LIBS_PPC32_LINUX) $(TOOL_LDADD_COMMON)
--- valgrind-3.1.0/configure.jj	2005-11-26 08:40:17.000000000 -0500
+++ valgrind-3.1.0/configure	2006-01-09 11:40:50.000000000 -0500
@@ -3996,11 +3996,12 @@ echo "${ECHO_T}ok (${host_cpu})" >&6
         echo "$as_me:$LINENO: result: ok (${host_cpu})" >&5
 echo "${ECHO_T}ok (${host_cpu})" >&6
         VG_ARCH="amd64"
-        # XXX: relocations under amd64's "small model" are 32-bit signed
-        # quantities; therefore going above 0x7fffffff doesn't work... this is
-        # a problem.
-        valt_load_address_normal="0x70000000"
-        valt_load_address_inner="0x60000000"
+        valt_load_address_normal="0x60b0000000"
+        valt_load_address_inner="0x60a0000000"
+        mkdir -p pie_crtfiles
+        cp -a `$CC -print-file-name=crtbeginS.o` pie_crtfiles/crtbegin.o
+        cp -a `$CC -print-file-name=crtendS.o` pie_crtfiles/crtend.o
+        cp -a `$CC -print-file-name=Scrt1.o` pie_crtfiles/crt1.o
         ;;
 
      powerpc*)
--- valgrind-3.1.0/massif/Makefile.in.jj	2005-11-26 08:40:07.000000000 -0500
+++ valgrind-3.1.0/massif/Makefile.in	2006-01-09 12:05:12.000000000 -0500
@@ -277,7 +277,7 @@ AM_CPPFLAGS_X86_LINUX = $(add_includes_x
 AM_CFLAGS_X86_LINUX = $(WERROR) @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_X86_LINUX = $(add_includes_x86_linux) @FLAG_M32@ -g
 AM_CPPFLAGS_AMD64_LINUX = $(add_includes_amd64_linux)
-AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer -fpie @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) -m64 -g
 AM_CPPFLAGS_PPC32_LINUX = $(add_includes_ppc32_linux)
 AM_CFLAGS_PPC32_LINUX = $(WERROR) $(AM_CFLAGS_BASE)
@@ -318,7 +318,7 @@ TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDADD_AMD64_LINUX = $(COREGRIND_LIBS_AMD64_LINUX) $(TOOL_LDADD_COMMON)
 TOOL_LDFLAGS_AMD64_LINUX = \
-	$(TOOL_LDFLAGS_COMMON) -m64 \
+	$(TOOL_LDFLAGS_COMMON) -m64 -B$(top_builddir)/pie_crtfiles/ \
 	-Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
 
 TOOL_LDADD_PPC32_LINUX = $(COREGRIND_LIBS_PPC32_LINUX) $(TOOL_LDADD_COMMON)
@@ -355,7 +355,7 @@ vgpreload_massif_x86_linux_so_LDFLAGS = 
 
 vgpreload_massif_amd64_linux_so_SOURCES = 
 vgpreload_massif_amd64_linux_so_CPPFLAGS = $(AM_CPPFLAGS_AMD64_LINUX)
-vgpreload_massif_amd64_linux_so_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) $(AM_CFLAGS_PIC)
+vgpreload_massif_amd64_linux_so_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) -fno-pie $(AM_CFLAGS_PIC)
 vgpreload_massif_amd64_linux_so_DEPENDENCIES = $(LIBREPLACEMALLOC_AMD64_LINUX)
 vgpreload_massif_amd64_linux_so_LDFLAGS = \
 	$(PRELOAD_LDFLAGS_AMD64_LINUX) \
--- valgrind-3.1.0/memcheck/Makefile.in.jj	2005-11-26 08:40:08.000000000 -0500
+++ valgrind-3.1.0/memcheck/Makefile.in	2006-01-09 12:05:12.000000000 -0500
@@ -304,7 +304,7 @@ AM_CPPFLAGS_X86_LINUX = $(add_includes_x
 AM_CFLAGS_X86_LINUX = $(WERROR) @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_X86_LINUX = $(add_includes_x86_linux) @FLAG_M32@ -g
 AM_CPPFLAGS_AMD64_LINUX = $(add_includes_amd64_linux)
-AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer -fpie @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) -m64 -g
 AM_CPPFLAGS_PPC32_LINUX = $(add_includes_ppc32_linux)
 AM_CFLAGS_PPC32_LINUX = $(WERROR) $(AM_CFLAGS_BASE)
@@ -345,7 +345,7 @@ TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDADD_AMD64_LINUX = $(COREGRIND_LIBS_AMD64_LINUX) $(TOOL_LDADD_COMMON)
 TOOL_LDFLAGS_AMD64_LINUX = \
-	$(TOOL_LDFLAGS_COMMON) -m64 \
+	$(TOOL_LDFLAGS_COMMON) -m64 -B$(top_builddir)/pie_crtfiles/ \
 	-Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
 
 TOOL_LDADD_PPC32_LINUX = $(COREGRIND_LIBS_PPC32_LINUX) $(TOOL_LDADD_COMMON)
@@ -384,7 +384,7 @@ vgpreload_memcheck_x86_linux_so_LDFLAGS 
 
 vgpreload_memcheck_amd64_linux_so_SOURCES = $(VGPRELOAD_MEMCHECK_SOURCES_COMMON)
 vgpreload_memcheck_amd64_linux_so_CPPFLAGS = $(AM_CPPFLAGS_AMD64_LINUX)
-vgpreload_memcheck_amd64_linux_so_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) $(AM_CFLAGS_PIC) -O2
+vgpreload_memcheck_amd64_linux_so_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) -fno-pie $(AM_CFLAGS_PIC) -O2
 vgpreload_memcheck_amd64_linux_so_CCASFLAGS = $(AM_CCASFLAGS_AMD64_LINUX)
 vgpreload_memcheck_amd64_linux_so_DEPENDENCIES = $(LIBREPLACEMALLOC_AMD64_LINUX)
 vgpreload_memcheck_amd64_linux_so_LDFLAGS = \
--- valgrind-3.1.0/cachegrind/Makefile.in.jj	2005-11-26 08:39:56.000000000 -0500
+++ valgrind-3.1.0/cachegrind/Makefile.in	2006-01-09 12:05:12.000000000 -0500
@@ -268,7 +268,7 @@ AM_CPPFLAGS_X86_LINUX = $(add_includes_x
 AM_CFLAGS_X86_LINUX = $(WERROR) @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_X86_LINUX = $(add_includes_x86_linux) @FLAG_M32@ -g
 AM_CPPFLAGS_AMD64_LINUX = $(add_includes_amd64_linux)
-AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer -fpie @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) -m64 -g
 AM_CPPFLAGS_PPC32_LINUX = $(add_includes_ppc32_linux)
 AM_CFLAGS_PPC32_LINUX = $(WERROR) $(AM_CFLAGS_BASE)
@@ -309,7 +309,7 @@ TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDADD_AMD64_LINUX = $(COREGRIND_LIBS_AMD64_LINUX) $(TOOL_LDADD_COMMON)
 TOOL_LDFLAGS_AMD64_LINUX = \
-	$(TOOL_LDFLAGS_COMMON) -m64 \
+	$(TOOL_LDFLAGS_COMMON) -m64 -B$(top_builddir)/pie_crtfiles/ \
 	-Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
 
 TOOL_LDADD_PPC32_LINUX = $(COREGRIND_LIBS_PPC32_LINUX) $(TOOL_LDADD_COMMON)
--- valgrind-3.1.0/helgrind/Makefile.in.jj	2005-11-26 08:40:04.000000000 -0500
+++ valgrind-3.1.0/helgrind/Makefile.in	2006-01-09 12:05:12.000000000 -0500
@@ -288,7 +288,7 @@ AM_CPPFLAGS_X86_LINUX = $(add_includes_x
 AM_CFLAGS_X86_LINUX = $(WERROR) @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_X86_LINUX = $(add_includes_x86_linux) @FLAG_M32@ -g
 AM_CPPFLAGS_AMD64_LINUX = $(add_includes_amd64_linux)
-AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer -fpie @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) -m64 -g
 AM_CPPFLAGS_PPC32_LINUX = $(add_includes_ppc32_linux)
 AM_CFLAGS_PPC32_LINUX = $(WERROR) $(AM_CFLAGS_BASE)
@@ -329,7 +329,7 @@ TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDADD_AMD64_LINUX = $(COREGRIND_LIBS_AMD64_LINUX) $(TOOL_LDADD_COMMON)
 TOOL_LDFLAGS_AMD64_LINUX = \
-	$(TOOL_LDFLAGS_COMMON) -m64 \
+	$(TOOL_LDFLAGS_COMMON) -m64 -B$(top_builddir)/pie_crtfiles/ \
 	-Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
 
 TOOL_LDADD_PPC32_LINUX = $(COREGRIND_LIBS_PPC32_LINUX) $(TOOL_LDADD_COMMON)
@@ -366,7 +366,7 @@ vgpreload_helgrind_x86_linux_so_LDFLAGS 
 
 vgpreload_helgrind_amd64_linux_so_SOURCES = 
 vgpreload_helgrind_amd64_linux_so_CPPFLAGS = $(AM_CPPFLAGS_AMD64_LINUX)
-vgpreload_helgrind_amd64_linux_so_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) $(AM_CFLAGS_PIC)
+vgpreload_helgrind_amd64_linux_so_CFLAGS = $(AM_CFLAGS_AMD64_LINUX) -fno-pie $(AM_CFLAGS_PIC)
 vgpreload_helgrind_amd64_linux_so_DEPENDENCIES = $(LIBREPLACEMALLOC_AMD64_LINUX)
 vgpreload_helgrind_amd64_linux_so_LDFLAGS = \
 	$(PRELOAD_LDFLAGS_AMD64_LINUX) \
--- valgrind-3.1.0/Makefile.in.jj	2005-11-26 08:40:16.000000000 -0500
+++ valgrind-3.1.0/Makefile.in	2006-01-09 12:05:12.000000000 -0500
@@ -869,7 +869,7 @@ valt_load_address_x86_linux.lds: Makefil
 	$(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
 		-e '1,/^=====\+$$/d' \
 		-e '/^=====\+$$/d' \
-		-e '/\. = 0x[0-9A-Fa-f]\+ + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
+		-e '/\. = 0x[0-9A-Fa-f]\+ + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/(valt_load_address \& 0xffffffff)/g' > $@ \
 	|| rm -f $@
 
 valt_load_address_amd64_linux.lds: Makefile
--- valgrind-3.1.0/auxprogs/Makefile.in.jj	2005-11-26 08:39:55.000000000 -0500
+++ valgrind-3.1.0/auxprogs/Makefile.in	2006-01-09 12:05:12.000000000 -0500
@@ -230,7 +230,7 @@ AM_CPPFLAGS_X86_LINUX = $(add_includes_x
 AM_CFLAGS_X86_LINUX = $(WERROR) @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_X86_LINUX = $(add_includes_x86_linux) @FLAG_M32@ -g
 AM_CPPFLAGS_AMD64_LINUX = $(add_includes_amd64_linux)
-AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_AMD64_LINUX = $(WERROR) -m64 -fomit-frame-pointer -fpie @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_AMD64_LINUX = $(add_includes_amd64_linux) -m64 -g
 AM_CPPFLAGS_PPC32_LINUX = $(add_includes_ppc32_linux)
 AM_CFLAGS_PPC32_LINUX = $(WERROR) $(AM_CFLAGS_BASE)

valgrind-3.1.0-amd64-speedup.patch:
 toIR.c |  385 ++++++++++++++++++++++++++++++++---------------------------------
 1 files changed, 193 insertions(+), 192 deletions(-)

--- NEW FILE valgrind-3.1.0-amd64-speedup.patch ---
Replaces 188 insn[0] == 0x0F tests with just one, allows for insn[0] != 0x0F
to quickly skip all the 188 if clauses.  I haven't analyzed if the compiler could
possibly figure this out itself, certainly it would be hard.
--- valgrind-3.1.0/VEX/priv/guest-amd64/toIR.c.jj	2005-08-12 20:08:15.000000000 +0200
+++ valgrind-3.1.0/VEX/priv/guest-amd64/toIR.c	2005-08-12 20:26:31.000000000 +0200
@@ -8055,13 +8055,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    insn = (UChar*)&guest_code[delta];
 
+   if (insn[0] == 0x0F) {
 //..    /* Treat fxsave specially.  It should be doable even on an SSE0
 //..       (Pentium-II class) CPU.  Hence be prepared to handle it on
 //..       any subarchitecture variant.
 //..    */
 //.. 
 //..    /* 0F AE /0 = FXSAVE m512 -- write x87 and SSE state to memory */
-//..    if (sz == 4 && insn[0] == 0x0F && insn[1] == 0xAE
+//..    if (sz == 4 /* && insn[0] == 0x0F */ && insn[1] == 0xAE
 //..        && !epartIsReg(insn[2]) && gregOfRM(insn[2]) == 0) {
 //..       modrm = getUChar(delta+2);
 //..       vassert(sz == 4);
@@ -8141,42 +8142,42 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 58 = ADDPS -- add 32Fx4 from R/M to R */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x58) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x58) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "addps", Iop_Add32Fx4 );
       goto decode_success;
    }
 
    /* F3 0F 58 = ADDSS -- add 32F0x4 from R/M to R */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x58) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x58) {
       delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "addss", Iop_Add32F0x4 );
       goto decode_success;
    }
 
    /* 0F 55 = ANDNPS -- G = (not G) and E */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x55) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x55) {
       delta = dis_SSE_E_to_G_all_invG( pfx, delta+2, "andnps", Iop_AndV128 );
       goto decode_success;
    }
 
    /* 0F 54 = ANDPS -- G = G and E */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x54) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x54) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "andps", Iop_AndV128 );
       goto decode_success;
    }
 
    /* 0F C2 = CMPPS -- 32Fx4 comparison from R/M to R */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xC2) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xC2) {
       delta = dis_SSEcmp_E_to_G( pfx, delta+2, "cmpps", True, 4 );
       goto decode_success;
    }
 
    /* F3 0F C2 = CMPSS -- 32F0x4 comparison from R/M to R */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0xC2) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xC2) {
       delta = dis_SSEcmp_E_to_G( pfx, delta+2, "cmpss", False, 4 );
       goto decode_success;
    }
@@ -8184,7 +8185,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 2F = COMISS  -- 32F0x4 comparison G,E, and set ZCP */
    /* 0F 2E = UCOMISS -- 32F0x4 comparison G,E, and set ZCP */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && (insn[1] == 0x2F || insn[1] == 0x2E)) {
+       /* && insn[0] == 0x0F */ && (insn[1] == 0x2F || insn[1] == 0x2E)) {
       IRTemp argL = newTemp(Ity_F32);
       IRTemp argR = newTemp(Ity_F32);
       modrm = getUChar(delta+2);
@@ -8224,7 +8225,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 2A = CVTPI2PS -- convert 2 x I32 in mem/mmx to 2 x F32 in low
       half xmm */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x2A) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x2A) {
       IRTemp arg64 = newTemp(Ity_I64);
       IRTemp rmode = newTemp(Ity_I32);
 
@@ -8266,7 +8267,7 @@ DisResult disInstr_AMD64_WRK ( 
       -- sz==4: convert I32 in mem/ireg to F32 in low quarter xmm
       -- sz==8: convert I64 in mem/ireg to F32 in low quarter xmm */
    if (haveF3no66noF2(pfx) && (sz == 4 || sz == 8)
-       && insn[0] == 0x0F && insn[1] == 0x2A) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x2A) {
 
       IRTemp rmode = newTemp(Ity_I32);
       assign( rmode, get_sse_roundingmode() );
@@ -8321,7 +8322,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 2C = CVTTPS2PI -- convert 2 x F32 in mem/low half xmm to 2 x
       I32 in mmx, rounding towards zero */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && (insn[1] == 0x2D || insn[1] == 0x2C)) {
+       /* && insn[0] == 0x0F */ && (insn[1] == 0x2D || insn[1] == 0x2C)) {
       IRTemp dst64  = newTemp(Ity_I64);
       IRTemp rmode  = newTemp(Ity_I32);
       IRTemp f32lo  = newTemp(Ity_F32);
@@ -8385,7 +8386,7 @@ DisResult disInstr_AMD64_WRK ( 
                     truncating towards zero 
    */
    if (haveF3no66noF2(pfx) 
-       && insn[0] == 0x0F 
+       /* && insn[0] == 0x0F */ 
        && (insn[1] == 0x2D || insn[1] == 0x2C)) {
       IRTemp rmode  = newTemp(Ity_I32);
       IRTemp f32lo  = newTemp(Ity_F32);
@@ -8431,20 +8432,20 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 5E = DIVPS -- div 32Fx4 from R/M to R */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x5E) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5E) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "divps", Iop_Div32Fx4 );
       goto decode_success;
    }
 
    /* F3 0F 5E = DIVSS -- div 32F0x4 from R/M to R */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x5E) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5E) {
       delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "divss", Iop_Div32F0x4 );
       goto decode_success;
    }
 
    /* 0F AE /2 = LDMXCSR m32 -- load %mxcsr */
-   if (insn[0] == 0x0F && insn[1] == 0xAE
+   if (/* insn[0] == 0x0F && */ insn[1] == 0xAE
        && haveNo66noF2noF3(pfx)
        && !epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 2) {
 
@@ -8494,28 +8495,28 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 5F = MAXPS -- max 32Fx4 from R/M to R */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x5F) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5F) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "maxps", Iop_Max32Fx4 );
       goto decode_success;
    }
 
    /* F3 0F 5F = MAXSS -- max 32F0x4 from R/M to R */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x5F) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5F) {
       delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "maxss", Iop_Max32F0x4 );
       goto decode_success;
    }
 
    /* 0F 5D = MINPS -- min 32Fx4 from R/M to R */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x5D) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5D) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "minps", Iop_Min32Fx4 );
       goto decode_success;
    }
 
    /* F3 0F 5D = MINSS -- min 32F0x4 from R/M to R */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x5D) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5D) {
       delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "minss", Iop_Min32F0x4 );
       goto decode_success;
    }
@@ -8523,7 +8524,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 28 = MOVAPS -- move from E (mem or xmm) to G (xmm). */
    /* 0F 10 = MOVUPS -- move from E (mem or xmm) to G (xmm). */
    if (haveNo66noF2noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && (insn[1] == 0x28 || insn[1] == 0x10)) {
+       /* && insn[0] == 0x0F */ && (insn[1] == 0x28 || insn[1] == 0x10)) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          putXMMReg( gregOfRexRM(pfx,modrm), 
@@ -8545,7 +8546,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 29 = MOVAPS -- move from G (xmm) to E (mem or xmm). */
    /* 0F 11 = MOVUPS -- move from G (xmm) to E (mem or xmm). */
    if (haveNo66noF2noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && (insn[1] == 0x29 || insn[1] == 0x11)) {
+       /* && insn[0] == 0x0F */ && (insn[1] == 0x29 || insn[1] == 0x11)) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          /* fall through; awaiting test case */
@@ -8562,7 +8563,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 16 = MOVHPS -- move from mem to high half of XMM. */
    /* 0F 16 = MOVLHPS -- move from lo half to hi half of XMM. */
    if (haveNo66noF2noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x16) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x16) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          delta += 2+1;
@@ -8583,7 +8584,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 17 = MOVHPS -- move from high half of XMM to mem. */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x17) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x17) {
       if (!epartIsReg(insn[2])) {
          delta += 2;
          addr = disAMode ( &alen, pfx, delta, dis_buf, 0 );
@@ -8601,7 +8602,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 12 = MOVLPS -- move from mem to low half of XMM. */
    /* OF 12 = MOVHLPS -- from from hi half to lo half of XMM. */
    if (haveNo66noF2noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x12) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x12) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          delta += 2+1;
@@ -8623,7 +8624,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 13 = MOVLPS -- move from low half of XMM to mem. */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x13) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x13) {
       if (!epartIsReg(insn[2])) {
          delta += 2;
          addr = disAMode ( &alen, pfx, delta, dis_buf, 0 );
@@ -8641,7 +8642,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 50 = MOVMSKPS - move 4 sign bits from 4 x F32 in xmm(E)
       to 4 lowest bits of ireg(G) */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x50) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x50) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          Int src;
@@ -8681,7 +8682,7 @@ DisResult disInstr_AMD64_WRK ( 
    if ( ( (haveNo66noF2noF3(pfx) && sz == 4)
           || (have66noF2noF3(pfx) && sz == 2) 
         )
-        && insn[0] == 0x0F && insn[1] == 0x2B) {
+        /* && insn[0] == 0x0F */ && insn[1] == 0x2B) {
       modrm = getUChar(delta+2);
       if (!epartIsReg(modrm)) {
          addr = disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
@@ -8702,7 +8703,7 @@ DisResult disInstr_AMD64_WRK ( 
       So we just leave them alone. 
    */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xE7) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE7) {
       modrm = getUChar(delta+2);
       if (!epartIsReg(modrm)) {
          /* do_MMX_preamble(); Intel docs don't specify this */
@@ -8719,7 +8720,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* F3 0F 10 = MOVSS -- move 32 bits from E (mem or lo 1/4 xmm) to G
       (lo 1/4 xmm).  If E is mem, upper 3/4 of G is zeroed out. */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x10) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x10) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          putXMMRegLane32( gregOfRexRM(pfx,modrm), 0,
@@ -8742,7 +8743,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* F3 0F 11 = MOVSS -- move 32 bits from G (lo 1/4 xmm) to E (mem
       or lo 1/4 xmm). */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x11) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x11) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          /* fall through, we don't yet have a test case */
@@ -8759,21 +8760,21 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 59 = MULPS -- mul 32Fx4 from R/M to R */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x59) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x59) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "mulps", Iop_Mul32Fx4 );
       goto decode_success;
    }
 
    /* F3 0F 59 = MULSS -- mul 32F0x4 from R/M to R */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x59) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x59) {
       delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "mulss", Iop_Mul32F0x4 );
       goto decode_success;
    }
 
    /* 0F 56 = ORPS -- G = G and E */
    if (haveNo66noF2noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x56) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x56) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "orps", Iop_OrV128 );
       goto decode_success;
    }
@@ -8781,7 +8782,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F E0 = PAVGB -- 8x8 unsigned Packed Average, with rounding */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xE0) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE0) {
       do_MMX_preamble();
       delta = dis_MMXop_regmem_to_reg ( 
                 pfx, delta+2, insn[1], "pavgb", False );
@@ -8791,7 +8792,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F E3 = PAVGW -- 16x4 unsigned Packed Average, with rounding */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xE3) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE3) {
       do_MMX_preamble();
       delta = dis_MMXop_regmem_to_reg ( 
                 pfx, delta+2, insn[1], "pavgw", False );
@@ -8802,7 +8803,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F C5 = PEXTRW -- extract 16-bit field from mmx(E) and put 
       zero-extend of it in ireg(G). */
    if (haveNo66noF2noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0xC5) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xC5) {
       modrm = insn[2];
       if (epartIsReg(modrm)) {
          IRTemp sV = newTemp(Ity_I64);
@@ -8834,7 +8835,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
       put it into the specified lane of mmx(G). */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xC4) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xC4) {
       /* Use t0 .. t3 to hold the 4 original 16-bit lanes of the
          mmx reg.  t4 is the new lane value.  t5 is the original
          mmx value. t6 is the new mmx value. */
@@ -8879,7 +8880,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F EE = PMAXSW -- 16x4 signed max */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xEE) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xEE) {
       do_MMX_preamble();
       delta = dis_MMXop_regmem_to_reg ( 
                 pfx, delta+2, insn[1], "pmaxsw", False );
@@ -8889,7 +8890,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F DE = PMAXUB -- 8x8 unsigned max */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xDE) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xDE) {
       do_MMX_preamble();
       delta = dis_MMXop_regmem_to_reg ( 
                 pfx, delta+2, insn[1], "pmaxub", False );
@@ -8899,7 +8900,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F EA = PMINSW -- 16x4 signed min */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xEA) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xEA) {
       do_MMX_preamble();
       delta = dis_MMXop_regmem_to_reg ( 
                 pfx, delta+2, insn[1], "pminsw", False );
@@ -8909,7 +8910,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F DA = PMINUB -- 8x8 unsigned min */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xDA) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xDA) {
       do_MMX_preamble();
       delta = dis_MMXop_regmem_to_reg ( 
                 pfx, delta+2, insn[1], "pminub", False );
@@ -8921,7 +8922,7 @@ DisResult disInstr_AMD64_WRK ( 
       mmx(G), turn them into a byte, and put zero-extend of it in
       ireg(G). */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xD7) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD7) {
       modrm = insn[2];
       if (epartIsReg(modrm)) {
          do_MMX_preamble();
@@ -8945,7 +8946,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F E4 = PMULUH -- 16x4 hi-half of unsigned widening multiply */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xE4) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE4) {
       do_MMX_preamble();
       delta = dis_MMXop_regmem_to_reg ( 
                 pfx, delta+2, insn[1], "pmuluh", False );
@@ -8956,7 +8957,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 18 /1 = PREFETCH0   -- with various different hints */
    /* 0F 18 /2 = PREFETCH1 */
    /* 0F 18 /3 = PREFETCH2 */
-   if (insn[0] == 0x0F && insn[1] == 0x18
+   if (/* insn[0] == 0x0F && */ insn[1] == 0x18
        && haveNo66noF2noF3(pfx)
        && !epartIsReg(insn[2]) 
        && gregLO3ofRM(insn[2]) >= 0 && gregLO3ofRM(insn[2]) <= 3) {
@@ -8983,7 +8984,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F F6 = PSADBW -- sum of 8Ux8 absolute differences */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xF6) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xF6) {
       do_MMX_preamble();
       delta = dis_MMXop_regmem_to_reg ( 
                  pfx, delta+2, insn[1], "psadbw", False );
@@ -8993,7 +8994,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F 70 = PSHUFW -- rearrange 4x16 from E(mmx or mem) to G(mmx) */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x70) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x70) {
       Int order;
       IRTemp sV, dV, s3, s2, s1, s0;
       s3 = s2 = s1 = s0 = IRTemp_INVALID;
@@ -9032,7 +9033,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 53 = RCPPS -- approx reciprocal 32Fx4 from R/M to R */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x53) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x53) {
       delta = dis_SSE_E_to_G_unary_all( pfx, delta+2, 
                                         "rcpps", Iop_Recip32Fx4 );
       goto decode_success;
@@ -9040,7 +9041,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* F3 0F 53 = RCPSS -- approx reciprocal 32F0x4 from R/M to R */
    if (haveF3no66noF2(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x53) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x53) {
       delta = dis_SSE_E_to_G_unary_lo32( pfx, delta+2, 
                                          "rcpss", Iop_Recip32F0x4 );
       goto decode_success;
@@ -9048,7 +9049,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 52 = RSQRTPS -- approx reciprocal sqrt 32Fx4 from R/M to R */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x52) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x52) {
       delta = dis_SSE_E_to_G_unary_all( pfx, delta+2, 
                                         "rsqrtps", Iop_RSqrt32Fx4 );
       goto decode_success;
@@ -9056,7 +9057,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* F3 0F 52 = RSQRTSS -- approx reciprocal sqrt 32F0x4 from R/M to R */
    if (haveF3no66noF2(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x52) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x52) {
       delta = dis_SSE_E_to_G_unary_lo32( pfx, delta+2, 
                                          "rsqrtss", Iop_RSqrt32F0x4 );
       goto decode_success;
@@ -9064,7 +9065,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F AE /7 = SFENCE -- flush pending operations to memory */
    if (haveNo66noF2noF3(pfx) 
-       && insn[0] == 0x0F && insn[1] == 0xAE
+       /* && insn[0] == 0x0F */ && insn[1] == 0xAE
        && epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 7
        && sz == 4) {
       delta += 3;
@@ -9077,7 +9078,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F C6 /r ib = SHUFPS -- shuffle packed F32s */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xC6) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xC6) {
       Int    select;
       IRTemp sV, dV;
       IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
@@ -9125,7 +9126,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 51 = SQRTPS -- approx sqrt 32Fx4 from R/M to R */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x51) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x51) {
       delta = dis_SSE_E_to_G_unary_all( pfx, delta+2, 
                                         "sqrtps", Iop_Sqrt32Fx4 );
       goto decode_success;
@@ -9133,14 +9134,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* F3 0F 51 = SQRTSS -- approx sqrt 32F0x4 from R/M to R */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x51) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x51) {
       delta = dis_SSE_E_to_G_unary_lo32( pfx, delta+2, 
                                          "sqrtss", Iop_Sqrt32F0x4 );
       goto decode_success;
    }
 
    /* 0F AE /3 = STMXCSR m32 -- store %mxcsr */
-   if (insn[0] == 0x0F && insn[1] == 0xAE
+   if (/* insn[0] == 0x0F && */ insn[1] == 0xAE
        && haveNo66noF2noF3(pfx)
        && !epartIsReg(insn[2]) && gregLO3ofRM(insn[2]) == 3) {
 
@@ -9168,14 +9169,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 5C = SUBPS -- sub 32Fx4 from R/M to R */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x5C) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5C) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "subps", Iop_Sub32Fx4 );
       goto decode_success;
    }
 
    /* F3 0F 5C = SUBSS -- sub 32F0x4 from R/M to R */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x5C) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5C) {
       delta = dis_SSE_E_to_G_lo32( pfx, delta+2, "subss", Iop_Sub32F0x4 );
       goto decode_success;
    }
@@ -9184,7 +9185,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 14 = UNPCKLPS -- unpack and interleave low part F32s */
    /* These just appear to be special cases of SHUFPS */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) {
+       /* && insn[0] == 0x0F */ && (insn[1] == 0x15 || insn[1] == 0x14)) {
       IRTemp sV, dV;
       IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
       Bool hi = toBool(insn[1] == 0x15);
@@ -9223,7 +9224,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F 57 = XORPS -- G = G and E */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x57) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x57) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "xorps", Iop_XorV128 );
       goto decode_success;
    }
@@ -9238,13 +9239,13 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 58 = ADDPD -- add 32Fx4 from R/M to R */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x58) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x58) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "addpd", Iop_Add64Fx2 );
       goto decode_success;
    }
  
    /* F2 0F 58 = ADDSD -- add 64F0x2 from R/M to R */
-   if (haveF2no66noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x58) {
+   if (haveF2no66noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x58) {
       vassert(sz == 4);
       delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "addsd", Iop_Add64F0x2 );
       goto decode_success;
@@ -9252,28 +9253,28 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 55 = ANDNPD -- G = (not G) and E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x55) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x55) {
       delta = dis_SSE_E_to_G_all_invG( pfx, delta+2, "andnpd", Iop_AndV128 );
       goto decode_success;
    }
 
    /* 66 0F 54 = ANDPD -- G = G and E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x54) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x54) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "andpd", Iop_AndV128 );
       goto decode_success;
    }
 
    /* 66 0F C2 = CMPPD -- 64Fx2 comparison from R/M to R */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xC2) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xC2) {
       delta = dis_SSEcmp_E_to_G( pfx, delta+2, "cmppd", True, 8 );
       goto decode_success;
    }
 
    /* F2 0F C2 = CMPSD -- 64F0x2 comparison from R/M to R */
    if (haveF2no66noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0xC2) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xC2) {
       delta = dis_SSEcmp_E_to_G( pfx, delta+2, "cmpsd", False, 8 );
       goto decode_success;
    }
@@ -9281,7 +9282,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 66 0F 2F = COMISD  -- 64F0x2 comparison G,E, and set ZCP */
    /* 66 0F 2E = UCOMISD -- 64F0x2 comparison G,E, and set ZCP */
    if (have66noF2noF3(pfx) && sz == 2
-       && insn[0] == 0x0F && (insn[1] == 0x2F || insn[1] == 0x2E)) {
+       /* && insn[0] == 0x0F */ && (insn[1] == 0x2F || insn[1] == 0x2E)) {
       IRTemp argL = newTemp(Ity_F64);
       IRTemp argR = newTemp(Ity_F64);
       modrm = getUChar(delta+2);
@@ -9318,7 +9319,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* F3 0F E6 = CVTDQ2PD -- convert 2 x I32 in mem/lo half xmm to 2 x
       F64 in xmm(G) */
-   if (haveF3no66noF2(pfx) && insn[0] == 0x0F && insn[1] == 0xE6) {
+   if (haveF3no66noF2(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0xE6) {
       IRTemp arg64 = newTemp(Ity_I64);
       if (sz != 4) goto decode_failure;
 
@@ -9352,7 +9353,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 5B = CVTDQ2PS -- convert 4 x I32 in mem/xmm to 4 x F32 in
       xmm(G) */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x5B) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5B) {
       IRTemp argV  = newTemp(Ity_V128);
       IRTemp rmode = newTemp(Ity_I32);
 
@@ -9395,7 +9396,7 @@ DisResult disInstr_AMD64_WRK ( 
    if ( ( (haveF2no66noF3(pfx) && sz == 4)
           || (have66noF2noF3(pfx) && sz == 2)
         )
-        && insn[0] == 0x0F && insn[1] == 0xE6) {
+        /* && insn[0] == 0x0F */ && insn[1] == 0xE6) {
       IRTemp argV   = newTemp(Ity_V128);
       IRTemp rmode  = newTemp(Ity_I32);
       Bool   r2zero = toBool(sz == 2);
@@ -9448,7 +9449,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 66 0F 2C = CVTTPD2PI -- convert 2 x F64 in mem/xmm to 2 x
       I32 in mmx, rounding towards zero */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && (insn[1] == 0x2D || insn[1] == 0x2C)) {
+       /* && insn[0] == 0x0F */ && (insn[1] == 0x2D || insn[1] == 0x2C)) {
       IRTemp dst64  = newTemp(Ity_I64);
       IRTemp rmode  = newTemp(Ity_I32);
       IRTemp f64lo  = newTemp(Ity_F64);
@@ -9502,7 +9503,7 @@ DisResult disInstr_AMD64_WRK ( 
       been nicer to merge them together, but the insn[] offsets differ
       by one. */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x5A) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5A) {
       IRTemp argV  = newTemp(Ity_V128);
       IRTemp rmode = newTemp(Ity_I32);
 
@@ -9545,7 +9546,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 66 0F 2A = CVTPI2PD -- convert 2 x I32 in mem/mmx to 2 x F64 in
       xmm(G) */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x2A) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x2A) {
       IRTemp arg64 = newTemp(Ity_I64);
 
       modrm = getUChar(delta+2);
@@ -9583,7 +9584,7 @@ DisResult disInstr_AMD64_WRK ( 
    if ( ( (have66noF2noF3(pfx) && sz == 2)
           || (haveF3no66noF2(pfx) && sz == 4)
         )
-        && insn[0] == 0x0F && insn[1] == 0x5B) {
+        /* && insn[0] == 0x0F */ && insn[1] == 0x5B) {
       IRTemp argV   = newTemp(Ity_V128);
       IRTemp rmode  = newTemp(Ity_I32);
       Bool   r2zero = toBool(sz == 4);
@@ -9631,7 +9632,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F 5A = CVTPS2PD -- convert 2 x F32 in low half mem/xmm to 2 x
       F64 in xmm(G). */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x5A) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5A) {
       IRTemp f32lo = newTemp(Ity_F32);
       IRTemp f32hi = newTemp(Ity_F32);
 
@@ -9673,7 +9674,7 @@ DisResult disInstr_AMD64_WRK ( 
                     truncating towards zero 
    */
    if (haveF2no66noF3(pfx) 
-       && insn[0] == 0x0F 
+       /* && insn[0] == 0x0F */ 
        && (insn[1] == 0x2D || insn[1] == 0x2C)) {
       IRTemp rmode  = newTemp(Ity_I32);
       IRTemp f64lo  = newTemp(Ity_F64);
@@ -9716,7 +9717,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* F2 0F 5A = CVTSD2SS -- convert F64 in mem/low half xmm to F32 in
       low 1/4 xmm(G), according to prevailing SSE rounding mode */
    if (haveF2no66noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x5A) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5A) {
       IRTemp rmode = newTemp(Ity_I32);
       IRTemp f64lo = newTemp(Ity_F64);
       vassert(sz == 4);
@@ -9749,7 +9750,7 @@ DisResult disInstr_AMD64_WRK ( 
       when sz==8 -- convert I64 in mem/ireg to F64 in low half xmm
    */
    if (haveF2no66noF3(pfx) && (sz == 4 || sz == 8)
-       && insn[0] == 0x0F && insn[1] == 0x2A) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x2A) {
       modrm = getUChar(delta+2);
 
       if (sz == 4) {
@@ -9801,7 +9802,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* F3 0F 5A = CVTSS2SD -- convert F32 in mem/low 1/4 xmm to F64 in
       low half xmm(G) */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x5A) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5A) {
       IRTemp f32lo = newTemp(Ity_F32);
 
       modrm = getUChar(delta+2);
@@ -9826,13 +9827,13 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 5E = DIVPD -- div 64Fx2 from R/M to R */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x5E) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5E) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "divpd", Iop_Div64Fx2 );
       goto decode_success;
    }
 
    /* F2 0F 5E = DIVSD -- div 64F0x2 from R/M to R */
-   if (haveF2no66noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x5E) {
+   if (haveF2no66noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x5E) {
       vassert(sz == 4);
       delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "divsd", Iop_Div64F0x2 );
       goto decode_success;
@@ -9841,7 +9842,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F AE /5 = LFENCE -- flush pending operations to memory */
    /* 0F AE /6 = MFENCE -- flush pending operations to memory */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xAE
+       /* && insn[0] == 0x0F */ && insn[1] == 0xAE
        && epartIsReg(insn[2]) 
        && (gregLO3ofRM(insn[2]) == 5 || gregLO3ofRM(insn[2]) == 6)) {
       delta += 3;
@@ -9854,28 +9855,28 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 5F = MAXPD -- max 64Fx2 from R/M to R */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x5F) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5F) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "maxpd", Iop_Max64Fx2 );
       goto decode_success;
    }
 
    /* F2 0F 5F = MAXSD -- max 64F0x2 from R/M to R */
    if (haveF2no66noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x5F) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5F) {
       delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "maxsd", Iop_Max64F0x2 );
       goto decode_success;
    }
 
    /* 66 0F 5D = MINPD -- min 64Fx2 from R/M to R */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x5D) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5D) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "minpd", Iop_Min64Fx2 );
       goto decode_success;
    }
 
    /* F2 0F 5D = MINSD -- min 64F0x2 from R/M to R */
    if (haveF2no66noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x5D) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5D) {
       delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "minsd", Iop_Min64F0x2 );
       goto decode_success;
    }
@@ -9884,7 +9885,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 66 0F 10 = MOVUPD -- move from E (mem or xmm) to G (xmm). */
    /* 66 0F 6F = MOVDQA -- move from E (mem or xmm) to G (xmm). */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F 
+       /* && insn[0] == 0x0F */ 
        && (insn[1] == 0x28 || insn[1] == 0x10 || insn[1] == 0x6F)) {
       HChar* wot = insn[1]==0x28 ? "apd" :
                    insn[1]==0x10 ? "upd" : "dqa";
@@ -9908,7 +9909,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */
    /* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */
-   if (have66noF2noF3(pfx) && insn[0] == 0x0F 
+   if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */
        && (insn[1] == 0x29 || insn[1] == 0x11)) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
@@ -9925,7 +9926,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 6E = MOVD from ireg32/m32 to xmm lo 1/4, zeroing high 3/4 of xmm. */
    /*              or from ireg64/m64 to xmm lo 1/2, zeroing high 1/2 of xmm. */
-   if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x6E) {
+   if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x6E) {
       vassert(sz == 2 || sz == 8);
       if (sz == 2) sz = 4;
       modrm = getUChar(delta+2);
@@ -9963,7 +9964,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 7E = MOVD from xmm low 1/4 to ireg32 or m32. */
    /*              or from xmm low 1/2 to ireg64 or m64. */
-   if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x7E) {
+   if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x7E) {
       if (sz == 2) sz = 4;
       vassert(sz == 4 || sz == 8);
       modrm = getUChar(delta+2);
@@ -9995,7 +9996,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 7F = MOVDQA -- move from G (xmm) to E (mem or xmm). */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x7F) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x7F) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          delta += 2+1;
@@ -10014,7 +10015,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* F3 0F 6F = MOVDQU -- move from E (mem or xmm) to G (xmm). */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x6F) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x6F) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          putXMMReg( gregOfRexRM(pfx,modrm), 
@@ -10035,7 +10036,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* F3 0F 7F = MOVDQU -- move from G (xmm) to E (mem or xmm). */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x7F) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x7F) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          goto decode_failure; /* awaiting test case */
@@ -10055,7 +10056,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* F2 0F D6 = MOVDQ2Q -- move from E (lo half xmm, not mem) to G (mmx). */
    if (haveF2no66noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xD6) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD6) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          do_MMX_preamble();
@@ -10074,7 +10075,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 66 0F 16 = MOVHPD -- move from mem to high half of XMM. */
    /* These seems identical to MOVHPS.  This instruction encoding is
       completely crazy. */
-   if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x16) {
+   if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x16) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          /* fall through; apparently reg-reg is not possible */
@@ -10091,7 +10092,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 17 = MOVHPD -- move from high half of XMM to mem. */
    /* Again, this seems identical to MOVHPS. */
-   if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x17) {
+   if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x17) {
       if (!epartIsReg(insn[2])) {
          delta += 2;
          addr = disAMode ( &alen, pfx, delta, dis_buf, 0 );
@@ -10108,7 +10109,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 12 = MOVLPD -- move from mem to low half of XMM. */
    /* Identical to MOVLPS ? */
-   if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x12) {
+   if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x12) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          /* fall through; apparently reg-reg is not possible */
@@ -10126,7 +10127,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 13 = MOVLPD -- move from low half of XMM to mem. */
    /* Identical to MOVLPS ? */
-   if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x13) {
+   if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x13) {
       modrm = getUChar(delta+2);
       if (!epartIsReg(modrm)) {
          addr = disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
@@ -10144,7 +10145,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 66 0F 50 = MOVMSKPD - move 2 sign bits from 2 x F64 in xmm(E) to
       2 lowest bits of ireg(G) */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x50) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x50) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          Int src;
@@ -10171,7 +10172,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F E7 = MOVNTDQ -- for us, just a plain SSE store. */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xE7) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE7) {
       modrm = getUChar(delta+2);
       if (!epartIsReg(modrm)) {
          addr = disAMode ( &alen, pfx, delta+2, dis_buf, 0 );
@@ -10187,7 +10188,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 0F C3 = MOVNTI -- for us, just a plain ireg store. */
    if (haveNo66noF2noF3(pfx) &&
-       insn[0] == 0x0F && insn[1] == 0xC3) {
+       /* insn[0] == 0x0F && */ insn[1] == 0xC3) {
       vassert(sz == 4 || sz == 8);
       modrm = getUChar(delta+2);
       if (!epartIsReg(modrm)) {
@@ -10203,7 +10204,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F D6 = MOVQ -- move 64 bits from G (lo half xmm) to E (mem
       or lo half xmm).  */
-   if (have66noF2noF3(pfx) && insn[0] == 0x0F && insn[1] == 0xD6) {
+   if (have66noF2noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0xD6) {
       vassert(sz == 2);
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
@@ -10222,7 +10223,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* F3 0F D6 = MOVQ2DQ -- move from E (mmx) to G (lo half xmm, zero
       hi half). */
    if (haveF3no66noF2(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0xD6) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD6) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          do_MMX_preamble();
@@ -10244,10 +10245,10 @@ DisResult disInstr_AMD64_WRK ( 
       G (lo half xmm).  If E is mem, upper half of G is zeroed out.
       If E is reg, upper half of G is unchanged. */
    if ( (haveF2no66noF3(pfx) && sz == 4 
-         && insn[0] == 0x0F && insn[1] == 0x10)
+         /* && insn[0] == 0x0F */ && insn[1] == 0x10)
         || 
         (haveF3no66noF2(pfx) && sz == 4 
-         && insn[0] == 0x0F && insn[1] == 0x7E)
+         /* && insn[0] == 0x0F */ && insn[1] == 0x7E)
       ) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
@@ -10275,7 +10276,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* F2 0F 11 = MOVSD -- move 64 bits from G (lo half xmm) to E (mem
       or lo half xmm). */
    if (haveF2no66noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x11) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x11) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
          /* fall through, we don't yet have a test case */
@@ -10292,28 +10293,28 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 59 = MULPD -- mul 64Fx2 from R/M to R */
    if (have66noF2noF3(pfx) && sz == 2
-       && insn[0] == 0x0F && insn[1] == 0x59) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x59) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "mulpd", Iop_Mul64Fx2 );
       goto decode_success;
    }
 
    /* F2 0F 59 = MULSD -- mul 64F0x2 from R/M to R */
    if (haveF2no66noF3(pfx) && sz == 4
-       && insn[0] == 0x0F && insn[1] == 0x59) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x59) {
       delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "mulsd", Iop_Mul64F0x2 );
       goto decode_success;
    }
 
    /* 66 0F 56 = ORPD -- G = G and E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x56) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x56) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "orpd", Iop_OrV128 );
       goto decode_success;
    }
 
    /* 66 0F C6 /r ib = SHUFPD -- shuffle packed F64s */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xC6) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xC6) {
       Int    select;
       IRTemp sV = newTemp(Ity_V128);
       IRTemp dV = newTemp(Ity_V128);
@@ -10363,14 +10364,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 51 = SQRTPD -- approx sqrt 64Fx2 from R/M to R */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x51) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x51) {
       delta = dis_SSE_E_to_G_unary_all( pfx, delta+2, 
                                         "sqrtpd", Iop_Sqrt64Fx2 );
       goto decode_success;
    }
 
    /* F2 0F 51 = SQRTSD -- approx sqrt 64F0x2 from R/M to R */
-   if (haveF2no66noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x51) {
+   if (haveF2no66noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x51) {
       vassert(sz == 4);
       delta = dis_SSE_E_to_G_unary_lo64( pfx, delta+2, 
                                          "sqrtsd", Iop_Sqrt64F0x2 );
@@ -10379,13 +10380,13 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 5C = SUBPD -- sub 64Fx2 from R/M to R */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x5C) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x5C) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "subpd", Iop_Sub64Fx2 );
       goto decode_success;
    }
 
    /* F2 0F 5C = SUBSD -- sub 64F0x2 from R/M to R */
-   if (haveF2no66noF3(pfx) && insn[0] == 0x0F && insn[1] == 0x5C) {
+   if (haveF2no66noF3(pfx) /* && insn[0] == 0x0F */ && insn[1] == 0x5C) {
       vassert(sz == 4);
       delta = dis_SSE_E_to_G_lo64( pfx, delta+2, "subsd", Iop_Sub64F0x2 );
       goto decode_success;
@@ -10396,7 +10397,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* These just appear to be special cases of SHUFPS */
    if (have66noF2noF3(pfx) 
        && sz == 2 /* could be 8 if rex also present */
-       && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) {
+       /* && insn[0] == 0x0F */ && (insn[1] == 0x15 || insn[1] == 0x14)) {
       IRTemp s1 = newTemp(Ity_I64);
       IRTemp s0 = newTemp(Ity_I64);
       IRTemp d1 = newTemp(Ity_I64);
@@ -10441,14 +10442,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 57 = XORPD -- G = G xor E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x57) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x57) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "xorpd", Iop_XorV128 );
       goto decode_success;
    }
 
    /* 66 0F 6B = PACKSSDW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x6B) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x6B) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "packssdw", Iop_QNarrow32Sx4, True );
       goto decode_success;
@@ -10456,7 +10457,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 63 = PACKSSWB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x63) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x63) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "packsswb", Iop_QNarrow16Sx8, True );
       goto decode_success;
@@ -10464,7 +10465,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 67 = PACKUSWB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x67) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x67) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "packuswb", Iop_QNarrow16Ux8, True );
       goto decode_success;
@@ -10472,7 +10473,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F FC = PADDB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xFC) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xFC) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "paddb", Iop_Add8x16, False );
       goto decode_success;
@@ -10480,7 +10481,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F FE = PADDD */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xFE) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xFE) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "paddd", Iop_Add32x4, False );
       goto decode_success;
@@ -10489,7 +10490,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
    /* 0F D4 = PADDQ -- add 64x1 */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xD4) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD4) {
       do_MMX_preamble();
       delta = dis_MMXop_regmem_to_reg ( 
                 pfx, delta+2, insn[1], "paddq", False );
@@ -10498,7 +10499,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F D4 = PADDQ */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xD4) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD4) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "paddq", Iop_Add64x2, False );
       goto decode_success;
@@ -10506,7 +10507,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F FD = PADDW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xFD) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xFD) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "paddw", Iop_Add16x8, False );
       goto decode_success;
@@ -10514,7 +10515,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F EC = PADDSB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xEC) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xEC) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "paddsb", Iop_QAdd8Sx16, False );
       goto decode_success;
@@ -10522,7 +10523,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F ED = PADDSW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xED) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xED) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "paddsw", Iop_QAdd16Sx8, False );
       goto decode_success;
@@ -10530,7 +10531,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F DC = PADDUSB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xDC) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xDC) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "paddusb", Iop_QAdd8Ux16, False );
       goto decode_success;
@@ -10538,7 +10539,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F DD = PADDUSW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xDD) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xDD) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "paddusw", Iop_QAdd16Ux8, False );
       goto decode_success;
@@ -10546,21 +10547,21 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F DB = PAND */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xDB) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xDB) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "pand", Iop_AndV128 );
       goto decode_success;
    }
 
    /* 66 0F DF = PANDN */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xDF) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xDF) {
       delta = dis_SSE_E_to_G_all_invG( pfx, delta+2, "pandn", Iop_AndV128 );
       goto decode_success;
    }
 
    /* 66 0F E0 = PAVGB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xE0) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE0) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pavgb", Iop_Avg8Ux16, False );
       goto decode_success;
@@ -10568,7 +10569,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F E3 = PAVGW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xE3) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE3) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pavgw", Iop_Avg16Ux8, False );
       goto decode_success;
@@ -10576,7 +10577,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 74 = PCMPEQB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x74) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x74) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pcmpeqb", Iop_CmpEQ8x16, False );
       goto decode_success;
@@ -10584,7 +10585,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 76 = PCMPEQD */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x76) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x76) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pcmpeqd", Iop_CmpEQ32x4, False );
       goto decode_success;
@@ -10592,7 +10593,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 75 = PCMPEQW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x75) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x75) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pcmpeqw", Iop_CmpEQ16x8, False );
       goto decode_success;
@@ -10600,7 +10601,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 64 = PCMPGTB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x64) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x64) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pcmpgtb", Iop_CmpGT8Sx16, False );
       goto decode_success;
@@ -10608,7 +10609,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 66 = PCMPGTD */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x66) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x66) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pcmpgtd", Iop_CmpGT32Sx4, False );
       goto decode_success;
@@ -10616,7 +10617,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 65 = PCMPGTW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x65) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x65) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pcmpgtw", Iop_CmpGT16Sx8, False );
       goto decode_success;
@@ -10625,7 +10626,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 66 0F C5 = PEXTRW -- extract 16-bit field from xmm(E) and put 
       zero-extend of it in ireg(G). */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xC5) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xC5) {
       modrm = insn[2];
       if (epartIsReg(modrm)) {
          t5 = newTemp(Ity_V128);
@@ -10658,7 +10659,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 66 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
       put it into the specified lane of xmm(G). */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xC4) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xC4) {
       Int lane;
       t4 = newTemp(Ity_I16);
       modrm = insn[2];
@@ -10687,7 +10688,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F EE = PMAXSW -- 16x8 signed max */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xEE) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xEE) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pmaxsw", Iop_Max16Sx8, False );
       goto decode_success;
@@ -10695,7 +10696,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F DE = PMAXUB -- 8x16 unsigned max */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xDE) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xDE) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pmaxub", Iop_Max8Ux16, False );
       goto decode_success;
@@ -10703,7 +10704,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F EA = PMINSW -- 16x8 signed min */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xEA) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xEA) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pminsw", Iop_Min16Sx8, False );
       goto decode_success;
@@ -10711,7 +10712,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F DA = PMINUB -- 8x16 unsigned min */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xDA) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xDA) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pminub", Iop_Min8Ux16, False );
       goto decode_success;
@@ -10723,7 +10724,7 @@ DisResult disInstr_AMD64_WRK ( 
       therefore and call a helper. */
    /* UInt x86g_calculate_sse_pmovmskb ( ULong w64hi, ULong w64lo ); */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xD7) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD7) {
       modrm = insn[2];
       if (epartIsReg(modrm)) {
          t0 = newTemp(Ity_I64);
@@ -10747,7 +10748,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F E4 = PMULHUW -- 16x8 hi-half of unsigned widening multiply */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xE4) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE4) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pmulhuw", Iop_MulHi16Ux8, False );
       goto decode_success;
@@ -10755,7 +10756,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F E5 = PMULHW -- 16x8 hi-half of signed widening multiply */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xE5) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE5) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pmulhw", Iop_MulHi16Sx8, False );
       goto decode_success;
@@ -10763,7 +10764,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F D5 = PMULHL -- 16x8 multiply */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xD5) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD5) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "pmullw", Iop_Mul16x8, False );
       goto decode_success;
@@ -10773,7 +10774,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 0F F4 = PMULUDQ -- unsigned widening multiply of 32-lanes 0 x
       0 to form 64-bit result */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xF4) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xF4) {
       IRTemp sV = newTemp(Ity_I64);
       IRTemp dV = newTemp(Ity_I64);
       t1 = newTemp(Ity_I32);
@@ -10809,7 +10810,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* This is a really poor translation -- could be improved if
       performance critical */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xF4) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xF4) {
       IRTemp sV, dV;
       IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
       sV = newTemp(Ity_V128);
@@ -10845,14 +10846,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F EB = POR */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xEB) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xEB) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "por", Iop_OrV128 );
       goto decode_success;
    }
 
    /* 66 0F 70 = PSHUFD -- rearrange 4x32 from E(xmm or mem) to G(xmm) */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x70) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x70) {
       Int order;
       IRTemp sV, dV, s3, s2, s1, s0;
       s3 = s2 = s1 = s0 = IRTemp_INVALID;
@@ -10892,7 +10893,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* F3 0F 70 = PSHUFHW -- rearrange upper half 4x16 from E(xmm or
       mem) to G(xmm), and copy lower half */
    if (haveF3no66noF2(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x70) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x70) {
       Int order;
       IRTemp sVhi, dVhi, sV, dV, s3, s2, s1, s0;
       s3 = s2 = s1 = s0 = IRTemp_INVALID;
@@ -10938,7 +10939,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* F2 0F 70 = PSHUFLW -- rearrange lower half 4x16 from E(xmm or
       mem) to G(xmm), and copy upper half */
    if (haveF2no66noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0x70) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x70) {
       Int order;
       IRTemp sVlo, dVlo, sV, dV, s3, s2, s1, s0;
       s3 = s2 = s1 = s0 = IRTemp_INVALID;
@@ -10983,7 +10984,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 72 /6 ib = PSLLD by immediate */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x72
+       /* && insn[0] == 0x0F */ && insn[1] == 0x72
        && epartIsReg(insn[2])
        && gregLO3ofRM(insn[2]) == 6) {
       delta = dis_SSE_shiftE_imm( pfx, delta+2, "pslld", Iop_ShlN32x4 );
@@ -10992,7 +10993,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F F2 = PSLLD by E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xF2) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xF2) {
       delta = dis_SSE_shiftG_byE( pfx, delta+2, "pslld", Iop_ShlN32x4 );
       goto decode_success;
    }
@@ -11000,7 +11001,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 66 0F 73 /7 ib = PSLLDQ by immediate */
    /* note, if mem case ever filled in, 1 byte after amode */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x73
+       /* && insn[0] == 0x0F */ && insn[1] == 0x73
        && epartIsReg(insn[2])
        && gregLO3ofRM(insn[2]) == 7) {
       IRTemp sV, dV, hi64, lo64, hi64r, lo64r;
@@ -11061,7 +11062,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 73 /6 ib = PSLLQ by immediate */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x73
+       /* && insn[0] == 0x0F */ && insn[1] == 0x73
        && epartIsReg(insn[2])
        && gregLO3ofRM(insn[2]) == 6) {
       delta = dis_SSE_shiftE_imm( pfx, delta+2, "psllq", Iop_ShlN64x2 );
@@ -11070,14 +11071,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F F3 = PSLLQ by E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xF3) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xF3) {
       delta = dis_SSE_shiftG_byE( pfx, delta+2, "psllq", Iop_ShlN64x2 );
       goto decode_success;
    }
 
    /* 66 0F 71 /6 ib = PSLLW by immediate */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x71
+       /* && insn[0] == 0x0F */ && insn[1] == 0x71
        && epartIsReg(insn[2])
        && gregLO3ofRM(insn[2]) == 6) {
       delta = dis_SSE_shiftE_imm( pfx, delta+2, "psllw", Iop_ShlN16x8 );
@@ -11086,14 +11087,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F F1 = PSLLW by E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xF1) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xF1) {
       delta = dis_SSE_shiftG_byE( pfx, delta+2, "psllw", Iop_ShlN16x8 );
       goto decode_success;
    }
 
    /* 66 0F 72 /4 ib = PSRAD by immediate */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x72
+       /* && insn[0] == 0x0F */ && insn[1] == 0x72
        && epartIsReg(insn[2])
        && gregLO3ofRM(insn[2]) == 4) {
       delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrad", Iop_SarN32x4 );
@@ -11102,14 +11103,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F E2 = PSRAD by E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xE2) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE2) {
       delta = dis_SSE_shiftG_byE( pfx, delta+2, "psrad", Iop_SarN32x4 );
       goto decode_success;
    }
 
    /* 66 0F 71 /4 ib = PSRAW by immediate */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x71
+       /* && insn[0] == 0x0F */ && insn[1] == 0x71
        && epartIsReg(insn[2])
        && gregLO3ofRM(insn[2]) == 4) {
       delta = dis_SSE_shiftE_imm( pfx, delta+2, "psraw", Iop_SarN16x8 );
@@ -11118,14 +11119,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F E1 = PSRAW by E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xE1) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE1) {
       delta = dis_SSE_shiftG_byE( pfx, delta+2, "psraw", Iop_SarN16x8 );
       goto decode_success;
    }
 
    /* 66 0F 72 /2 ib = PSRLD by immediate */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x72
+       /* && insn[0] == 0x0F */ && insn[1] == 0x72
        && epartIsReg(insn[2])
        && gregLO3ofRM(insn[2]) == 2) {
       delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrld", Iop_ShrN32x4 );
@@ -11134,7 +11135,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F D2 = PSRLD by E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xD2) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD2) {
       delta = dis_SSE_shiftG_byE( pfx, delta+2, "psrld", Iop_ShrN32x4 );
       goto decode_success;
    }
@@ -11142,7 +11143,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* 66 0F 73 /3 ib = PSRLDQ by immediate */
    /* note, if mem case ever filled in, 1 byte after amode */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x73
+       /* && insn[0] == 0x0F */ && insn[1] == 0x73
        && epartIsReg(insn[2])
        && gregLO3ofRM(insn[2]) == 3) {
       IRTemp sV, dV, hi64, lo64, hi64r, lo64r;
@@ -11204,7 +11205,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 73 /2 ib = PSRLQ by immediate */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x73
+       /* && insn[0] == 0x0F */ && insn[1] == 0x73
        && epartIsReg(insn[2])
        && gregLO3ofRM(insn[2]) == 2) {
       delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrlq", Iop_ShrN64x2 );
@@ -11213,14 +11214,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F D3 = PSRLQ by E */
    if (have66noF2noF3(pfx) && sz == 2
-       && insn[0] == 0x0F && insn[1] == 0xD3) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD3) {
       delta = dis_SSE_shiftG_byE( pfx, delta+2, "psrlq", Iop_ShrN64x2 );
       goto decode_success;
    }
 
    /* 66 0F 71 /2 ib = PSRLW by immediate */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x71
+       /* && insn[0] == 0x0F */ && insn[1] == 0x71
        && epartIsReg(insn[2])
        && gregLO3ofRM(insn[2]) == 2) {
       delta = dis_SSE_shiftE_imm( pfx, delta+2, "psrlw", Iop_ShrN16x8 );
@@ -11229,14 +11230,14 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F D1 = PSRLW by E */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xD1) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD1) {
       delta = dis_SSE_shiftG_byE( pfx, delta+2, "psrlw", Iop_ShrN16x8 );
       goto decode_success;
    }
 
    /* 66 0F F8 = PSUBB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xF8) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xF8) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "psubb", Iop_Sub8x16, False );
       goto decode_success;
@@ -11244,7 +11245,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F FA = PSUBD */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xFA) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xFA) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "psubd", Iop_Sub32x4, False );
       goto decode_success;
@@ -11253,7 +11254,7 @@ DisResult disInstr_AMD64_WRK ( 
    /* ***--- this is an MMX class insn introduced in SSE2 ---*** */
    /* 0F FB = PSUBQ -- sub 64x1 */
    if (haveNo66noF2noF3(pfx) && sz == 4 
-       && insn[0] == 0x0F && insn[1] == 0xFB) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xFB) {
       do_MMX_preamble();
       delta = dis_MMXop_regmem_to_reg ( 
                 pfx, delta+2, insn[1], "psubq", False );
@@ -11262,7 +11263,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F FB = PSUBQ */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xFB) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xFB) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "psubq", Iop_Sub64x2, False );
       goto decode_success;
@@ -11270,7 +11271,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F F9 = PSUBW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xF9) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xF9) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "psubw", Iop_Sub16x8, False );
       goto decode_success;
@@ -11278,7 +11279,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F E8 = PSUBSB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xE8) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE8) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "psubsb", Iop_QSub8Sx16, False );
       goto decode_success;
@@ -11286,7 +11287,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F E9 = PSUBSW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xE9) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xE9) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "psubsw", Iop_QSub16Sx8, False );
       goto decode_success;
@@ -11294,7 +11295,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F D8 = PSUBSB */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xD8) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD8) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "psubusb", Iop_QSub8Ux16, False );
       goto decode_success;
@@ -11302,7 +11303,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F D9 = PSUBSW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xD9) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xD9) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "psubusw", Iop_QSub16Ux8, False );
       goto decode_success;
@@ -11310,7 +11311,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 68 = PUNPCKHBW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x68) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x68) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "punpckhbw",
                                  Iop_InterleaveHI8x16, True );
@@ -11319,7 +11320,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 6A = PUNPCKHDQ */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x6A) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x6A) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "punpckhdq",
                                  Iop_InterleaveHI32x4, True );
@@ -11328,7 +11329,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 6D = PUNPCKHQDQ */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x6D) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x6D) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "punpckhqdq",
                                  Iop_InterleaveHI64x2, True );
@@ -11337,7 +11338,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 69 = PUNPCKHWD */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x69) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x69) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "punpckhwd",
                                  Iop_InterleaveHI16x8, True );
@@ -11346,7 +11347,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 60 = PUNPCKLBW */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x60) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x60) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "punpcklbw",
                                  Iop_InterleaveLO8x16, True );
@@ -11355,7 +11356,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 62 = PUNPCKLDQ */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x62) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x62) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "punpckldq",
                                  Iop_InterleaveLO32x4, True );
@@ -11364,7 +11365,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 6C = PUNPCKLQDQ */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x6C) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x6C) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "punpcklqdq",
                                  Iop_InterleaveLO64x2, True );
@@ -11373,7 +11374,7 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F 61 = PUNPCKLWD */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0x61) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0x61) {
       delta = dis_SSEint_E_to_G( pfx, delta+2, 
                                  "punpcklwd",
                                  Iop_InterleaveLO16x8, True );
@@ -11382,13 +11383,13 @@ DisResult disInstr_AMD64_WRK ( 
 
    /* 66 0F EF = PXOR */
    if (have66noF2noF3(pfx) && sz == 2 
-       && insn[0] == 0x0F && insn[1] == 0xEF) {
+       /* && insn[0] == 0x0F */ && insn[1] == 0xEF) {
       delta = dis_SSE_E_to_G_all( pfx, delta+2, "pxor", Iop_XorV128 );
       goto decode_success;
    }
 
 //.. //--    /* FXSAVE/FXRSTOR m32 -- load/store the FPU/MMX/SSE state. */
-//.. //--    if (insn[0] == 0x0F && insn[1] == 0xAE 
+//.. //--    if (/* insn[0] == 0x0F && */ insn[1] == 0xAE 
 //.. //--        && (!epartIsReg(insn[2]))
 //.. //--        && (gregOfRM(insn[2]) == 1 || gregOfRM(insn[2]) == 0) ) {
 //.. //--       Bool store = gregOfRM(insn[2]) == 0;
@@ -11405,7 +11406,7 @@ DisResult disInstr_AMD64_WRK ( 
 //.. //--    }
 //.. //-- 
 //.. //--    /* CLFLUSH -- flush cache line */
-//.. //--    if (insn[0] == 0x0F && insn[1] == 0xAE
+//.. //--    if (/* insn[0] == 0x0F && */ insn[1] == 0xAE
 //.. //--        && (!epartIsReg(insn[2]))
 //.. //--        && (gregOfRM(insn[2]) == 7))
 //.. //--    {
@@ -11420,7 +11421,7 @@ DisResult disInstr_AMD64_WRK ( 
 //.. //--       DIP("clflush %s\n", dis_buf);
 //.. //--       goto decode_success;
 //.. //--    }
-
+   }
 
    /* ---------------------------------------------------- */
    /* --- end of the SSE/SSE2 decoder.                 --- */

valgrind-3.1.0-valgrind_h.patch:
 valgrind.h |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

--- NEW FILE valgrind-3.1.0-valgrind_h.patch ---
--- valgrind-3.1.0/include/valgrind.h.jj	2005-03-11 01:28:13.000000000 -0500
+++ valgrind-3.1.0/include/valgrind.h	2005-03-29 16:42:31.000000000 -0500
@@ -215,10 +215,11 @@ typedef
 
 #else /* NVALGRIND */
 
-int VALGRIND_PRINTF(const char *format, ...)
-   __attribute__((format(__printf__, 1, 2)));
-__attribute__((weak))
-int
+/* Modern GCC will optimize the static routine out if unused,
+   and unused attribute will shut down warnings about it.  */
+static int VALGRIND_PRINTF(const char *format, ...)
+   __attribute__((format(__printf__, 1, 2), __unused__));
+static int
 VALGRIND_PRINTF(const char *format, ...)
 {
    unsigned long _qzz_res;
@@ -230,10 +231,9 @@ VALGRIND_PRINTF(const char *format, ...)
    return (int)_qzz_res;
 }
 
-int VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
-   __attribute__((format(__printf__, 1, 2)));
-__attribute__((weak))
-int
+static int VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
+   __attribute__((format(__printf__, 1, 2), __unused__));
+static int
 VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
 {
    unsigned long _qzz_res;


Index: .cvsignore
===================================================================
RCS file: /cvs/dist/rpms/valgrind/devel/.cvsignore,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -r1.7 -r1.8
--- .cvsignore	11 Sep 2005 19:44:18 -0000	1.7
+++ .cvsignore	10 Jan 2006 10:36:37 -0000	1.8
@@ -1 +1 @@
-valgrind-3.0.1.tar.bz2
+valgrind-3.1.0.tar.bz2


Index: sources
===================================================================
RCS file: /cvs/dist/rpms/valgrind/devel/sources,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -r1.7 -r1.8
--- sources	11 Sep 2005 19:44:18 -0000	1.7
+++ sources	10 Jan 2006 10:36:37 -0000	1.8
@@ -1 +1 @@
-c29efdb7d1a93440f5644a6769054681  valgrind-3.0.1.tar.bz2
+d92156e9172dc6097e56c69ea9c88013  valgrind-3.1.0.tar.bz2


Index: valgrind.spec
===================================================================
RCS file: /cvs/dist/rpms/valgrind/devel/valgrind.spec,v
retrieving revision 1.24
retrieving revision 1.25
diff -u -r1.24 -r1.25
--- valgrind.spec	9 Dec 2005 22:43:44 -0000	1.24
+++ valgrind.spec	10 Jan 2006 10:36:37 -0000	1.25
@@ -1,19 +1,17 @@
 Summary: Tool for finding memory management bugs in programs
 Name: valgrind
-Version: 3.0.1
-Release: 2.1
+Version: 3.1.0
+Release: 1
 Epoch: 1
 Source0: http://www.valgrind.org/downloads/valgrind-%{version}.tar.bz2
-Patch1: valgrind-3.0.1-valgrind_h.patch
-Patch2: valgrind-3.0.1-amd64-highbase.patch
-Patch3: valgrind-3.0.1-biarch-hack.patch
-Patch4: valgrind-3.0.1-amd64-speedup.patch
-Patch5: valgrind-3.0.1-amd64-syscalls.patch
+Patch1: valgrind-3.1.0-valgrind_h.patch
+Patch2: valgrind-3.1.0-amd64-highbase.patch
+Patch3: valgrind-3.1.0-amd64-speedup.patch
 License: GPL
 URL: http://www.valgrind.org/
 Group: Development/Debuggers
 BuildRoot: %{_tmppath}/%{name}-root
-ExclusiveArch: %{ix86} x86_64
+ExclusiveArch: %{ix86} x86_64 ppc
 
 # Disable build root strip policy
 %define __spec_install_post /usr/lib/rpm/brp-compress || :
@@ -33,20 +31,23 @@
 %setup -q
 %patch1 -p1
 %ifarch x86_64
-%patch2 -p1
+#%patch2 -p1
 %endif
 %patch3 -p1
-%patch4 -p1
-%patch5 -p1
 
 %build
+%ifarch x86_64
+# Ugly hack - libgcc 32-bit package might not be installed
+mkdir -p libgcc/32
+touch libgcc/32/libgcc_s.a
+%configure CC="gcc -B `pwd`/libgcc/"
+%else
 %configure
-
-cp -a glibc-2.3.supp glibc-2.4.supp
+%endif
 
 # Force a specific set of default suppressions
 echo -n > default.supp
-for file in glibc-2.3.supp xfree-4.supp ; do
+for file in glibc-2.4.supp xfree-4.supp ; do
     cat $file >> default.supp
 done
 
@@ -70,6 +71,13 @@
 EOF
 gcc $RPM_OPT_FLAGS -o close_fds close_fds.c
 
+for i in `find . -type f \( -name *-amd64-linux -o -name *-x86-linux -o -name *-ppc-linux \)`; do
+  case "`file $i`" in
+    *ELF*executable*statically\ linked*)
+      objcopy -R .debug_loc -R .debug_frame -R .debug_ranges $i
+  esac
+done
+
 # test
 make check || :
 echo ===============TESTING===================
@@ -80,12 +88,15 @@
 rm -rf $RPM_BUILD_ROOT
 
 %makeinstall
-cp -a $RPM_BUILD_ROOT%{_bindir}/valgrind \
-  $RPM_BUILD_ROOT%{_libdir}/valgrind/valgrind
 mkdir docs.installed
 mv $RPM_BUILD_ROOT%{_datadir}/doc/valgrind/* docs.installed/
 rm -f docs.installed/*.ps
 
+%ifarch x86_64
+rm -rf $RPM_BUILD_ROOT%{_libdir}/valgrind/x86-linux
+ln -sf ../../lib/valgrind/x86-linux $RPM_BUILD_ROOT%{_libdir}/valgrind/x86-linux
+%endif
+
 %clean
 rm -rf $RPM_BUILD_ROOT
 
@@ -100,8 +111,9 @@
 %{_mandir}/man1/valgrind*
 
 %changelog
-* Fri Dec 09 2005 Jesse Keating <jkeating redhat com>
-- rebuilt
+* Mon Jan  9 2006 Jakub Jelinek <jakub redhat com> 3.1.0-1
+- upgrade to 3.1.0 (#174582)
+  - many bugfixes, ppc32 support
 
 * Thu Oct 13 2005 Jakub Jelinek <jakub redhat com> 3.0.1-2
 - remove Obsoletes for valgrind-callgrind, as it has been


--- valgrind-3.0.1-amd64-highbase.patch DELETED ---


--- valgrind-3.0.1-amd64-speedup.patch DELETED ---


--- valgrind-3.0.1-amd64-syscalls.patch DELETED ---


--- valgrind-3.0.1-biarch-hack.patch DELETED ---


--- valgrind-3.0.1-valgrind_h.patch DELETED ---


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