rpms/binutils/FC-6 binutils-2.17.50.0.6-bz4267.patch, NONE, 1.1 binutils-2.17.50.0.6-ppc-relbrlt-test.patch, NONE, 1.1 binutils-2.17.50.0.6-ppc64-version-script.patch, NONE, 1.1 binutils-2.17.50.0.6-rh235221.patch, NONE, 1.1 binutils-2.17.50.0.6-rh241252.patch, NONE, 1.1 binutils-2.17.50.0.6-sse4.patch, NONE, 1.1 binutils.spec, 1.105, 1.106
fedora-cvs-commits at redhat.com
fedora-cvs-commits at redhat.com
Wed Jun 27 18:52:53 UTC 2007
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Author: jakub
Update of /cvs/dist/rpms/binutils/FC-6
In directory cvs.devel.redhat.com:/tmp/cvs-serv32629/FC-6
Modified Files:
binutils.spec
Added Files:
binutils-2.17.50.0.6-bz4267.patch
binutils-2.17.50.0.6-ppc-relbrlt-test.patch
binutils-2.17.50.0.6-ppc64-version-script.patch
binutils-2.17.50.0.6-rh235221.patch
binutils-2.17.50.0.6-rh241252.patch
binutils-2.17.50.0.6-sse4.patch
Log Message:
auto-import binutils-2.17.50.0.6-5.fc6 on branch FC-6 from binutils-2.17.50.0.6-5.fc6.src.rpm
binutils-2.17.50.0.6-bz4267.patch:
elf32-ppc.c | 14 ++++++++------
1 files changed, 8 insertions(+), 6 deletions(-)
--- NEW FILE binutils-2.17.50.0.6-bz4267.patch ---
2007-03-29 Alan Modra <amodra at bigpond.net.au>
PR ld/4267
* elf32-ppc.c (allocate_dynrelocs): Set plt.offset to -1 for
unused entries. Don't clear plt.plist in loop.
--- bfd/elf32-ppc.c 26 Mar 2007 12:23:00 -0000 1.211
+++ bfd/elf32-ppc.c 29 Mar 2007 01:11:30 -0000 1.212
@@ -4500,13 +4500,15 @@ allocate_dynrelocs (struct elf_link_hash
}
else
ent->plt.offset = (bfd_vma) -1;
-
- if (!doneone)
- {
- h->plt.plist = NULL;
- h->needs_plt = 0;
- }
}
+ else
+ ent->plt.offset = (bfd_vma) -1;
+
+ if (!doneone)
+ {
+ h->plt.plist = NULL;
+ h->needs_plt = 0;
+ }
}
else
{
binutils-2.17.50.0.6-ppc-relbrlt-test.patch:
plt1.d | 20 ++++++++++++++++++++
plt1.s | 9 +++++++++
powerpc.exp | 5 ++++-
relbrlt.d | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
relbrlt.s | 34 ++++++++++++++++++++++++++++++++++
5 files changed, 117 insertions(+), 1 deletion(-)
--- NEW FILE binutils-2.17.50.0.6-ppc-relbrlt-test.patch ---
2006-10-24 Alan Modra <amodra at bigpond.net.au>
* ld-powerpc/plt1.s: New.
* ld-powerpc/plt1.d: New.
* ld-powerpc/relbrlt.s: New.
* ld-powerpc/relbrlt.d: New.
* ld-powerpc/powerpc.exp: Run them.
--- ld/testsuite/ld-powerpc/powerpc.exp 3 Mar 2006 09:32:01 -0000 1.15
+++ ld/testsuite/ld-powerpc/powerpc.exp 24 Oct 2006 13:29:37 -0000 1.16
@@ -1,5 +1,5 @@
# Expect script for ld-powerpc tests
-# Copyright 2002, 2003, 2005 Free Software Foundation
+# Copyright 2002, 2003, 2005, 2006 Free Software Foundation
#
# This file is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -143,4 +143,7 @@ run_ld_link_tests $ppcelftests
if [ supports_ppc64 ] then {
run_ld_link_tests $ppc64elftests
+ run_dump_test "relbrlt"
}
+
+run_dump_test "plt1"
--- ld/testsuite/ld-powerpc/plt1.d 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-powerpc/plt1.d 24 Oct 2006 13:29:37 -0000 1.1
@@ -0,0 +1,20 @@
+#source: plt1.s
+#as: -a32
+#objdump: -dr
+#target: powerpc*-*-*
+
+.*: file format elf32-powerpc
+
+Disassembly of section .text:
+
+0+ <_start>:
+ 0: 42 9f 00 05 bcl- 20,4\*cr7\+so,4 .*
+ 4: 7f c8 02 a6 mflr r30
+ 8: 3f de 00 00 addis r30,r30,0
+ a: R_PPC_REL16_HA _GLOBAL_OFFSET_TABLE_\+0x6
+ c: 3b de 00 0a addi r30,r30,10
+ e: R_PPC_REL16_LO _GLOBAL_OFFSET_TABLE_\+0xa
+ 10: 48 00 00 01 bl 10 .*
+ 10: R_PPC_PLTREL24 _exit
+ 14: 48 00 00 00 b 14 .*
+ 14: R_PPC_REL24 _start
--- ld/testsuite/ld-powerpc/plt1.s 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-powerpc/plt1.s 24 Oct 2006 13:29:37 -0000 1.1
@@ -0,0 +1,9 @@
+ .text
+ .global _start
+_start:
+ bcl 20,31,1f
+1: mflr 30
+ addis 30,30,(_GLOBAL_OFFSET_TABLE_-1b)@ha
+ addi 30,30,(_GLOBAL_OFFSET_TABLE_-1b)@l
+ bl _exit at plt
+ b _start
--- ld/testsuite/ld-powerpc/relbrlt.d 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-powerpc/relbrlt.d 24 Oct 2006 13:29:37 -0000 1.1
@@ -0,0 +1,50 @@
+#source: relbrlt.s
+#as: -a64
+#ld: -melf64ppc --emit-relocs
+#objdump: -dr
+
+.*: file format elf64-powerpc
+
+Disassembly of section \.text:
+
+0*100000a8 <_start>:
+ 100000a8: 49 bf 00 31 bl 11bf00d8 .*
+ 100000a8: R_PPC64_REL24 \.text\+0x37e0044
+ 100000ac: 60 00 00 00 nop
+ 100000b0: 49 bf 00 19 bl 11bf00c8 .*
+ 100000b0: R_PPC64_REL24 \.text\+0x3bf0020
+ 100000b4: 60 00 00 00 nop
+ 100000b8: 49 bf 00 25 bl 11bf00dc .*
+ 100000b8: R_PPC64_REL24 \.text\+0x57e0024
+ 100000bc: 60 00 00 00 nop
+ 100000c0: 00 00 00 00 \.long 0x0
+ 100000c4: 4b ff ff e4 b 100000a8 <_start>
+ \.\.\.
+
+0*11bf00c8 <.*plt_branch.*>:
+ 11bf00c8: 3d 82 05 7e addis r12,r2,1406
+ 11bf00cc: e9 6c 80 58 ld r11,-32680\(r12\)
+ 11bf00d0: 7d 69 03 a6 mtctr r11
+ 11bf00d4: 4e 80 04 20 bctr
+
+0*11bf00d8 <.*long_branch.*>:
+ 11bf00d8: 49 bf 00 14 b 137e00ec <far>
+ 11bf00d8: R_PPC64_REL24 \*ABS\*\+0x137e00ec
+
+0*11bf00dc <.*plt_branch.*>:
+ 11bf00dc: 3d 82 05 7e addis r12,r2,1406
+ 11bf00e0: e9 6c 80 60 ld r11,-32672\(r12\)
+ 11bf00e4: 7d 69 03 a6 mtctr r11
+ 11bf00e8: 4e 80 04 20 bctr
+ \.\.\.
+
+0*137e00ec <far>:
+ 137e00ec: 4e 80 00 20 blr
+ \.\.\.
+
+0*13bf00c8 <far2far>:
+ 13bf00c8: 4e 80 00 20 blr
+ \.\.\.
+
+0*157e00cc <huge>:
+ 157e00cc: 4e 80 00 20 blr
--- ld/testsuite/ld-powerpc/relbrlt.s 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-powerpc/relbrlt.s 24 Oct 2006 13:29:37 -0000 1.1
@@ -0,0 +1,34 @@
+ .text
+ .global _start
+_start:
+1:
+ bl far
+ nop
+ bl far2far
+ nop
+ bl huge
+ nop
+ .long 0
+ b 1b
+ .space 0x1bf0000
+
+ .section .text.pad1,"ax"
+ .space 0x1bf0000
+
+ .section .text.far,"ax"
+far:
+ blr
+
+ .section .text.pad2,"ax"
+ .space 0x40ffd8
+
+ .section .text.far2far,"ax"
+far2far:
+ blr
+
+ .section .text.pad3,"ax"
+ .space 0x1bf0000
+
+ .section .text.huge,"ax"
+huge:
+ blr
binutils-2.17.50.0.6-ppc64-version-script.patch:
emultempl/ppc64elf.em | 17 +++++++++++------
testsuite/ld-elf/dl2a.list | 3 +++
testsuite/ld-elf/shared.exp | 3 +++
3 files changed, 17 insertions(+), 6 deletions(-)
--- NEW FILE binutils-2.17.50.0.6-ppc64-version-script.patch ---
2007-05-14 Andreas Schwab <schwab at suse.de>
* emultempl/ppc64elf.em (gld${EMULATION_NAME}_new_vers_pattern):
Handle null pattern.
--- ld/emultempl/ppc64elf.em 26 Mar 2007 11:10:44 -0000 1.52
+++ ld/emultempl/ppc64elf.em 14 May 2007 08:53:23 -0000 1.53
@@ -414,17 +414,22 @@ gld${EMULATION_NAME}_new_vers_pattern (s
unsigned int len;
char *dot_pat;
- if (!dotsyms || entry->pattern[0] == '*' || entry->pattern[0] == '.')
+ if (!dotsyms
+ || (entry->pattern != NULL
+ && (entry->pattern[0] == '*' || entry->pattern[0] == '.')))
return entry;
dot_entry = xmalloc (sizeof *dot_entry);
*dot_entry = *entry;
dot_entry->next = entry;
- len = strlen (entry->pattern) + 2;
- dot_pat = xmalloc (len);
- dot_pat[0] = '.';
- memcpy (dot_pat + 1, entry->pattern, len - 1);
- dot_entry->pattern = dot_pat;
+ if (entry->pattern != NULL)
+ {
+ len = strlen (entry->pattern) + 2;
+ dot_pat = xmalloc (len);
+ dot_pat[0] = '.';
+ memcpy (dot_pat + 1, entry->pattern, len - 1);
+ dot_entry->pattern = dot_pat;
+ }
if (entry->symbol != NULL)
{
len = strlen (entry->symbol) + 2;
* ld-elf/dl2a.list: New file.
* ld-elf/shared.exp: Add test using --dynamic-list=dl2a.list.
--- ld/testsuite/ld-elf/dl2a.list 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-elf/dl2a.list 14 May 2007 08:53:23 -0000 1.1
@@ -0,0 +1,3 @@
+{
+ "foo";
+};
--- ld/testsuite/ld-elf/shared.exp 14 Feb 2007 14:15:52 -0000 1.6
+++ ld/testsuite/ld-elf/shared.exp 15 May 2007 13:57:03 -0000 1.8
@@ -72,6 +72,9 @@ set build_tests {
{"Build libdl2a.so with --dynamic-list=dl2.list"
"-shared -Wl,--dynamic-list=dl2.list" "-fPIC"
{dl2.c dl2xxx.c} {} "libdl2a.so"}
+ {"Build libdl2a.so with --dynamic-list=dl2a.list"
+ "-shared -Wl,--dynamic-list=dl2a.list" "-fPIC"
+ {dl2.c dl2xxx.c} {} "libdl2a.so"}
{"Build libdl2b.so with --dynamic-list=dl2.list and dl2xxx.list"
"-shared -Wl,--dynamic-list=dl2.list,--dynamic-list=dl2xxx.list" "-fPIC"
{dl2.c dl2xxx.c} {} "libdl2b.so"}
binutils-2.17.50.0.6-rh235221.patch:
bfd/elf64-ppc.c | 99 ++++++++++++++++++++++--------------
ld/emulparams/elf64ppc.sh | 3 -
ld/emultempl/ppc64elf.em | 2
ld/testsuite/ld-powerpc/relbrlt.d | 66 ++++++++++++------------
ld/testsuite/ld-powerpc/tlsexe.r | 40 +++++++-------
ld/testsuite/ld-powerpc/tlsexetoc.r | 38 ++++++-------
ld/testsuite/ld-powerpc/tlsso.r | 4 -
ld/testsuite/ld-powerpc/tlstocso.r | 4 -
8 files changed, 140 insertions(+), 116 deletions(-)
--- NEW FILE binutils-2.17.50.0.6-rh235221.patch ---
2007-02-13 Alan Modra <amodra at bigpond.net.au>
* elf64-ppc.c (create_linkage_sections): Use section ".branch_lt"
for branch lookup table.
* emulparams/elf64ppc.sh (OTHER_READWRITE_SECTIONS): Add ".branch_lt".
* emultempl/ppc64elf.em (ppc_add_stub_section): Create without
SEC_RELOC flag set.
* ld-powerpc/relbrlt.d: Update.
* ld-powerpc/tlsexe.r: Update.
* ld-powerpc/tlsexetoc.r: Update.
* ld-powerpc/tlsso.r: Update.
* ld-powerpc/tlstocso.r: Update.
2007-02-12 Alan Modra <amodra at bigpond.net.au>
* elf64-ppc.c (create_linkage_sections): Don't create
.rela.rodata.brlt for --emit-relocs.
(ppc_build_one_stub): Create relocs for brlt --emit-relocs here.
(ppc_size_one_stub): Count them. Simplify test of stub type
when counting stub relocs. Set SEC_RELOC too.
(ppc64_elf_size_stubs): Clear reloc_count and SEC_RELOC.
(ppc64_elf_finish_dynamic_sections): Output brlt relocs.
* ld-powerpc/relbrlt.d: Update.
--- bfd/elf64-ppc.c 1 Feb 2007 05:35:58 -0000 1.255
+++ bfd/elf64-ppc.c 13 Feb 2007 01:53:02 -0000 1.257
@@ -3818,45 +3818,22 @@ create_linkage_sections (bfd *dynobj, st
return FALSE;
/* Create branch lookup table for plt_branch stubs. */
- if (info->shared)
- {
- flags = (SEC_ALLOC | SEC_LOAD
- | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED);
- htab->brlt
- = bfd_make_section_anyway_with_flags (dynobj, ".data.rel.ro.brlt",
- flags);
- }
- else
- {
- flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY
- | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED);
- htab->brlt
- = bfd_make_section_anyway_with_flags (dynobj, ".rodata.brlt", flags);
- }
-
+ flags = (SEC_ALLOC | SEC_LOAD
+ | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED);
+ htab->brlt = bfd_make_section_anyway_with_flags (dynobj, ".branch_lt",
+ flags);
if (htab->brlt == NULL
|| ! bfd_set_section_alignment (dynobj, htab->brlt, 3))
return FALSE;
- if (info->shared)
- {
- flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY
- | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED);
- htab->relbrlt
- = bfd_make_section_anyway_with_flags (dynobj, ".rela.data.rel.ro.brlt",
- flags);
- }
- else if (info->emitrelocations)
- {
- flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY
- | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED);
- htab->relbrlt
- = bfd_make_section_anyway_with_flags (dynobj, ".rela.rodata.brlt",
- flags);
- }
- else
+ if (!info->shared)
return TRUE;
+ flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY
+ | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED);
+ htab->relbrlt = bfd_make_section_anyway_with_flags (dynobj,
+ ".rela.branch_lt",
+ flags);
if (!htab->relbrlt
|| ! bfd_set_section_alignment (dynobj, htab->relbrlt, 3))
return FALSE;
@@ -8394,6 +8371,33 @@ ppc_build_one_stub (struct bfd_hash_entr
rl += htab->relbrlt->reloc_count++ * sizeof (Elf64_External_Rela);
bfd_elf64_swap_reloca_out (htab->relbrlt->owner, &rela, rl);
}
+ else if (info->emitrelocations)
+ {
+ Elf_Internal_Rela *relocs, *r;
+ struct bfd_elf_section_data *elfsec_data;
+
+ elfsec_data = elf_section_data (htab->brlt);
+ relocs = elfsec_data->relocs;
+ if (relocs == NULL)
+ {
+ bfd_size_type relsize;
+ relsize = htab->brlt->reloc_count * sizeof (*relocs);
+ relocs = bfd_alloc (htab->brlt->owner, relsize);
+ if (relocs == NULL)
+ return FALSE;
+ elfsec_data->relocs = relocs;
+ elfsec_data->rel_hdr.sh_size = relsize;
+ elfsec_data->rel_hdr.sh_entsize = 24;
+ htab->brlt->reloc_count = 0;
+ }
+ r = relocs + htab->brlt->reloc_count;
+ htab->brlt->reloc_count += 1;
+ r->r_offset = (br_entry->offset
+ + htab->brlt->output_offset
+ + htab->brlt->output_section->vma);
+ r->r_info = ELF64_R_INFO (0, R_PPC64_RELATIVE);
+ r->r_addend = off;
+ }
off = (br_entry->offset
+ htab->brlt->output_offset
@@ -8623,6 +8627,11 @@ ppc_size_one_stub (struct bfd_hash_entry
if (htab->relbrlt != NULL)
htab->relbrlt->size += sizeof (Elf64_External_Rela);
+ else if (info->emitrelocations)
+ {
+ htab->brlt->reloc_count += 1;
+ htab->brlt->flags |= SEC_RELOC;
+ }
}
stub_entry->stub_type += ppc_stub_plt_branch - ppc_stub_long_branch;
@@ -8630,11 +8639,11 @@ ppc_size_one_stub (struct bfd_hash_entry
if (stub_entry->stub_type != ppc_stub_plt_branch)
size = 28;
}
-
- if (info->emitrelocations
- && (stub_entry->stub_type == ppc_stub_long_branch
- || stub_entry->stub_type == ppc_stub_long_branch_r2off))
- stub_entry->stub_sec->reloc_count += 1;
+ else if (info->emitrelocations)
+ {
+ stub_entry->stub_sec->reloc_count += 1;
+ stub_entry->stub_sec->flags |= SEC_RELOC;
+ }
}
stub_entry->stub_sec->size += size;
@@ -9426,9 +9435,12 @@ ppc64_elf_size_stubs (bfd *output_bfd,
stub_sec->rawsize = stub_sec->size;
stub_sec->size = 0;
stub_sec->reloc_count = 0;
+ stub_sec->flags &= ~SEC_RELOC;
}
htab->brlt->size = 0;
+ htab->brlt->reloc_count = 0;
+ htab->brlt->flags &= ~SEC_RELOC;
if (htab->relbrlt != NULL)
htab->relbrlt->size = 0;
@@ -11442,6 +11454,17 @@ ppc64_elf_finish_dynamic_sections (bfd *
= PLT_ENTRY_SIZE;
}
+ /* brlt is SEC_LINKER_CREATED, so we need to write out relocs for
+ brlt ourselves if emitrelocations. */
+ if (htab->brlt != NULL
+ && htab->brlt->reloc_count != 0
+ && !_bfd_elf_link_output_relocs (output_bfd,
+ htab->brlt,
+ &elf_section_data (htab->brlt)->rel_hdr,
+ elf_section_data (htab->brlt)->relocs,
+ NULL))
+ return FALSE;
+
/* We need to handle writing out multiple GOT sections ourselves,
since we didn't add them to DYNOBJ. We know dynobj is the first
bfd. */
--- ld/emulparams/elf64ppc.sh 30 May 2006 16:45:32 -0000 1.18
+++ ld/emulparams/elf64ppc.sh 13 Feb 2007 01:53:03 -0000 1.19
@@ -31,7 +31,8 @@ OTHER_GOT_RELOC_SECTIONS="
.rela.toc ${RELOCATING-0} : { *(.rela.toc) }"
OTHER_READWRITE_SECTIONS="
.toc1 ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { *(.toc1) }
- .opd ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { KEEP (*(.opd)) }"
+ .opd ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { KEEP (*(.opd)) }
+ .branch_lt ${RELOCATING-0} :${RELOCATING+ ALIGN(8)} { *(.branch_lt) }"
# Treat a host that matches the target with the possible exception of "64"
# in the name as if it were native.
--- ld/emultempl/ppc64elf.em 20 Jun 2006 02:22:14 -0000 1.50
+++ ld/emultempl/ppc64elf.em 13 Feb 2007 01:53:03 -0000 1.51
@@ -225,7 +225,7 @@ ppc_add_stub_section (const char *stub_s
goto err_ret;
flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
- | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY | SEC_KEEP);
+ | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_KEEP);
if (!bfd_set_section_flags (stub_file->the_bfd, stub_sec, flags))
goto err_ret;
--- ld/testsuite/ld-powerpc/relbrlt.d 24 Oct 2006 13:29:37 -0000 1.1
+++ ld/testsuite/ld-powerpc/relbrlt.d 13 Feb 2007 01:53:03 -0000 1.3
@@ -7,44 +7,44 @@
Disassembly of section \.text:
-0*100000a8 <_start>:
- 100000a8: 49 bf 00 31 bl 11bf00d8 .*
- 100000a8: R_PPC64_REL24 \.text\+0x37e0044
- 100000ac: 60 00 00 00 nop
- 100000b0: 49 bf 00 19 bl 11bf00c8 .*
- 100000b0: R_PPC64_REL24 \.text\+0x3bf0020
- 100000b4: 60 00 00 00 nop
- 100000b8: 49 bf 00 25 bl 11bf00dc .*
- 100000b8: R_PPC64_REL24 \.text\+0x57e0024
- 100000bc: 60 00 00 00 nop
- 100000c0: 00 00 00 00 \.long 0x0
- 100000c4: 4b ff ff e4 b 100000a8 <_start>
+0*100000b0 <_start>:
+[0-9a-f ]*: 49 bf 00 31 bl .*
+[0-9a-f ]*: R_PPC64_REL24 \.text\+0x37e0044
+[0-9a-f ]*: 60 00 00 00 nop
+[0-9a-f ]*: 49 bf 00 19 bl .*
+[0-9a-f ]*: R_PPC64_REL24 \.text\+0x3bf0020
+[0-9a-f ]*: 60 00 00 00 nop
+[0-9a-f ]*: 49 bf 00 25 bl .*
+[0-9a-f ]*: R_PPC64_REL24 \.text\+0x57e0024
+[0-9a-f ]*: 60 00 00 00 nop
+[0-9a-f ]*: 00 00 00 00 \.long 0x0
+[0-9a-f ]*: 4b ff ff e4 b .* <_start>
\.\.\.
-0*11bf00c8 <.*plt_branch.*>:
- 11bf00c8: 3d 82 05 7e addis r12,r2,1406
- 11bf00cc: e9 6c 80 58 ld r11,-32680\(r12\)
- 11bf00d0: 7d 69 03 a6 mtctr r11
- 11bf00d4: 4e 80 04 20 bctr
-
-0*11bf00d8 <.*long_branch.*>:
- 11bf00d8: 49 bf 00 14 b 137e00ec <far>
- 11bf00d8: R_PPC64_REL24 \*ABS\*\+0x137e00ec
-
-0*11bf00dc <.*plt_branch.*>:
- 11bf00dc: 3d 82 05 7e addis r12,r2,1406
- 11bf00e0: e9 6c 80 60 ld r11,-32672\(r12\)
- 11bf00e4: 7d 69 03 a6 mtctr r11
- 11bf00e8: 4e 80 04 20 bctr
+[0-9a-f ]*<.*plt_branch.*>:
+[0-9a-f ]*: 3d 82 00 00 addis r12,r2,0
+[0-9a-f ]*: e9 6c 80 00 ld r11,-32768\(r12\)
+[0-9a-f ]*: 7d 69 03 a6 mtctr r11
+[0-9a-f ]*: 4e 80 04 20 bctr
+
+[0-9a-f ]*<.*long_branch.*>:
+[0-9a-f ]*: 49 bf 00 14 b .* <far>
+[0-9a-f ]*: R_PPC64_REL24 \*ABS\*\+0x137e00f4
+
+[0-9a-f ]*<.*plt_branch.*>:
+[0-9a-f ]*: 3d 82 00 00 addis r12,r2,0
+[0-9a-f ]*: e9 6c 80 08 ld r11,-32760\(r12\)
+[0-9a-f ]*: 7d 69 03 a6 mtctr r11
+[0-9a-f ]*: 4e 80 04 20 bctr
\.\.\.
-0*137e00ec <far>:
- 137e00ec: 4e 80 00 20 blr
+0*137e00f4 <far>:
+[0-9a-f ]*: 4e 80 00 20 blr
\.\.\.
-0*13bf00c8 <far2far>:
- 13bf00c8: 4e 80 00 20 blr
+[0-9a-f ]*<far2far>:
+[0-9a-f ]*: 4e 80 00 20 blr
\.\.\.
-0*157e00cc <huge>:
- 157e00cc: 4e 80 00 20 blr
+[0-9a-f ]*<huge>:
+[0-9a-f ]*: 4e 80 00 20 blr
--- ld/testsuite/ld-powerpc/tlsexe.r 17 Aug 2006 08:21:06 -0000 1.18
+++ ld/testsuite/ld-powerpc/tlsexe.r 13 Feb 2007 01:53:03 -0000 1.19
@@ -17,10 +17,10 @@ Section Headers:
+\[ 5\] \.rela\.dyn +.*
+\[ 6\] \.rela\.plt +.*
+\[ 7\] \.text +PROGBITS .* 0+100 0+ +AX +0 +0 +8
- +\[ 8\] \.rodata + PROGBITS .* 0+ 0+ +A +0 +0 +8
- +\[ 9\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
- +\[10\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
- +\[11\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8
+ +\[ 8\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[ 9\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[10\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8
+ +\[11\] \.branch_lt + PROGBITS .* 0+ 0+ +WA +0 +0 +8
+\[12\] \.got +PROGBITS .* 0+30 08 +WA +0 +0 +8
+\[13\] \.plt +.*
+\[14\] \.shstrtab +.*
@@ -67,7 +67,7 @@ Symbol table '\.dynsym' contains [0-9]+
.* TLS +GLOBAL DEFAULT +UND gd
.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
.* TLS +GLOBAL DEFAULT +UND ld
-.* TLS +GLOBAL DEFAULT +10 ld2
+.* TLS +GLOBAL DEFAULT +9 ld2
.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
.* NOTYPE +GLOBAL DEFAULT +ABS _edata
.* NOTYPE +GLOBAL DEFAULT +ABS _end
@@ -88,26 +88,26 @@ Symbol table '\.symtab' contains .* entr
.* SECTION LOCAL +DEFAULT +11
.* SECTION LOCAL +DEFAULT +12
.* SECTION LOCAL +DEFAULT +13
-.* TLS +LOCAL +DEFAULT +9 gd4
-.* TLS +LOCAL +DEFAULT +9 ld4
-.* TLS +LOCAL +DEFAULT +9 ld5
-.* TLS +LOCAL +DEFAULT +9 ld6
-.* TLS +LOCAL +DEFAULT +9 ie4
-.* TLS +LOCAL +DEFAULT +9 le4
-.* TLS +LOCAL +DEFAULT +9 le5
-.* OBJECT +LOCAL +HIDDEN +11 _DYNAMIC
+.* TLS +LOCAL +DEFAULT +8 gd4
+.* TLS +LOCAL +DEFAULT +8 ld4
+.* TLS +LOCAL +DEFAULT +8 ld5
+.* TLS +LOCAL +DEFAULT +8 ld6
+.* TLS +LOCAL +DEFAULT +8 ie4
+.* TLS +LOCAL +DEFAULT +8 le4
+.* TLS +LOCAL +DEFAULT +8 le5
+.* OBJECT +LOCAL +HIDDEN +10 _DYNAMIC
.* FUNC +LOCAL +DEFAULT +UND \.__tls_get_addr
.* GLOBAL DEFAULT +UND gd
-.* GLOBAL DEFAULT +10 le0
+.* GLOBAL DEFAULT +9 le0
.* GLOBAL DEFAULT +UND __tls_get_addr
-.* GLOBAL DEFAULT +10 ld0
-.* GLOBAL DEFAULT +10 le1
+.* GLOBAL DEFAULT +9 ld0
+.* GLOBAL DEFAULT +9 le1
.* GLOBAL DEFAULT +UND ld
.* NOTYPE +GLOBAL DEFAULT +7 _start
-.* TLS +GLOBAL DEFAULT +10 ld2
-.* TLS +GLOBAL DEFAULT +10 ld1
+.* TLS +GLOBAL DEFAULT +9 ld2
+.* TLS +GLOBAL DEFAULT +9 ld1
.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
.* NOTYPE +GLOBAL DEFAULT +ABS _edata
.* NOTYPE +GLOBAL DEFAULT +ABS _end
-.* TLS +GLOBAL DEFAULT +10 gd0
-.* TLS +GLOBAL DEFAULT +10 ie0
+.* TLS +GLOBAL DEFAULT +9 gd0
+.* TLS +GLOBAL DEFAULT +9 ie0
--- ld/testsuite/ld-powerpc/tlsexetoc.r 17 Aug 2006 08:21:06 -0000 1.19
+++ ld/testsuite/ld-powerpc/tlsexetoc.r 13 Feb 2007 01:53:03 -0000 1.20
@@ -17,10 +17,10 @@ Section Headers:
+\[ 5\] \.rela\.dyn +.*
+\[ 6\] \.rela\.plt +.*
+\[ 7\] \.text +PROGBITS .* 0+c0 0+ +AX +0 +0 +8
- +\[ 8\] \.rodata +PROGBITS .* 0+ 0+ +A +0 +0 +8
- +\[ 9\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
- +\[10\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
- +\[11\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8
+ +\[ 8\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[ 9\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[10\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8
+ +\[11\] \.branch_lt +PROGBITS .* 0+ 0+ +WA +0 +0 +8
+\[12\] \.got +PROGBITS .* 0+58 08 +WA +0 +0 +8
+\[13\] \.plt +.*
+\[14\] \.shstrtab +.*
@@ -87,27 +87,27 @@ Symbol table '\.symtab' contains .* entr
.* SECTION LOCAL +DEFAULT +11
.* SECTION LOCAL +DEFAULT +12
.* SECTION LOCAL +DEFAULT +13
-.* TLS +LOCAL +DEFAULT +9 gd4
-.* TLS +LOCAL +DEFAULT +9 ld4
-.* TLS +LOCAL +DEFAULT +9 ld5
-.* TLS +LOCAL +DEFAULT +9 ld6
-.* TLS +LOCAL +DEFAULT +9 ie4
-.* TLS +LOCAL +DEFAULT +9 le4
-.* TLS +LOCAL +DEFAULT +9 le5
+.* TLS +LOCAL +DEFAULT +8 gd4
+.* TLS +LOCAL +DEFAULT +8 ld4
+.* TLS +LOCAL +DEFAULT +8 ld5
+.* TLS +LOCAL +DEFAULT +8 ld6
+.* TLS +LOCAL +DEFAULT +8 ie4
+.* TLS +LOCAL +DEFAULT +8 le4
+.* TLS +LOCAL +DEFAULT +8 le5
.* NOTYPE +LOCAL +DEFAULT +12 \.Lie0
-.* OBJECT +LOCAL +HIDDEN +11 _DYNAMIC
+.* OBJECT +LOCAL +HIDDEN +10 _DYNAMIC
.* FUNC +LOCAL +DEFAULT +UND \.__tls_get_addr
.* TLS +GLOBAL DEFAULT +UND gd
-.* TLS +GLOBAL DEFAULT +10 le0
+.* TLS +GLOBAL DEFAULT +9 le0
.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
-.* TLS +GLOBAL DEFAULT +10 ld0
-.* TLS +GLOBAL DEFAULT +10 le1
+.* TLS +GLOBAL DEFAULT +9 ld0
+.* TLS +GLOBAL DEFAULT +9 le1
.* TLS +GLOBAL DEFAULT +UND ld
.* NOTYPE +GLOBAL DEFAULT +7 _start
-.* TLS +GLOBAL DEFAULT +10 ld2
-.* TLS +GLOBAL DEFAULT +10 ld1
+.* TLS +GLOBAL DEFAULT +9 ld2
+.* TLS +GLOBAL DEFAULT +9 ld1
.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
.* NOTYPE +GLOBAL DEFAULT +ABS _edata
.* NOTYPE +GLOBAL DEFAULT +ABS _end
-.* TLS +GLOBAL DEFAULT +10 gd0
-.* TLS +GLOBAL DEFAULT +10 ie0
+.* TLS +GLOBAL DEFAULT +9 gd0
+.* TLS +GLOBAL DEFAULT +9 ie0
--- ld/testsuite/ld-powerpc/tlsso.r 17 Oct 2006 13:41:48 -0000 1.18
+++ ld/testsuite/ld-powerpc/tlsso.r 13 Feb 2007 01:53:03 -0000 1.19
@@ -17,8 +17,8 @@ Section Headers:
+\[ 6\] \.text .*
+\[ 7\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+\[ 8\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
- +\[ 9\] \.data\.rel\.ro .*
- +\[10\] \.dynamic .*
+ +\[ 9\] \.dynamic .*
+ +\[10\] \.branch_lt .*
+\[11\] \.got .*
+\[12\] \.plt .*
+\[13\] \.shstrtab .*
--- ld/testsuite/ld-powerpc/tlstocso.r 17 Oct 2006 13:41:48 -0000 1.18
+++ ld/testsuite/ld-powerpc/tlstocso.r 13 Feb 2007 01:53:03 -0000 1.19
@@ -17,8 +17,8 @@ Section Headers:
+\[ 6\] \.text .*
+\[ 7\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+\[ 8\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
- +\[ 9\] \.data\.rel\.ro .*
- +\[10\] \.dynamic .*
+ +\[ 9\] \.dynamic .*
+ +\[10\] \.branch_lt .*
+\[11\] \.got .*
+\[12\] \.plt .*
+\[13\] \.shstrtab .*
binutils-2.17.50.0.6-rh241252.patch:
elf.sc | 4 ++++
1 files changed, 4 insertions(+)
--- NEW FILE binutils-2.17.50.0.6-rh241252.patch ---
2007-05-03 Alan Modra <amodra at bigpond.net.au>
* scripttempl/elf.sc: Add .debug_pubtypes and .debug_ranges.
--- ld/scripttempl/elf.sc 26 Oct 2006 00:31:59 -0000 1.79
+++ ld/scripttempl/elf.sc 3 May 2007 07:06:13 -0000 1.80
@@ -505,6 +505,10 @@ cat <<EOF
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+
${TINY_DATA_SECTION}
${TINY_BSS_SECTION}
binutils-2.17.50.0.6-sse4.patch:
gas/config/tc-i386.c | 121 ++-
gas/config/tc-i386.h | 12
gas/doc/c-i386.texi | 1
gas/testsuite/gas/i386/crc32-intel.d | 25
gas/testsuite/gas/i386/crc32.d | 24
gas/testsuite/gas/i386/crc32.s | 24
gas/testsuite/gas/i386/i386.exp | 10
gas/testsuite/gas/i386/inval-crc32.l | 43 +
gas/testsuite/gas/i386/inval-crc32.s | 23
gas/testsuite/gas/i386/sse4_1.d | 102 ++
gas/testsuite/gas/i386/sse4_1.s | 99 ++
gas/testsuite/gas/i386/sse4_2.d | 36
gas/testsuite/gas/i386/sse4_2.s | 33
gas/testsuite/gas/i386/x86-64-crc32-intel.d | 35
gas/testsuite/gas/i386/x86-64-crc32.d | 34
gas/testsuite/gas/i386/x86-64-crc32.s | 34
gas/testsuite/gas/i386/x86-64-inval-crc32.l | 65 +
gas/testsuite/gas/i386/x86-64-inval-crc32.s | 34
gas/testsuite/gas/i386/x86-64-sse4_1.d | 110 ++
gas/testsuite/gas/i386/x86-64-sse4_1.s | 107 ++
gas/testsuite/gas/i386/x86-64-sse4_2.d | 45 +
gas/testsuite/gas/i386/x86-64-sse4_2.s | 42 +
include/opcode/i386.h | 71 +
opcodes/i386-dis.c | 1099 ++++++++++++++++++++++++----
24 files changed, 2055 insertions(+), 174 deletions(-)
--- NEW FILE binutils-2.17.50.0.6-sse4.patch ---
gas/
2007-05-03 H.J. Lu <hongjiu.lu at intel.com>
* config/tc-i386.c (match_template): Don't explicitly check
suffix for crc32 in Intel mode.
(process_suffix): Issue an error for crc32 if the operand size
is ambiguous.
2007-05-01 H.J. Lu <hongjiu.lu at intel.com>
* config/tc-i386.c (match_template): Check suffix for crc32 in
Intel mdoe.
(process_suffix): Default the suffix of 8bit crc32 to
BYTE_MNEM_SUFFIX.
(check_byte_reg): Skip check for 8bit crc32.
2007-04-18 H.J. Lu <hongjiu.lu at intel.com>
* doc/c-i386.texi; Document .ssse3, .sse4.1, .sse4.2 and .sse4.
2007-04-18 H.J. Lu <hongjiu.lu at intel.com>
* config/tc-i386.c (cpu_arch): Add .sse4.2 and .sse4.
(match_template): Handle operand size for crc32 in SSE4.2.
(process_suffix): Handle operand type for crc32 in SSE4.2.
(output_insn): Support SSE4.2.
2007-04-18 H.J. Lu <hongjiu.lu at intel.com>
* config/tc-i386.c (cpu_arch): Add .sse4.1.
(process_operands): Adjust implicit operand for blendvpd,
blendvps and pblendvb in SSE4.1.
(output_insn): Support SSE4.1.
gas/testsuite/
2007-05-03 H.J. Lu <hongjiu.lu at intel.com>
* gas/i386/crc32-intel.d: Updated.
* gas/i386/crc32.d: Likewise.
* gas/i386/sse4_2.d: Likewise.
* gas/i386/x86-64-crc32-intel.d: Likewise.
* gas/i386/x86-64-crc32.d: Likewise.
* gas/i386/x86-64-sse4_2.d: Likewise.
* gas/i386/crc32.s: Remove crc32 instructions with ambiguous
operand size and suffix in crc32 instructions in Intel mode.
* gas/i386/x86-64-crc32.s: Likewise.
* gas/i386/sse4_2.s: Remove crc32 instructions with ambiguous
operand size.
* gas/i386/x86-64-sse4_2.s: Likewise.
* gas/i386/i386.exp: Run inval-crc32 and x86-64-inval-crc32.
* gas/i386/inval-crc32.l: New.
* gas/i386/inval-crc32.s: Likewise.
* gas/i386/x86-64-inval-crc32.l: Likewise.
* gas/i386/x86-64-inval-crc32.s: Likewise.
2007-05-01 H.J. Lu <hongjiu.lu at intel.com>
* gas/i386/crc32-intel.d: New file.
* gas/i386/crc32.d:Likewise.
* gas/i386/crc32.s:Likewise.
* gas/i386/x86-64-crc32-intel.d:Likewise.
* gas/i386/x86-64-crc32.d:Likewise.
* gas/i386/x86-64-crc32.s:Likewise.
* gas/i386/i386.exp: Run crc32, crc32-intel, x86-64-crc32
and x86-64-crc32-intel.
2007-04-18 H.J. Lu <hongjiu.lu at intel.com>
* gas/i386/i386.exp: Add sse4.2 and x86-64-sse4.2.
* gas/i386/sse4_2.d: New file.
* gas/i386/sse4_2.s: Likewise.
* gas/i386/x86-64-sse4_2.d: Likewise.
* gas/i386/x86-64-sse4_2.s: Likewise.
2007-04-18 H.J. Lu <hongjiu.lu at intel.com>
* gas/i386/i386.exp: Add sse4.1 and x86-64-sse4.1.
* gas/i386/sse4_1.d: New file.
* gas/i386/sse4_1.s: Likewise.
* gas/i386/x86-64-sse4_1.d: Likewise.
* gas/i386/x86-64-sse4_1.s: Likewise.
opcodes/
2007-05-07 H.J. Lu <hongjiu.lu at intel.com>
* i386-dis.c (threebyte_0x38_uses_DATA_prefix): Correct entries
for SSE4.
(threebyte_0x3a_uses_DATA_prefix): Likewise.
2007-05-03 H.J. Lu <hongjiu.lu at intel.com>
* i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode.
* i386-opc.c (i386_optab): Remove IgnoreSize and correct operand
type for crc32.
2007-05-01 H.J. Lu <hongjiu.lu at intel.com>
* i386-dis.c (CRC32_Fixup): Properly handle Intel mode and
check data size prefix in 16bit mode.
* i386-opc.c (i386_optab): Default crc32 to non-8bit and
support Intel mode.
2007-04-18 H.J. Lu <hongjiu.lu at intel.com>
* i386-dis.c (CRC32_Fixup): New.
(PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90,
PREGRP91): New.
(threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2.
(threebyte_0x3a_uses_DATA_prefix): Likewise.
(prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87,
PREGRP88, PREGRP89, PREGRP90 and PREGRP91.
(three_byte_table): Likewise.
* i386-opc.c (i386_optab): Add SSE4.2 opcodes.
2006-11-09 H.J. Lu <hongjiu.lu at intel.com>
* i386-dis.c (print_insn): Check PREFIX_REPNZ before
PREFIX_DATA when prefix user table is used.
2006-11-09 H.J. Lu <hongjiu.lu at intel.com>
* i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ...
(twobyte_uses_DATA_prefix): This.
(twobyte_uses_REPNZ_prefix): New.
(twobyte_uses_REPZ_prefix): Likewise.
(threebyte_0x38_uses_DATA_prefix): Likewise.
(threebyte_0x38_uses_REPNZ_prefix): Likewise.
(threebyte_0x38_uses_REPZ_prefix): Likewise.
(threebyte_0x3a_uses_DATA_prefix): Likewise.
(threebyte_0x3a_uses_REPNZ_prefix): Likewise.
(threebyte_0x3a_uses_REPZ_prefix): Likewise.
(print_insn): Updated checking usages of DATA/REPNZ/REPZ
prefixes.
2007-04-18 H.J. Lu <hongjiu.lu at intel.com>
* i386-dis.c (XMM_Fixup): New.
(Edqb): New.
(Edqd): New.
(XMM0): New.
(dqb_mode): New.
(dqd_mode): New.
(PREGRP39 ... PREGRP85): New.
(threebyte_0x38_uses_DATA_prefix): Updated for SSE4.
(threebyte_0x3a_uses_DATA_prefix): Likewise.
(prefix_user_table): Add PREGRP39 ... PREGRP85.
(three_byte_table): Likewise.
(putop): Handle 'K'.
(intel_operand_size): Handle dqb_mode, dqd_mode):
(OP_E): Likewise.
(OP_G): Likewise.
* i386-opc.c (i386_optab): Add SSE4.1 opcodes.
* i386-opc.h (CpuSSE4_1): New.
(CpuUnknownFlags): Add CpuSSE4_1.
(regKludge): Update comment.
--- include/opcode/i386.h.jj 2007-05-07 10:48:24.000000000 +0200
+++ include/opcode/i386.h 2007-05-07 12:46:35.000000000 +0200
@@ -1197,6 +1197,10 @@ static const template i386_optab[] =
{"pavgw", 2, 0x660fe3, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX, Reg32|Reg64 } },
{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM, Reg32|Reg64 } },
+
+/* Streaming SIMD extensions 4.1 Instructions. */
+{"pextrw", 3, 0x660f3a15,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, Reg32|Reg64|ShortMem } },
+
{"pinsrw", 3, 0x0fc4, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
{"pinsrw", 3, 0x660fc4, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
{"pmaxsw", 2, 0x0fee, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
@@ -1410,6 +1414,71 @@ static const template i386_optab[] =
{"pabsd", 2, 0x0f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
{"pabsd", 2, 0x660f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+/* Streaming SIMD extensions 4.1 Instructions. */
+
+{"blendpd", 3, 0x660f3a0d,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"blendps", 3, 0x660f3a0c,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"blendvpd", 3, 0x660f3815,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"blendvps", 3, 0x660f3814,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"dppd", 3, 0x660f3a41,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"dpps", 3, 0x660f3a40,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"extractps",3, 0x660f3a17,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, Reg32|Reg64|LongMem } },
+{"insertps", 3, 0x660f3a21,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
+{"movntdqa", 2, 0x660f382a,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
+{"mpsadbw", 3, 0x660f3a42,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"packusdw", 2, 0x660f382b,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pblendvb", 3, 0x660f3810,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
[...2448 lines suppressed...]
+ sizes. The same applies to crc32 in SSE4.2. */
|| !((t->base_opcode == 0x0f01
&& t->extension_opcode == 0xc8)
+ || t->base_opcode == 0xf20f38f1
|| CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
operand_types[0],
overlap1, i.types[1],
@@ -2856,19 +2863,44 @@ process_suffix (void)
{
/* We take i.suffix from the last register operand specified,
Destination register type is more significant than source
- register type. */
- int op;
-
- for (op = i.operands; --op >= 0;)
- if ((i.types[op] & Reg)
- && !(i.tm.operand_types[op] & InOutPortReg))
- {
- i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
- (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
- (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
+ register type. crc32 in SSE4.2 prefers source register
+ type. */
+ if (i.tm.base_opcode == 0xf20f38f1)
+ {
+ if ((i.types[0] & Reg))
+ i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
LONG_MNEM_SUFFIX);
- break;
- }
+ }
+ else if (i.tm.base_opcode == 0xf20f38f0)
+ {
+ if ((i.types[0] & Reg8))
+ i.suffix = BYTE_MNEM_SUFFIX;
+ }
+
+ if (!i.suffix)
+ {
+ int op;
+
+ if (i.tm.base_opcode == 0xf20f38f1
+ || i.tm.base_opcode == 0xf20f38f0)
+ {
+ /* We have to know the operand size for crc32. */
+ as_bad (_("ambiguous memory operand size for `%s`"),
+ i.tm.name);
+ return 0;
+ }
+
+ for (op = i.operands; --op >= 0;)
+ if ((i.types[op] & Reg)
+ && !(i.tm.operand_types[op] & InOutPortReg))
+ {
+ i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
+ (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
+ (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
+ LONG_MNEM_SUFFIX);
+ break;
+ }
+ }
}
else if (i.suffix == BYTE_MNEM_SUFFIX)
{
@@ -3047,6 +3079,10 @@ check_byte_reg (void)
|| i.tm.base_opcode == 0xfbf))
continue;
+ /* crc32 doesn't generate this warning. */
+ if (i.tm.base_opcode == 0xf20f38f0)
+ continue;
+
if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
{
/* Prohibit these changes in the 64bit mode, since the
@@ -3302,12 +3338,45 @@ process_operands ()
is converted into xor %reg, %reg. */
if (i.tm.opcode_modifier & regKludge)
{
- unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
- /* Pretend we saw the extra register operand. */
- assert (i.op[first_reg_op + 1].regs == 0);
- i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
- i.types[first_reg_op + 1] = i.types[first_reg_op];
- i.reg_operands = 2;
+ if ((i.tm.cpu_flags & CpuSSE4_1))
+ {
+ /* The first operand in instruction blendvpd, blendvps and
+ pblendvb in SSE4.1 is implicit and must be xmm0. */
+ assert (i.operands == 3
+ && i.reg_operands >= 2
+ && i.types[0] == RegXMM);
+ if (i.op[0].regs->reg_num != 0)
+ {
+ if (intel_syntax)
+ as_bad (_("the last operand of `%s' must be `xmm0'"),
+ i.tm.name);
+ else
+ as_bad (_("the first operand of `%s' must be `%%xmm0'"),
+ i.tm.name);
+ return 0;
+ }
+ i.op[0] = i.op[1];
+ i.op[1] = i.op[2];
+ i.types[0] = i.types[1];
+ i.types[1] = i.types[2];
+ i.operands--;
+ i.reg_operands--;
+
+ /* We need to adjust fields in i.tm since they are used by
+ build_modrm_byte. */
+ i.tm.operand_types [0] = i.tm.operand_types [1];
+ i.tm.operand_types [1] = i.tm.operand_types [2];
+ i.tm.operands--;
+ }
+ else
+ {
+ unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
+ /* Pretend we saw the extra register operand. */
+ assert (i.op[first_reg_op + 1].regs == 0);
+ i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
+ i.types[first_reg_op + 1] = i.types[first_reg_op];
+ i.reg_operands = 2;
+ }
}
if (i.tm.opcode_modifier & ShortForm)
@@ -3891,11 +3960,12 @@ output_insn ()
unsigned char *q;
unsigned int prefix;
- /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
- Streaming SIMD extensions 3 Instructions have 3 bytes. We may
- use one more higher byte to specify a prefix the instruction
- requires. */
- if ((i.tm.cpu_flags & CpuSSSE3) != 0)
+ /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
+ SSE4 instructions have 3 bytes. We may use one more higher
+ byte to specify a prefix the instruction requires. Exclude
+ instructions which are in both SSE4 and ABM. */
+ if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
+ && (i.tm.cpu_flags & CpuABM) == 0)
{
if (i.tm.base_opcode & 0xff000000)
{
@@ -3936,7 +4006,8 @@ output_insn ()
}
else
{
- if ((i.tm.cpu_flags & CpuSSSE3) != 0)
+ if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
+ && (i.tm.cpu_flags & CpuABM) == 0)
{
p = frag_more (3);
*p++ = (i.tm.base_opcode >> 16) & 0xff;
--- gas/config/tc-i386.h.jj 2006-10-20 20:50:59.000000000 +0200
+++ gas/config/tc-i386.h 2007-05-07 12:27:46.000000000 +0200
@@ -190,6 +190,11 @@ typedef struct
#define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */
#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */
#define CpuABM 0x200000 /* ABM New Instructions required */
+#define CpuSSE4_1 0x400000 /* SSE4.1 Instructions required */
+#define CpuSSE4_2 0x800000 /* SSE4.2 Instructions required */
+
+/* SSE4.1/4.2 Instructions required */
+#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
/* These flags are set by gas depending on the flag_code. */
#define Cpu64 0x4000000 /* 64bit support required */
@@ -198,7 +203,8 @@ typedef struct
/* The default value for unknown CPUs - enable all features to avoid problems. */
#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
- |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a)
+ |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
+ |CpuSSE4_2|CpuABM|CpuSSE4a)
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
@@ -234,7 +240,9 @@ typedef struct
#define No_xSuf 0x800000 /* x suffix on instruction illegal */
#define FWait 0x1000000 /* instruction needs FWAIT */
#define IsString 0x2000000 /* quick test for string instructions */
-#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
+#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul
+ and special register processing for
+ some instructions. */
#define IsPrefix 0x8000000 /* opcode is a prefix */
#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
--- gas/doc/c-i386.texi.jj 2007-05-07 10:48:24.000000000 +0200
+++ gas/doc/c-i386.texi 2007-05-07 11:15:33.000000000 +0200
@@ -756,6 +756,7 @@ supported on the CPU specified. The cho
@item @samp{amdfam10}
@item @samp{k6} @tab @samp{athlon} @tab @samp{sledgehammer} @tab @samp{k8}
@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
+ at item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
@item @samp{.sse4a} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.padlock}
@item @samp{.pacifica} @tab @samp{.svme} @tab @samp{.abm}
@end multitable
Index: binutils.spec
===================================================================
RCS file: /cvs/dist/rpms/binutils/FC-6/binutils.spec,v
retrieving revision 1.105
retrieving revision 1.106
diff -u -r1.105 -r1.106
--- binutils.spec 19 Jan 2007 15:26:44 -0000 1.105
+++ binutils.spec 27 Jun 2007 18:52:49 -0000 1.106
@@ -1,7 +1,7 @@
Summary: A GNU collection of binary utilities.
Name: binutils
Version: 2.17.50.0.6
-Release: 3%{?dist}
+Release: 5%{?dist}
License: GPL
Group: Development/Tools
URL: http://sources.redhat.com/binutils
@@ -20,6 +20,12 @@
Patch12: binutils-2.17.50.0.6-popcnt.patch
Patch13: binutils-2.17.50.0.6-rh223181.patch
Patch14: binutils-2.17.50.0.6-tekhex.patch
+Patch15: binutils-2.17.50.0.6-bz4267.patch
+Patch16: binutils-2.17.50.0.6-ppc-relbrlt-test.patch
+Patch17: binutils-2.17.50.0.6-rh235221.patch
+Patch18: binutils-2.17.50.0.6-sse4.patch
+Patch19: binutils-2.17.50.0.6-ppc64-version-script.patch
+Patch20: binutils-2.17.50.0.6-rh241252.patch
Buildroot: %{_tmppath}/binutils-root
BuildRequires: texinfo >= 4.0, dejagnu, gettext, flex, bison
@@ -75,6 +81,12 @@
%patch12 -p0 -b .popcnt~
%patch13 -p0 -b .rh223181~
%patch14 -p0 -b .tekhex~
+%patch15 -p0 -b .bz4267~
+%patch16 -p0 -b .ppc-relbrlt-test~
+%patch17 -p0 -b .rh235221~
+%patch18 -p0 -b .sse4~
+%patch19 -p0 -b .ppc64-version-script~
+%patch20 -p0 -b .rh241252~
# On ppc64 we might use 64K pages
sed -i -e '/#define.*ELF_COMMONPAGESIZE/s/0x1000$/0x10000/' bfd/elf*ppc.c
@@ -94,7 +106,7 @@
%ifarch ia64
CARGS=--enable-targets=i386-linux
%endif
-CC="gcc -L`pwd`/bfd/.libs/" CFLAGS="${CFLAGS:-%optflags}" ../configure \
+CC="gcc -L`pwd`/bfd/.libs/" CFLAGS="${CFLAGS:-%optflags} -D_FILE_OFFSET_BITS=64" ../configure \
%{_target_platform} --prefix=%{_prefix} --exec-prefix=%{_exec_prefix} \
--bindir=%{_bindir} --sbindir=%{_sbindir} --sysconfdir=%{_sysconfdir} \
--datadir=%{_datadir} --includedir=%{_includedir} --libdir=%{_libdir} \
@@ -119,7 +131,7 @@
# Rebuild libiberty.a with -fPIC
make -C libiberty clean
-make CFLAGS="-g -fPIC $RPM_OPT_FLAGS" -C libiberty
+make CFLAGS="-g -fPIC $RPM_OPT_FLAGS -D_FILE_OFFSET_BITS=64" -C libiberty
install -m 644 libiberty/libiberty.a %{buildroot}%{_prefix}/%{_lib}
install -m 644 ../include/libiberty.h %{buildroot}%{_prefix}/include
@@ -217,6 +229,15 @@
%{_infodir}/bfd*info*
%changelog
+* Fri Jun 27 2007 Jakub Jelinek <jakub at redhat.com> 2.17.50.0.6-5.fc6
+- fix ld --unique with new DWARF3 sections .debug_ranges and .debug_pubtypes
+ (Alan Modra, #241252)
+- fix segfault in ppc64 version script handling (Andreas Schwab)
+- SSE4 support in gas and objdump (H.J.Lu, #223120)
+- compile binutils with -D_FILE_OFFSET_BITS=64 (#215514)
+- fix ld --emit-relocs on ppc64 (Alan Modra, #235221)
+- fix ppc32 ld segfault with -msecure-plt (Alan Modra, BZ#4267)
+
* Fri Jan 19 2007 Jakub Jelinek <jakub at redhat.com> 2.17.50.0.6-3.fc6
- 10x linking speedup on large C++ apps (#223181)
- fix tekhex reader
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