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Feature: Fedora Electronic Lab



Hello there,

Since F7 development cycle I've been introducing new opensource tools
for electronic engineering. However I did not have time to make it a
feature for Moonshine at that time.

A few months later, I've been focusing primarily on the VLSI field and
tried to ensure that one _can_ complete a design flow. If we don't
have a complete design flow, there's no use for a user to use bits of
it as it will cost him/her time and money.

VLSI stands for : Very Large Scale Integration, about 10⁶ to 10⁷
transistors per chip
So as you might have guess, these simulators should be mature and they
are. Magic and alliance are around for more than 10 years.

Now with Alliance VLSI cad, ngspice, magic and irsim, one can create
and simulates his/her own chip on Fedora and asks a particular foundry
to create it in real life.

Those tools are used worldwide by more than 250 universities. Surely
these VLSI tools are not for my mother, nor my neighbour but targeted
for VLSI/ASIC students and hobbyists for educational purposes.

Like I said in my blog
http://clunixchit.blogspot.com/2007/08/eda-physical-layout-is-done-so-whats.html
, real VLSI professional would use commercial tools that are far more
expensive (more than 10 times of Vista, just to give you a number) and
far more precise than Alliance, magic and friends. But at least they
are opensource and will help students designing their own layouts or
schematics.

Those major commercial tools are built on RHEL and shipped the
binaries on the cd (you can see glibc compiled under RHELx in those
cds). So whatever educational institutions are using those commercial
tools are either using RHEL or its clone. (I've never seen vendors
shipping binaries built under a debian based distro). Take for
example, at my university those nodes are under scientific linux
because of that. The current situation is that students can't afford
to have commercial tools at home and they are mostly windows users.
Now that fedora is shipping those VLSI CADs it's an open door for
these people to try linux and use opensource. Eventually, perhaps
helping in the development of those VLSI cads. Also, one can easily
deploy a VLSI simulation kit of fedora at home (thanks to yum).

Enough blabla on my part, but it is important to get the picture.

So here is the Feature Proposal of
http://fedoraproject.org/wiki/Features/FedoraElectronicLab

For now, I'm calling it Fedora Electronic Lab. I was also thinking
about Fedora Simulation Kit.
However since for now what I explained, it is only about :
# Analog/Digital Simulation
# Spice Simulation
# Hardware Development (VHDL,Verilog)
# VLSI (layout, synthesis, Finite State Machines...)
there are other tools that fedora provides to create a non-VLSI
platform, but still in the Electronic field.
Example: PIC Programming,
Fedora ships ktechlab, piklab, sdcc those could be under "PIC
Programming" secton.
There are more examples like this. Hence by giving it a generic name,
I'm hoping that other fedora maintainers packaging electronic
simulators could join in.
I understand that the use of "Fedora" in the "Fedora Electronic Lab"
might be questioned. We will see to that if one objects.

I hope to complete the wiki page by this Thursday so that FESCo could
review it. This email is to familarise everyone about this little but
important feature for education, so that they can comment and suggest
ideas on how to proceed.

Most of the work done was to ensure Interoperability between
opensource simulators.
Example:
>From a hardware description of a Mealy/Moore machine, one can now
create its layout:
Hardware description -> checking vhdl syntax -> optimising ->
schematic -> layout -> adding technology (e.g 0.25µm) -> Real layout
-> chip fabrication.


More information and screenshots can be found on my blog:
http://clunixchit.blogspot.com/2007/07/from-vhdl-description-to-layout.html
http://clunixchit.blogspot.com/2007/08/eda-addon-gds2pov-being-shipped-by.html
http://clunixchit.blogspot.com/2007/08/eda-physical-layout-is-done-so-whats.html
http://clunixchit.blogspot.com/2007/08/eda-physical-layout-is-done-so-whats_09.html

Also, one opensource tools that I really miss is "netgen" for LVS
checks (Layout Versus Schematic". There is segmentation fault on
runtime. So if you are C guru, please do help to figure out why it
crashes:
http://clunixchit.blogspot.com/2007/08/loss-there-is-no-opensource-lvs-netlist.html

regards,
Chitlesh
-- 
http://clunixchit.blogspot.com


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