rpms/xorg-x11-drv-ati/devel radeon-git-upstream-fixes2.patch, 1.3, 1.4 xorg-x11-drv-ati.spec, 1.90, 1.91
Dave Airlie (airlied)
fedora-extras-commits at redhat.com
Sun Apr 6 07:15:04 UTC 2008
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Author: airlied
Update of /cvs/pkgs/rpms/xorg-x11-drv-ati/devel
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv2124
Modified Files:
radeon-git-upstream-fixes2.patch xorg-x11-drv-ati.spec
Log Message:
* Sun Apr 06 2008 Dave Airlie <airlied at redhat.com> 6.8.0-10
- attempt to fix VT switch and X restart hangs
radeon-git-upstream-fixes2.patch:
Index: radeon-git-upstream-fixes2.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon-git-upstream-fixes2.patch,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -r1.3 -r1.4
--- radeon-git-upstream-fixes2.patch 2 Apr 2008 00:07:55 -0000 1.3
+++ radeon-git-upstream-fixes2.patch 6 Apr 2008 07:14:38 -0000 1.4
@@ -1,3 +1,72 @@
+commit bc0407e53237d7968808110bc0243076377acf6e
+Author: Alex Deucher <alex at cube.(none)>
+Date: Fri Apr 4 18:40:16 2008 -0400
+
+ ATOMBIOS: Add support for DynamicClocks option
+
+ This patch adds support for dynamic clock gating and static
+ power management using the atom command tables. In some cases
+ the bios may already set this up during post, so YMMV.
+
+ I was only able to test on desktop cards, so I haven't tested
+ to see how much (if any) power this saves or how it affects the
+ thermal footprint.
+
+commit 5f5e21bb50555c56bd371576074c28c929307ff1
+Author: Alex Deucher <alex at cube.(none)>
+Date: Fri Apr 4 14:29:45 2008 -0400
+
+ RADEON: warning fixes
+
+commit c8e9a973aaded24aad567a0e36d0c78a05d6b2fd
+Author: Alex Deucher <alex at cube.(none)>
+Date: Fri Apr 4 14:26:19 2008 -0400
+
+ RADEON: add some quirks
+
+commit 091963a635b79884afe77c026eabb48972fbe175
+Author: Alex Deucher <alex at botch2.com>
+Date: Thu Apr 3 22:35:16 2008 -0400
+
+ Minor cleanup
+
+commit 950e9860643c20acde0eca4e4ff26baacc1f2b69
+Author: Alex Deucher <alex at botch2.com>
+Date: Thu Apr 3 22:11:48 2008 -0400
+
+ Revert "RADEON: memmap rework 1"
+
+ This reverts commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94.
+
+ Conflicts:
+
+ src/radeon.h
+ src/radeon_driver.c
+
+ This rework seems to have caused more trouble than it was worth.
+
+commit 88a1fe4a94c5d11aff22734b21c89890e4428cd5
+Author: Alex Deucher <alex at botch2.com>
+Date: Thu Apr 3 22:04:43 2008 -0400
+
+ Revert "RADEON: remove driver rec copies of mc info, use save rec directly"
+
+ This reverts commit be0858a84fbdf74c0b844f462933a221d48c707d.
+
+ Conflicts:
+
+ src/radeon_driver.c
+
+commit c40a7aa3989576a8144213e2f31b892d21df8686
+Author: Owen W. Taylor <otaylor at fishsoup.net>
+Date: Thu Apr 3 14:43:55 2008 -0400
+
+ R3xx/R5xx: Fix pitch and clamp mode for repeating textures
+
+ - We can always use TXPITCH on a R300 even when repeating,
+ (previous check for pitch matching width was also wrong)
+ - Fix clamp mode for repeating textures to be WRAP
+
commit a8593482c1f2e0f2dbac06c2e5325ba8c83ed9ff
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Apr 2 09:58:05 2008 +1000
@@ -871,6 +940,14 @@
R300+: update RADEONCP_REFRESH() to reflect new location of scissor regs
+commit b865faf95666e2172c3eec143f77fe9c524e4983
+Author: Alex Deucher <alex at samba.(none)>
+Date: Wed Feb 27 14:05:44 2008 -0500
+
+ R100/R200: move r100/r200 specific 3D setup into appropriate blocks
+
+ R3xx+ doesn't have these regs.
+
commit 3de2dc88cf26ff5932f11cecdf975777b8aa2a4a
Author: Adam Jackson <ajax at redhat.com>
Date: Wed Jan 16 14:55:05 2008 -0500
@@ -1031,7 +1108,7 @@
static XF86ModuleVersionInfo ATIVersionRec =
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
-index bc2df18..08f8386 100644
+index bc2df18..51981a7 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -1,10 +1,5 @@
@@ -1292,13 +1369,9 @@
}
for (i = 0; i < xf86_config->num_output; i++) {
-@@ -330,31 +403,26 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
- ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay,
- adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
+@@ -334,27 +407,25 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
-- RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
-- RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
--
if (IS_AVIVO_VARIANT) {
- radeon_crtc->fb_width = mode->CrtcHDisplay;
- radeon_crtc->fb_height = pScrn->virtualY;
@@ -1330,7 +1403,7 @@
}
if (radeon_crtc->crtc_id == 0)
-@@ -376,17 +444,14 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
+@@ -376,17 +447,14 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
@@ -1353,7 +1426,7 @@
OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
crtc->scrn->displayWidth);
OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
-@@ -398,7 +463,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
+@@ -398,7 +466,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK);
OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
@@ -1362,7 +1435,7 @@
OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
(mode->HDisplay << 16) | mode->VDisplay);
-@@ -411,7 +476,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
+@@ -411,7 +479,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
@@ -1913,7 +1986,7 @@
data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
data.exec.dataSpace = (void *)&space;
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
-index 06ad60c..12d1b9b 100644
+index 06ad60c..5ef86ce 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -78,6 +78,13 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
@@ -2084,30 +2157,9 @@
}
for (i = 0; i < xf86_config->num_output; i++) {
-@@ -1693,8 +1724,6 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
- }
-
-
-- ErrorF("init memmap\n");
-- RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
- ErrorF("init common\n");
- RADEONInitCommonRegisters(info->ModeReg, info);
-
-@@ -1748,8 +1777,6 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
- }
- }
-
-- ErrorF("restore memmap\n");
-- RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
- ErrorF("restore common\n");
- RADEONRestoreCommonRegisters(pScrn, info->ModeReg);
-
-@@ -1773,9 +1800,9 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
- radeon_update_tv_routing(pScrn, info->ModeReg);
-
+@@ -1775,7 +1806,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
if (info->DispPriority)
-- RADEONInitDispBandwidth(pScrn);
-+ RADEONInitDispBandwidth(pScrn);
+ RADEONInitDispBandwidth(pScrn);
- if (info->tilingEnabled != tilingOld) {
+ if (tilingChanged) {
@@ -2370,7 +2422,7 @@
+"0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
+"0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics"
diff --git a/src/radeon.h b/src/radeon.h
-index aba3c0f..f3db451 100644
+index aba3c0f..ef62883 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -167,7 +167,8 @@ typedef enum {
@@ -2435,17 +2487,7 @@
/*
* Errata workarounds
*/
-@@ -355,9 +379,6 @@ typedef struct {
- unsigned long BIOSAddr; /* BIOS physical address */
- CARD32 fbLocation;
- CARD32 gartLocation;
-- CARD32 mc_fb_location;
-- CARD32 mc_agp_location;
-- CARD32 mc_agp_location_hi;
-
- void *MMIO; /* Map of MMIO region */
- void *FB; /* Map of frame buffer */
-@@ -745,152 +766,204 @@ do { \
+@@ -745,152 +769,208 @@ do { \
info->fifo_slots -= entries; \
} while (0)
@@ -2699,6 +2741,10 @@
+extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info);
+extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
+extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
++extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
++ RADEONInfoPtr info);
++extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
++ RADEONSavePtr restore);
-extern void RADEONSetPitch (ScrnInfoPtr pScrn);
-extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode);
@@ -2784,7 +2830,7 @@
extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
DisplayModePtr mode, xf86OutputPtr output);
extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
-@@ -901,47 +974,18 @@ extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save
+@@ -901,47 +981,18 @@ extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save
DisplayModePtr mode, xf86OutputPtr output);
extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
DisplayModePtr mode, BOOL IsPrimary);
@@ -2840,7 +2886,7 @@
#define RADEONCP_START(pScrn, info) \
do { \
-@@ -998,11 +1042,18 @@ do { \
+@@ -998,11 +1049,18 @@ do { \
info->needCacheFlush = FALSE; \
} \
RADEON_WAIT_UNTIL_IDLE(); \
@@ -2908,10 +2954,87 @@
a->SetupForCPUToScreenTexture2 =
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
-index 88c220b..85a2e71 100644
+index 88c220b..224aae3 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
-@@ -1399,7 +1399,7 @@ const int object_connector_convert[] =
+@@ -35,6 +35,8 @@
+ #include "radeon_probe.h"
+ #include "radeon_macros.h"
+
++#include "ati_pciids_gen.h"
++
+ #include "xorg-server.h"
+
+ /* only for testing now */
+@@ -517,25 +519,52 @@ rhdAtomASICInit(atomBiosHandlePtr handle)
+ return FALSE;
+ }
+
+-Bool
+-rhdAtomSetScaler(atomBiosHandlePtr handle, unsigned char scalerID, int setting)
++int
++atombios_dyn_clk_setup(ScrnInfoPtr pScrn, int enable)
+ {
+- ENABLE_SCALER_PARAMETERS scaler;
++ RADEONInfoPtr info = RADEONPTR(pScrn);
++ DYNAMIC_CLOCK_GATING_PS_ALLOCATION dynclk_data;
+ AtomBiosArgRec data;
++ unsigned char *space;
+
+- scaler.ucScaler = scalerID;
+- scaler.ucEnable = setting;
+- data.exec.dataSpace = NULL;
+- data.exec.index = 0x21;
+- data.exec.pspace = &scaler;
+- xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling EnableScaler\n");
+- if (RHDAtomBiosFunc(handle->scrnIndex, handle,
+- ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+- xf86DrvMsg(handle->scrnIndex, X_INFO, "EnableScaler Successful\n");
+- return TRUE;
++ dynclk_data.ucEnable = enable;
++
++ data.exec.index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
++ data.exec.dataSpace = (void *)&space;
++ data.exec.pspace = &dynclk_data;
++
++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
++ ErrorF("Dynamic clock gating %s success\n", enable? "enable" : "disable");
++ return ATOM_SUCCESS;
+ }
+- xf86DrvMsg(handle->scrnIndex, X_INFO, "EableScaler Failed\n");
+- return FALSE;
++
++ ErrorF("Dynamic clock gating %s failure\n", enable? "enable" : "disable");
++ return ATOM_NOT_IMPLEMENTED;
++
++}
++
++int
++atombios_static_pwrmgt_setup(ScrnInfoPtr pScrn, int enable)
++{
++ RADEONInfoPtr info = RADEONPTR(pScrn);
++ ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION pwrmgt_data;
++ AtomBiosArgRec data;
++ unsigned char *space;
++
++ pwrmgt_data.ucEnable = enable;
++
++ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
++ data.exec.dataSpace = (void *)&space;
++ data.exec.pspace = &pwrmgt_data;
++
++ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
++ ErrorF("Static power management %s success\n", enable? "enable" : "disable");
++ return ATOM_SUCCESS;
++ }
++
++ ErrorF("Static power management %s failure\n", enable? "enable" : "disable");
++ return ATOM_NOT_IMPLEMENTED;
++
+ }
+
+ # endif
+@@ -1399,7 +1428,7 @@ const int object_connector_convert[] =
CONNECTOR_NONE,
CONNECTOR_NONE,
CONNECTOR_NONE,
@@ -2920,7 +3043,7 @@
};
static void
-@@ -1499,6 +1499,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
+@@ -1499,6 +1528,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
unsigned short size;
atomDataTablesPtr atomDataPtr;
ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
@@ -2928,7 +3051,7 @@
int i, j, ddc_line = 0;
atomDataPtr = info->atomBIOS->atomDataPtr;
-@@ -1507,7 +1508,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
+@@ -1507,7 +1537,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
if (crev < 2)
return FALSE;
@@ -2937,7 +3060,7 @@
con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
((char *)&atomDataPtr->Object_Header->sHeader +
atomDataPtr->Object_Header->usConnectorObjectTableOffset);
-@@ -1527,10 +1528,34 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
+@@ -1527,10 +1557,34 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
((char *)&atomDataPtr->Object_Header->sHeader
+ con_obj->asObjects[i].usSrcDstTableOffset);
@@ -2975,7 +3098,7 @@
info->BiosConnector[i].devices = 0;
for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) {
-@@ -1538,7 +1563,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
+@@ -1538,7 +1592,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
sobj_id = (SrcDstTable->usSrcObjectID[j] & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
ErrorF("src object id %04x %d\n", SrcDstTable->usSrcObjectID[j], sobj_id);
@@ -2984,7 +3107,7 @@
switch(sobj_id) {
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_LCD1_INDEX);
-@@ -1548,6 +1573,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
+@@ -1548,6 +1602,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP1_INDEX);
info->BiosConnector[i].TMDSType = TMDS_INT;
break;
@@ -2998,7 +3121,7 @@
case ENCODER_OBJECT_ID_INTERNAL_TMDS2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX);
-@@ -1560,7 +1592,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
+@@ -1560,7 +1621,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
@@ -3013,7 +3136,7 @@
info->BiosConnector[i].DACType = DAC_PRIMARY;
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
-@@ -1568,7 +1606,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
+@@ -1568,7 +1635,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
if (info->BiosConnector[i].ConnectorType == CONNECTOR_DIN ||
info->BiosConnector[i].ConnectorType == CONNECTOR_STV ||
info->BiosConnector[i].ConnectorType == CONNECTOR_CTV)
@@ -3023,7 +3146,7 @@
else
info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT2_INDEX);
info->BiosConnector[i].DACType = DAC_TVDAC;
-@@ -1588,7 +1627,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
+@@ -1588,7 +1656,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
ErrorF("record type %d\n", Record->ucRecordType);
switch (Record->ucRecordType) {
case ATOM_I2C_RECORD_TYPE:
@@ -3032,7 +3155,30 @@
(ATOM_I2C_RECORD *)Record,
&ddc_line);
info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line);
-@@ -1745,12 +1784,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
+@@ -1708,6 +1776,22 @@ RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_
+ return TRUE;
+ }
+
++static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index)
++{
++ RADEONInfoPtr info = RADEONPTR (pScrn);
++
++ /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
++ if ((info->Chipset == PCI_CHIP_RS690_791E) &&
++ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1043) &&
++ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x826d)) {
++ if ((info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) &&
++ (info->BiosConnector[index].TMDSType == TMDS_LVTMA)) {
++ info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D;
++ }
++ }
++
++}
++
+ Bool
+ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
+ {
+@@ -1745,12 +1829,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
info->BiosConnector[i].valid = TRUE;
info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
@@ -3046,7 +3192,7 @@
info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType;
info->BiosConnector[i].DACType = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
-@@ -1759,14 +1793,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
+@@ -1759,14 +1838,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
(i == ATOM_DEVICE_TV2_INDEX) ||
(i == ATOM_DEVICE_CV_INDEX))
info->BiosConnector[i].ddc_i2c.valid = FALSE;
@@ -3067,7 +3213,7 @@
} else
info->BiosConnector[i].ddc_i2c =
RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
-@@ -1774,16 +1809,14 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
+@@ -1774,16 +1854,14 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
if (i == ATOM_DEVICE_DFP1_INDEX)
info->BiosConnector[i].TMDSType = TMDS_INT;
else if (i == ATOM_DEVICE_DFP2_INDEX) {
@@ -3090,7 +3236,17 @@
info->BiosConnector[i].TMDSType = TMDS_NONE;
/* Always set the connector type to VGA for CRT1/CRT2. if they are
-@@ -1859,689 +1892,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
+@@ -1816,6 +1894,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
+ } else {
+ info->BiosConnector[i].hpd_mask = 0;
+ }
++
++ RADEONApplyATOMQuirks(pScrn, i);
++
+ }
+
+ /* CRTs/DFPs may share a port */
+@@ -1859,689 +1940,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
return TRUE;
}
@@ -3780,6 +3936,23 @@
# ifdef ATOM_BIOS_PARSER
static AtomBiosResult
rhdAtomExec (atomBiosHandlePtr handle,
+diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h
+index 9cb279e..955f2e4 100644
+--- a/src/radeon_atombios.h
++++ b/src/radeon_atombios.h
+@@ -116,6 +116,12 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn);
+ extern Bool
+ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn);
+
++extern int
++atombios_dyn_clk_setup(ScrnInfoPtr pScrn, int enable);
++
++extern int
++atombios_static_pwrmgt_setup(ScrnInfoPtr pScrn, int enable);
++
+ extern Bool
+ RADEONGetATOMTVInfo(xf86OutputPtr output);
+
diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c
index 259366c..3e7ae01 100644
--- a/src/radeon_atomwrapper.c
@@ -3794,7 +3967,7 @@
#define INT32 INT32
#include "CD_Common_Types.h"
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
-index 8e6bd8d..f97ed2f 100644
+index 8e6bd8d..6be3528 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -75,7 +75,8 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
@@ -3807,7 +3980,7 @@
#else
info->VBIOS = xalloc(RADEON_VBIOS_SIZE);
#endif
-@@ -216,6 +217,44 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
+@@ -216,6 +217,54 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
return FALSE;
}
@@ -3847,12 +4020,22 @@
+ info->BiosConnector[index].valid = FALSE;
+ }
+ }
++
++ /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
++ if (info->Chipset == PCI_CHIP_RV100_QY &&
++ PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1002 &&
++ PCI_SUB_DEVICE_ID(info->PciInfo) == 0x013a) {
++ if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) {
++ info->BiosConnector[index].ConnectorType = CONNECTOR_VGA;
++ }
++ }
++
+}
+
static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
-@@ -297,28 +336,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
+@@ -297,28 +346,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
else
info->BiosConnector[i].TMDSType = TMDS_INT;
@@ -3882,7 +4065,7 @@
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n");
-@@ -620,6 +639,9 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
+@@ -620,6 +649,9 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
if (!info->VBIOS) return FALSE;
@@ -3892,7 +4075,7 @@
if (info->IsAtomBios) {
/* not implemented yet */
return FALSE;
-@@ -628,7 +650,21 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
+@@ -628,7 +660,21 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32);
if (offset) {
rev = RADEON_BIOS8(offset + 0x3);
@@ -3915,7 +4098,7 @@
bg = RADEON_BIOS8(offset + 0xc) & 0xf;
dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf;
radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20);
-@@ -656,6 +692,14 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
+@@ -656,6 +702,14 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output)
radeon_output->ntsc_tvdac_adj = radeon_output->ps2_tvdac_adj;
return TRUE;
@@ -4052,7 +4235,7 @@
{ -1, NULL }
};
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
-index 4469cd8..5c9eae1 100644
+index 0250aef..5c9eae1 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -60,7 +60,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
@@ -4133,6 +4316,60 @@
} else {
OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
(0 << R300_CLIP_Y_SHIFT)));
+@@ -239,6 +249,19 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
+ OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
+ R200_VAP_VF_MAX_VTX_NUM);
+ FINISH_ACCEL();
++
++ BEGIN_ACCEL(5);
++ OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
++ OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
++ OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
++ OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
++ OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
++ RADEON_BFACE_SOLID |
++ RADEON_FFACE_SOLID |
++ RADEON_VTX_PIX_CENTER_OGL |
++ RADEON_ROUND_MODE_ROUND |
++ RADEON_ROUND_PREC_4TH_PIX));
++ FINISH_ACCEL();
+ } else {
+ BEGIN_ACCEL(2);
+ if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
+@@ -252,20 +275,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
+ RADEON_VTX_ST1_NONPARAMETRIC |
+ RADEON_TEX1_W_ROUTING_USE_W0);
+ FINISH_ACCEL();
++
++ BEGIN_ACCEL(5);
++ OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
++ OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
++ OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
++ OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
++ OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
++ RADEON_BFACE_SOLID |
++ RADEON_FFACE_SOLID |
++ RADEON_VTX_PIX_CENTER_OGL |
++ RADEON_ROUND_MODE_ROUND |
++ RADEON_ROUND_PREC_4TH_PIX));
++ FINISH_ACCEL();
+ }
+
+- BEGIN_ACCEL(5);
+- OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
+- OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
+- OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
+- OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
+- OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
+- RADEON_BFACE_SOLID |
+- RADEON_FFACE_SOLID |
+- RADEON_VTX_PIX_CENTER_OGL |
+- RADEON_ROUND_MODE_ROUND |
+- RADEON_ROUND_PREC_4TH_PIX));
+- FINISH_ACCEL();
+ }
+
+
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 3524b75..e2d31eb 100644
--- a/src/radeon_crtc.c
@@ -4284,14 +4521,13 @@
HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
HARDWARE_CURSOR_ARGB));
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
-index 5cf8d51..0183aa3 100644
+index 5cf8d51..d5595ea 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
-@@ -125,35 +125,8 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
- #ifdef XF86DRI
+@@ -126,35 +126,6 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
#endif
--
+
-extern DisplayModePtr
-RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode);
-
@@ -4320,12 +4556,11 @@
-extern Bool
-RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen);
-#endif /* USE_XAA */
-+static void
-+RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
-
+-
static const OptionInfoRec RADEONOptions[] = {
{ OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
-@@ -219,18 +192,17 @@ static const OptionInfoRec RADEONOptions[] = {
+ { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE },
+@@ -219,18 +190,17 @@ static const OptionInfoRec RADEONOptions[] = {
{ OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE },
{ OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE },
@@ -4348,7 +4583,7 @@
}
struct RADEONInt10Save {
-@@ -439,6 +411,9 @@ static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn)
+@@ -439,6 +409,9 @@ static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn)
/* Memory map the frame buffer. Used by RADEONMapMem, below. */
static Bool RADEONMapFB(ScrnInfoPtr pScrn)
{
@@ -4358,7 +4593,7 @@
RADEONInfoPtr info = RADEONPTR(pScrn);
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-@@ -456,7 +431,7 @@ static Bool RADEONMapFB(ScrnInfoPtr pScrn)
+@@ -456,7 +429,7 @@ static Bool RADEONMapFB(ScrnInfoPtr pScrn)
#else
@@ -4367,7 +4602,7 @@
info->LinearAddr,
info->FbMapSize,
PCI_DEV_MAP_FLAG_WRITABLE |
-@@ -585,10 +560,10 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr)
+@@ -585,10 +558,10 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr)
unsigned char *RADEONMMIO = info->MMIO;
CARD32 data;
@@ -4382,7 +4617,7 @@
} else if (IS_AVIVO_VARIANT) {
OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
(void)INREG(AVIVO_MC_INDEX);
-@@ -614,12 +589,12 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data)
+@@ -614,12 +587,12 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data)
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
@@ -4401,7 +4636,7 @@
} else if (IS_AVIVO_VARIANT) {
OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000);
(void)INREG(AVIVO_MC_INDEX);
-@@ -636,7 +611,7 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data)
+@@ -636,7 +609,7 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data)
}
}
@@ -4410,7 +4645,7 @@
{
RADEONInfoPtr info = RADEONPTR(pScrn);
-@@ -648,7 +623,8 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
+@@ -648,7 +621,8 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
return TRUE;
else
return FALSE;
@@ -4420,7 +4655,7 @@
if (INMC(pScrn, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE)
return TRUE;
else
-@@ -663,7 +639,7 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
+@@ -663,7 +637,7 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
#define LOC_FB 0x1
#define LOC_AGP 0x2
@@ -4429,7 +4664,7 @@
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
-@@ -681,12 +657,13 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc,
+@@ -681,12 +655,13 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc,
if (mask & LOC_AGP)
OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc);
(void)INMC(pScrn, RV515_MC_AGP_LOCATION);
@@ -4445,7 +4680,7 @@
if (mask & LOC_FB)
OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc);
if (mask & LOC_AGP)
-@@ -700,7 +677,7 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc,
+@@ -700,7 +675,7 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc,
}
}
@@ -4454,7 +4689,7 @@
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
-@@ -719,7 +696,8 @@ void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc,
+@@ -719,7 +694,8 @@ void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc,
*agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
@@ -4464,41 +4699,7 @@
if (mask & LOC_FB)
*fb_loc = INMC(pScrn, RS690_MC_FB_LOCATION);
if (mask & LOC_AGP) {
-@@ -1207,30 +1185,15 @@ static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn)
- return TRUE;
- }
-
--void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
-- RADEONInfoPtr info)
--{
-- save->mc_fb_location = info->mc_fb_location;
-- save->mc_agp_location = info->mc_agp_location;
--
-- if (IS_AVIVO_VARIANT) {
-- save->mc_agp_location_hi = info->mc_agp_location_hi;
-- } else {
-- save->display_base_addr = info->fbLocation;
-- save->display2_base_addr = info->fbLocation;
-- save->ov0_base_addr = info->fbLocation;
-- }
--}
--
--static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
-+static void RADEONInitMemoryMap(ScrnInfoPtr pScrn, RADEONSavePtr save)
- {
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 mem_size;
- CARD32 aper_size;
-
-- radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location,
-- &info->mc_agp_location, &info->mc_agp_location_hi);
-+ radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location,
-+ &save->mc_agp_location, &save->mc_agp_location_hi);
-
- /* We shouldn't use info->videoRam here which might have been clipped
- * but the real video RAM instead
-@@ -1259,15 +1222,16 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
+@@ -1259,7 +1235,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
}
#endif
@@ -4506,88 +4707,9 @@
+ if ((info->ChipFamily != CHIP_FAMILY_RS690) &&
+ (info->ChipFamily != CHIP_FAMILY_RS740)) {
if (info->IsIGP)
-- info->mc_fb_location = INREG(RADEON_NB_TOM);
-+ save->mc_fb_location = INREG(RADEON_NB_TOM);
+ info->mc_fb_location = INREG(RADEON_NB_TOM);
else
- #ifdef XF86DRI
- /* Old DRI has restrictions on the memory map */
- if ( info->directRenderingEnabled &&
- info->pKernelDRMVersion->version_minor < 10 )
-- info->mc_fb_location = (mem_size - 1) & 0xffff0000U;
-+ save->mc_fb_location = (mem_size - 1) & 0xffff0000U;
- else
- #endif
- {
-@@ -1295,19 +1259,19 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
- aper0_base &= ~(mem_size - 1);
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
-- info->mc_fb_location = (aper0_base >> 24) |
-+ save->mc_fb_location = (aper0_base >> 24) |
- (((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
-- ErrorF("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
-+ ErrorF("mc fb loc is %08x\n", (unsigned int)save->mc_fb_location);
- } else {
-- info->mc_fb_location = (aper0_base >> 16) |
-+ save->mc_fb_location = (aper0_base >> 16) |
- ((aper0_base + mem_size - 1) & 0xffff0000U);
- }
- }
- }
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
-- info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
-+ info->fbLocation = (save->mc_fb_location & 0xffff) << 24;
- } else {
-- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
-+ info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
- }
- /* Just disable the damn AGP apertures for now, it may be
- * re-enabled later by the DRM
-@@ -1315,22 +1279,27 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
-
- if (IS_AVIVO_VARIANT) {
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
-- OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
-+ OUTREG(R600_HDP_NONSURFACE_BASE, (save->mc_fb_location << 16) & 0xff0000);
- } else {
-- OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
-+ OUTREG(AVIVO_HDP_FB_LOCATION, save->mc_fb_location);
- }
-- info->mc_agp_location = 0x003f0000;
-- } else
-- info->mc_agp_location = 0xffffffc0;
-+ save->mc_agp_location = 0x003f0000;
-+ } else {
-+ save->mc_agp_location = 0xffffffc0;
-+ save->display_base_addr = info->fbLocation;
-+ save->display2_base_addr = info->fbLocation;
-+ save->ov0_base_addr = info->fbLocation;
-+ }
-+
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "RADEONInitMemoryMap() : \n");
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " mem_size : 0x%08x\n", (unsigned)mem_size);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-- " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location);
-+ " MC_FB_LOCATION : 0x%08x\n", (unsigned)save->mc_fb_location);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- " MC_AGP_LOCATION : 0x%08x\n",
-- (unsigned)info->mc_agp_location);
-+ (unsigned)save->mc_agp_location);
- }
-
- static void RADEONGetVRamType(ScrnInfoPtr pScrn)
-@@ -1339,7 +1308,7 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn)
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 tmp;
--
-+
- if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) ||
- (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30)))
- info->IsDDR = TRUE;
-@@ -1458,23 +1427,20 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
+@@ -1458,23 +1435,20 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn)
MessageType from = X_PROBED;
CARD32 accessible, bar_size;
@@ -4614,7 +4736,7 @@
/* Some production boards of m6 will return 0 if it's 8 MB */
if (pScrn->videoRam == 0) {
pScrn->videoRam = 8192;
-@@ -2163,7 +2129,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
+@@ -2163,7 +2137,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
} else {
from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP,
&info->allowPageFlip) ? X_CONFIG : X_DEFAULT;
@@ -4630,7 +4752,7 @@
}
#else
from = X_DEFAULT;
-@@ -2221,7 +2194,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn)
+@@ -2221,7 +2202,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn)
info->pKernelDRMVersion->version_minor,
info->pKernelDRMVersion->version_patchlevel);
info->allowColorTiling = FALSE;
@@ -4639,7 +4761,7 @@
}
#endif /* XF86DRI */
-@@ -2366,7 +2339,7 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn)
+@@ -2366,7 +2347,7 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn)
}
bios_header=info->VBIOS[0x48];
@@ -4648,7 +4770,7 @@
mm_table=info->VBIOS[bios_header+0x38];
if(mm_table==0)
-@@ -2636,8 +2609,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2636,8 +2617,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive))
goto fail;
@@ -4658,7 +4780,7 @@
pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR;
pScrn->monitor = pScrn->confScreen->monitor;
-@@ -2689,7 +2661,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2689,7 +2669,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (!RADEONPreInitWeight(pScrn))
goto fail;
@@ -4667,7 +4789,7 @@
if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) {
if (strcmp(s, "AUTO") == 0) {
info->DispPriority = 1;
-@@ -2698,7 +2670,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2698,7 +2678,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
} else if (strcmp(s, "HIGH") == 0) {
info->DispPriority = 2;
} else
@@ -4676,7 +4798,7 @@
}
if (!RADEONPreInitInt10(pScrn, &pInt10))
-@@ -2739,17 +2711,22 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2739,17 +2719,22 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (crtc_max_Y > 8192)
crtc_max_Y = 8192;
} else {
@@ -4706,7 +4828,7 @@
}
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Max desktop size set to %dx%d\n",
-@@ -2793,14 +2770,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2793,14 +2778,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (!RADEONPreInitAccel(pScrn)) goto fail;
@@ -4726,7 +4848,7 @@
if (pScrn->modes == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n");
goto fail;
-@@ -3001,7 +2980,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn)
+@@ -3001,7 +2988,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn)
/* let the bios control the backlight */
save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
/* tell the bios not to handle mode switching */
@@ -4736,7 +4858,7 @@
if (info->ChipFamily >= CHIP_FAMILY_R600) {
OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch);
-@@ -3014,7 +2994,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn)
+@@ -3014,7 +3002,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn)
/* let the bios control the backlight */
save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
/* tell the bios not to handle mode switching */
@@ -4746,7 +4868,7 @@
/* tell the bios a driver is loaded */
save->bios_7_scratch |= RADEON_DRV_LOADED;
-@@ -3032,9 +3013,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3032,9 +3021,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -4756,15 +4878,28 @@
#ifdef RENDER
int subPixelOrder = SubPixelUnknown;
char* s;
-@@ -3136,15 +3115,20 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
- /* Initialize the memory map, this basically calculates the values
- * we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION
- */
-- RADEONInitMemoryMap(pScrn);
-+ RADEONInitMemoryMap(pScrn, info->ModeReg);
-+
-+ /* write any changes we made */
-+ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+@@ -3080,11 +3067,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+ RADEONBlank(pScrn);
+
+ if (info->IsMobility && !IS_AVIVO_VARIANT) {
+- if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
++ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
+ RADEONSetDynamicClock(pScrn, 1);
+- } else {
++ } else {
+ RADEONSetDynamicClock(pScrn, 0);
+- }
++ }
++ } else if (IS_AVIVO_VARIANT) {
++ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
++ atombios_static_pwrmgt_setup(pScrn, 1);
++ atombios_dyn_clk_setup(pScrn, 1);
++ }
+ }
+
+ if (IS_R300_VARIANT || IS_RV100_VARIANT)
+@@ -3139,12 +3131,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+ RADEONInitMemoryMap(pScrn);
/* empty the surfaces */
- unsigned char *RADEONMMIO = info->MMIO;
@@ -4784,25 +4919,7 @@
}
#ifdef XF86DRI
-@@ -3272,7 +3256,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "[drm] failed to enable new memory map\n");
- RADEONDRICloseScreen(pScreen);
-- info->directRenderingEnabled = FALSE;
-+ info->directRenderingEnabled = FALSE;
- }
- }
- #endif
-@@ -3332,7 +3316,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
- else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR;
- else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone;
- PictureSetSubpixelOrder (pScreen, subPixelOrder);
-- }
-+ }
- #endif
-
- pScrn->vtSema = TRUE;
-@@ -3340,28 +3324,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3340,28 +3334,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* xf86CrtcRotate() accesses pScrn->pScreen */
pScrn->pScreen = pScreen;
@@ -4831,46 +4948,7 @@
RADEONSaveScreen(pScreen, SCREEN_SAVER_ON);
-@@ -3399,7 +3363,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
- RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
-
- if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) {
-- /* we need to re-calculate bandwidth because of AGPMode difference. */
-+ /* we need to re-calculate bandwidth because of AGPMode difference. */
- RADEONInitDispBandwidth(pScrn);
- }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
-@@ -3537,8 +3501,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
- }
-
- /* Write memory mapping registers */
--void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
-- RADEONSavePtr restore)
-+static void
-+RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
-+ RADEONSavePtr restore)
- {
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
-@@ -3608,7 +3573,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
- } else {
- OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000);
- }
--
-+
- /* Reset the engine and HDP */
- RADEONEngineReset(pScrn);
- }
-@@ -3658,7 +3623,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
- | RADEON_CRTC2_DISP_REQ_EN_B);
- }
-
-- /* Make sure the chip settles down (paranoid !) */
-+ /* Make sure the chip settles down (paranoid !) */
- usleep(100000);
-
- /* Wait for MC idle */
-@@ -3760,15 +3725,15 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
+@@ -3760,15 +3734,15 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
CARD32 fb, agp, agp_hi;
@@ -4890,70 +4968,7 @@
changed = 1;
if (changed) {
-@@ -3776,21 +3741,28 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
- "DRI init changed memory map, adjusting ...\n");
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n",
-- (long unsigned int)info->mc_fb_location, (long unsigned int)fb);
-+ (long unsigned int)save->mc_fb_location, (long unsigned int)fb);
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
-- (long unsigned int)info->mc_agp_location, (long unsigned int)agp);
-- info->mc_fb_location = fb;
-- info->mc_agp_location = agp;
-+ (long unsigned int)save->mc_agp_location, (long unsigned int)agp);
-+ save->mc_fb_location = fb;
-+ save->mc_agp_location = agp;
-+ save->mc_agp_location_hi = agp_hi;
- if (info->ChipFamily >= CHIP_FAMILY_R600)
-- info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
-+ info->fbLocation = (save->mc_fb_location & 0xffff) << 24;
- else
-- info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
-+ info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
-+
-+ if (!IS_AVIVO_VARIANT) {
-+ save->display_base_addr = info->fbLocation;
-+ save->display2_base_addr = info->fbLocation;
-+ save->ov0_base_addr = info->fbLocation;
-+ }
-
- info->dst_pitch_offset =
- (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
- << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
-- RADEONInitMemMapRegisters(pScrn, save, info);
-+
- RADEONRestoreMemMapRegisters(pScrn, save);
- }
-
-@@ -3824,7 +3796,7 @@ static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore)
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned int surfnr;
--
-+
- for ( surfnr = 0; surfnr < 8; surfnr++ ) {
- OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]);
- OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]);
-@@ -3885,7 +3857,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
- color_pattern = R300_SURF_TILE_COLOR_MACRO;
- } else {
- color_pattern = R200_SURF_TILE_COLOR_MACRO;
-- }
-+ }
- #ifdef XF86DRI
- if (info->directRenderingInited) {
- drmRadeonSurfaceFree drmsurffree;
-@@ -3930,7 +3902,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
- if (retvalue < 0)
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "drm: could not allocate surface for front buffer!\n");
--
-+
- if ((info->have3DWindows) && (!info->noBackBuffer)) {
- drmsurfalloc.address = info->backOffset;
- retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
-@@ -4039,12 +4011,13 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save)
+@@ -4039,12 +4013,13 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
#endif
@@ -4968,7 +4983,7 @@
// state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE);
// state->vga_fb_start = INREG(AVIVO_VGA_FB_START);
-@@ -4110,8 +4083,6 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
+@@ -4110,8 +4085,6 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START);
state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE);
@@ -4977,7 +4992,7 @@
state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL);
-@@ -4151,57 +4122,207 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
+@@ -4151,57 +4124,207 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START);
state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE);
@@ -5178,8 +5193,8 @@
+ j++;
+ }
+ }
-+ }
-+
+ }
+
+ /* scalers */
+ j = 0;
+ for (i = 0x6578; i <= 0x65e4; i += 4) {
@@ -5196,10 +5211,10 @@
+ for (i = 0x66e8; i <= 0x66fc; i += 4) {
+ state->dxscl[j] = INREG(i);
+ j++;
- }
++ }
+ state->dxscl[6] = INREG(0x6e30);
+ state->dxscl[7] = INREG(0x6e34);
-
++
if (state->crtc1.control & AVIVO_CRTC_EN)
info->crtc_on = TRUE;
-
@@ -5220,7 +5235,7 @@
// OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map);
// OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base);
-@@ -4266,8 +4387,6 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
+@@ -4266,8 +4389,6 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start);
OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size);
@@ -5229,7 +5244,7 @@
OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source);
-@@ -4306,49 +4425,199 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
+@@ -4306,49 +4427,199 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start);
OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size);
@@ -5431,8 +5446,8 @@
+ j++;
+ }
+ }
-+ }
-+
+ }
+
+ /* scalers */
+ j = 0;
+ for (i = 0x6578; i <= 0x65e4; i += 4) {
@@ -5444,7 +5459,7 @@
+ OUTREG(i, state->d1scl[j]);
+ OUTREG((i + 0x800), state->d2scl[j]);
+ j++;
- }
++ }
+ j = 0;
+ for (i = 0x66e8; i <= 0x66fc; i += 4) {
+ OUTREG(i, state->dxscl[j]);
@@ -5452,7 +5467,7 @@
+ }
+ OUTREG(0x6e30, state->dxscl[6]);
+ OUTREG(0x6e34, state->dxscl[7]);
-
++
OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
}
@@ -5464,7 +5479,7 @@
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
struct avivo_state *state = &restore->avivo;
-@@ -4471,7 +4740,7 @@ static void RADEONSave(ScrnInfoPtr pScrn)
+@@ -4471,7 +4742,7 @@ static void RADEONSave(ScrnInfoPtr pScrn)
}
/* Restore the original (text) mode */
@@ -5473,12 +5488,7 @@
{
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
-@@ -4563,11 +4832,13 @@ void RADEONRestore(ScrnInfoPtr pScrn)
- #endif
-
- /* to restore console mode, DAC registers should be set after every other registers are set,
-- * otherwise,we may get blank screen
-+ * otherwise,we may get blank screen
+@@ -4567,7 +4838,9 @@ void RADEONRestore(ScrnInfoPtr pScrn)
*/
if (IS_AVIVO_VARIANT)
avivo_restore_vga_regs(pScrn, restore);
@@ -5489,16 +5499,7 @@
#if 0
RADEONWaitForVerticalSync(pScrn);
-@@ -4624,7 +4895,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
-
- if (info->allowColorTiling) {
- info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
--#ifdef XF86DRI
-+#ifdef XF86DRI
- if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
- RADEONSAREAPrivPtr pSAREAPriv;
- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
-@@ -4885,8 +5156,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -4885,8 +5158,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
@@ -5507,7 +5508,7 @@
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONEnterVT\n");
-@@ -4907,42 +5176,32 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -4907,41 +5178,34 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
RADEONWaitForIdleMMIO(pScrn);
if (info->IsMobility && !IS_AVIVO_VARIANT) {
@@ -5519,6 +5520,11 @@
RADEONSetDynamicClock(pScrn, 0);
- }
+ }
++ } else if (IS_AVIVO_VARIANT) {
++ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
++ atombios_static_pwrmgt_setup(pScrn, 1);
++ atombios_dyn_clk_setup(pScrn, 1);
++ }
}
if (IS_R300_VARIANT || IS_RV100_VARIANT)
@@ -5535,68 +5541,51 @@
- crtc->desiredX = 0;
- crtc->desiredY = 0;
- }
-
+-
- if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation,
- crtc->desiredX, crtc->desiredY))
- return FALSE;
-+ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
-+ RADEONRestoreSurfaces(pScrn, info->ModeReg);
- }
+ if (!xf86SetDesiredModes(pScrn))
+ return FALSE;
-- RADEONRestoreSurfaces(pScrn, info->ModeReg);
+ RADEONRestoreSurfaces(pScrn, info->ModeReg);
#ifdef XF86DRI
if (info->directRenderingEnabled) {
- if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize)
- {
- /* we need to backup the PCIE GART TABLE from fb memory */
- memcpy(info->FB + info->pciGartOffset, info->pciGartBackup, info->pciGartSize);
-- }
-+ if (info->cardType == CARD_PCIE &&
++ if (info->cardType == CARD_PCIE &&
+ info->pKernelDRMVersion->version_minor >= 19 &&
+ info->FbSecureSize) {
+ /* we need to backup the PCIE GART TABLE from fb memory */
+ memcpy(info->FB + info->pciGartOffset, info->pciGartBackup, info->pciGartSize);
-+ }
+ }
/* get the DRI back into shape after resume */
- RADEONDRISetVBlankInterrupt (pScrn, TRUE);
-@@ -4951,6 +5210,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
-
- }
- #endif
-+
- /* this will get XVideo going again, but only if XVideo was initialised
- during server startup (hence the info->adaptor if). */
- if (info->adaptor)
-@@ -4966,7 +5226,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -4966,8 +5230,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
}
#endif
- // pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
-
+-
return TRUE;
}
-@@ -4988,11 +5247,12 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+
+@@ -4988,8 +5250,9 @@ void RADEONLeaveVT(int scrnIndex, int flags)
DRILock(pScrn->pScreen, 0);
RADEONCP_STOP(pScrn, info);
- if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize)
- {
-- /* we need to backup the PCIE GART TABLE from fb memory */
-- memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize);
-- }
-+ if (info->cardType == CARD_PCIE &&
++ if (info->cardType == CARD_PCIE &&
+ info->pKernelDRMVersion->version_minor >= 19 &&
+ info->FbSecureSize) {
-+ /* we need to backup the PCIE GART TABLE from fb memory */
-+ memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize);
-+ }
-
- /* Make sure 3D clients will re-upload textures to video RAM */
- if (info->textureSize) {
+ /* we need to backup the PCIE GART TABLE from fb memory */
+ memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize);
+ }
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 4da4841..a6ededa 100644
--- a/src/radeon_exa.c
@@ -5658,7 +5647,7 @@
RADEONEngineInit(pScrn);
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
-index 9bbccb5..9496bb6 100644
+index 9bbccb5..4e5ab81 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -177,9 +177,8 @@ static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format)
@@ -5824,6 +5813,13 @@
+
+ if (pMaskPicture) {
+ PixmapPtr pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable);
++
++ if (pMaskPixmap->drawable.width >= 2048 ||
++ pMaskPixmap->drawable.height >= 2048) {
++ RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n",
++ pMaskPixmap->drawable.width,
++ pMaskPixmap->drawable.height));
++ }
- if (pMaskPicture != NULL && pMaskPicture->componentAlpha) {
- /* Check if it's component alpha that relies on a source alpha and on
@@ -5836,13 +5832,6 @@
- {
- RADEON_FALLBACK(("Component alpha not supported with source "
- "alpha and source value blending.\n"));
-+ if (pMaskPixmap->drawable.width >= 2048 ||
-+ pMaskPixmap->drawable.height >= 2048) {
-+ RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n",
-+ pMaskPixmap->drawable.width,
-+ pMaskPixmap->drawable.height));
- }
-+
+ if (pMaskPicture->componentAlpha) {
+ /* Check if it's component alpha that relies on a source alpha and
+ * on the source value. We can only get one of those into the
@@ -5854,7 +5843,7 @@
+ RADEON_FALLBACK(("Component alpha not supported with source "
+ "alpha and source value blending.\n"));
+ }
-+ }
+ }
+
+ if (!R200CheckCompositeTexture(pMaskPicture, 1))
+ return FALSE;
@@ -5903,7 +5892,15 @@
RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h));
for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++)
-@@ -809,11 +885,16 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+@@ -794,6 +870,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+ if ((txpitch & 0x1f) != 0)
+ RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
+
++ /* TXPITCH = pixels (texels) per line - 1 */
+ pixel_shift = pPix->drawable.bitsPerPixel >> 4;
+ txpitch >>= pixel_shift;
+ txpitch -= 1;
+@@ -809,24 +886,32 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txformat1 = R300TexFormats[i].card_fmt;
@@ -5911,28 +5908,44 @@
- ((h - 1) << R300_TXHEIGHT_SHIFT));
+ txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
+ (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
-+
+
+- if (pPict->repeat) {
+- ErrorF("repeat\n");
+- if ((h != 1) &&
+- (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch))
+- RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
+- w, (unsigned)txpitch));
+- } else
+- txformat0 |= R300_TXPITCH_EN;
+ if (IS_R500_3D && ((w - 1) & 0x800))
+ txpitch |= R500_TXWIDTH_11;
-+
+
+ if (IS_R500_3D && ((h - 1) & 0x800))
+ txpitch |= R500_TXHEIGHT_11;
++
++ /* Use TXPITCH instead of TXWIDTH for address computations: we could
++ * omit this if there is no padding, but there is no apparent advantage
++ * in doing so.
++ */
++ txformat0 |= R300_TXPITCH_EN;
- if (pPict->repeat) {
-- ErrorF("repeat\n");
- if ((h != 1) &&
- (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch))
- RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
-@@ -828,6 +909,8 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
- txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
- R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST));
+ info->texW[unit] = w;
+ info->texH[unit] = h;
-+ txfilter |= (unit << R300_TX_ID_SHIFT);
+- txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
+- R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST));
++ if (pPict->repeat)
++ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP) |
++ R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP));
++ else
++ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
++ R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST));
+
++ txfilter |= (unit << R300_TX_ID_SHIFT);
+
switch (pPict->filter) {
case PictFilterNearest:
- txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST);
-@@ -841,7 +924,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+@@ -841,7 +926,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
BEGIN_ACCEL(6);
OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter);
@@ -5941,7 +5954,7 @@
OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0);
OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1);
OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch);
-@@ -867,8 +950,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
+@@ -867,8 +952,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
ScreenPtr pScreen = pDstPicture->pDrawable->pScreen;
PixmapPtr pSrcPixmap, pDstPixmap;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
@@ -5952,7 +5965,7 @@
TRACE;
-@@ -876,51 +959,64 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
+@@ -876,51 +961,64 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
@@ -6050,7 +6063,7 @@
return FALSE;
if (!R300GetDestFormat(pDstPicture, &tmp1))
-@@ -940,7 +1036,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -940,7 +1038,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
CARD32 txenable, colorpitch;
CARD32 blendcntl;
int pixel_shift;
@@ -6058,7 +6071,7 @@
ACCEL_PREAMBLE();
TRACE;
-@@ -948,7 +1043,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -948,7 +1045,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
if (!info->XInited3D)
RADEONInit3DEngine(pScrn);
@@ -6069,7 +6082,7 @@
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
-@@ -979,279 +1076,643 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -979,279 +1078,643 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
RADEON_SWITCH_TO_3D();
Index: xorg-x11-drv-ati.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/xorg-x11-drv-ati.spec,v
retrieving revision 1.90
retrieving revision 1.91
diff -u -r1.90 -r1.91
--- xorg-x11-drv-ati.spec 2 Apr 2008 00:07:55 -0000 1.90
+++ xorg-x11-drv-ati.spec 6 Apr 2008 07:14:38 -0000 1.91
@@ -5,7 +5,7 @@
Summary: Xorg X11 ati video driver
Name: xorg-x11-drv-ati
Version: 6.8.0
-Release: 9%{?dist}
+Release: 10%{?dist}
URL: http://www.x.org
License: MIT
Group: User Interface/X Hardware Support
@@ -89,6 +89,9 @@
%{_mandir}/man4/radeon.4*
%changelog
+* Sun Apr 06 2008 Dave Airlie <airlied at redhat.com> 6.8.0-10
+- attempt to fix VT switch and X restart hangs
+
* Wed Apr 02 2008 Dave Airlie <airlied at redhat.com> 6.8.0-9
- attempt to fix dualhead and rotation at the same time.
- Previous message (by thread): rpms/jd/devel .cvsignore, 1.217, 1.218 jd.spec, 1.252, 1.253 sources, 1.218, 1.219
- Next message (by thread): rpms/jd/devel jd-2.0.0-svn1936_trunk-gcc43.patch, NONE, 1.1 jd.spec, 1.253, 1.254
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