rpms/oprofile/F-8 oprofile-0.9.3-xen.patch, NONE, 1.1 oprofile-0.9.3-family10.patch, NONE, 1.1 oprofile-0.9.3-ranges.patch, NONE, 1.1 oprofile-0.9.3-970MP.patch, NONE, 1.1 oprofile-0.9.3-fmtver.patch, NONE, 1.1 oprofile-gcc43.patch, NONE, 1.1 oprofile.spec, 1.61, 1.62 oprofile-0.4-guess2.patch, 1.1, 1.2 oprofile-0.9.1-xen.patch, 1.4, NONE
William Eden Cohen (wcohen)
fedora-extras-commits at redhat.com
Mon Jun 23 20:04:19 UTC 2008
Author: wcohen
Update of /cvs/pkgs/rpms/oprofile/F-8
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv5813
Modified Files:
oprofile.spec oprofile-0.4-guess2.patch
Added Files:
oprofile-0.9.3-xen.patch oprofile-0.9.3-family10.patch
oprofile-0.9.3-ranges.patch oprofile-0.9.3-970MP.patch
oprofile-0.9.3-fmtver.patch oprofile-gcc43.patch
Removed Files:
oprofile-0.9.1-xen.patch
Log Message:
* Mon Jun 23 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-18
- Fix default location for vmlinux. rhbz #451539
* Fri Apr 04 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-17
- Use older qt3-devel. rhbz #440949
* Fri Feb 15 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-16
- Corrections for compilation with gcc-4.3.
* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-15
- Deal with xenoprof conlficts with cell. Resolves: rhbz #250852
* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-14
- Bump format version. Check version properly. Resolves: rhbz #394571
* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-13
- Disable profiling in hypervisor on 970MP to prevent lost interrupts.
Resolves: rhbz #391251
* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-12
- Use more incluse set of kernel ranges. Resolves: rhbz #307111
* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-11
- Update AMD family 10h events to match AMD documentation Resolves: rhbz #232956
oprofile-0.9.3-xen.patch:
--- NEW FILE oprofile-0.9.3-xen.patch ---
diff -Naur oprofile-0.9.3/daemon/init.c oprofile-0.9.3-xen-r2/daemon/init.c
--- oprofile-0.9.3/daemon/init.c 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/daemon/init.c 2007-07-30 10:28:09.000000000 -0700
@@ -226,6 +226,8 @@
opd_create_vmlinux(vmlinux, kernel_range);
opd_create_xen(xenimage, xen_range);
+ if (xen_passive_setup)
+ opd_create_passive(xen_passive_setup);
opd_buf_size = opd_read_fs_int("/dev/oprofile/", "buffer_size", 1);
kernel_pointer_size = opd_read_fs_int("/dev/oprofile/", "pointer_size", 1);
diff -Naur oprofile-0.9.3/daemon/opd_interface.h oprofile-0.9.3-xen-r2/daemon/opd_interface.h
--- oprofile-0.9.3/daemon/opd_interface.h 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/daemon/opd_interface.h 2007-12-20 11:59:20.000000000 -0800
@@ -27,8 +27,19 @@
/* Code 9 used to be TRACE_END_CODE which is not used anymore */
/* Code 9 is now considered an unknown escape code */
#define XEN_ENTER_SWITCH_CODE 10
+/*
+ * Ugly work-around for the unfortunate collision between Xenoprof's
+ * DOMAIN_SWITCH_CODE (in use on x86 and ia64) and Cell's SPU_PROFILING_CODE
+ * (in use with Power):
+ */
+#if defined(__i386__) || defined(__x86_64__) || defined(__ia64__)
+#define DOMAIN_SWITCH_CODE 11
+#define LAST_CODE 12
+#else
#define SPU_PROFILING_CODE 11
#define SPU_CTX_SWITCH_CODE 12
-#define LAST_CODE 13
+#define DOMAIN_SWITCH_CODE 13
+#define LAST_CODE 14
+#endif
#endif /* OPD_INTERFACE_H */
diff -Naur oprofile-0.9.3/daemon/opd_kernel.c oprofile-0.9.3-xen-r2/daemon/opd_kernel.c
--- oprofile-0.9.3/daemon/opd_kernel.c 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/daemon/opd_kernel.c 2007-08-02 09:46:27.000000000 -0700
@@ -34,11 +34,22 @@
static struct kernel_image xen_image;
+static struct kernel_image xen_image_anon;
+static struct kernel_image vmlinux_image_anon;
+
+static LIST_HEAD(passive_vmlinux);
+static LIST_HEAD(passive_xen);
+static LIST_HEAD(passive_apps);
+static LIST_HEAD(passive_modules);
+static LIST_HEAD(passive_xen_anon);
+
void opd_create_vmlinux(char const * name, char const * arg)
{
/* vmlinux is *not* on the list of modules */
list_init(&vmlinux_image.list);
+ list_init(&vmlinux_image_anon.list);
+
/* for no vmlinux */
if (no_vmlinux) {
vmlinux_image.name = "no-vmlinux";
@@ -57,13 +68,22 @@
vmlinux_image.start, vmlinux_image.end);
exit(EXIT_FAILURE);
}
+
+ vmlinux_image_anon.name = "vmlinux-unknown";
+ vmlinux_image_anon.start = vmlinux_image.start;
+ vmlinux_image_anon.end = vmlinux_image.end;
+
}
void opd_create_xen(char const * name, char const * arg)
{
+ int stat;
+
/* xen is *not* on the list of modules */
list_init(&xen_image.list);
+ list_init(&xen_image_anon.list);
+
/* for no xen */
if (no_xen) {
xen_image.name = "no-xen";
@@ -72,18 +92,106 @@
xen_image.name = xstrdup(name);
- sscanf(arg, "%llx,%llx", &xen_image.start, &xen_image.end);
+ stat = sscanf(arg, "%llx,%llx", &xen_image.start, &xen_image.end);
+
+ xen_image_anon.name = "xen-unknown";
+ xen_image_anon.start = xen_image.start;
+ xen_image_anon.end = xen_image.end;
verbprintf(vmisc, "xen_start = %llx, xen_end = %llx\n",
xen_image.start, xen_image.end);
- if (!xen_image.start && !xen_image.end) {
+ if ( stat != 2 ) {
fprintf(stderr, "error: mis-parsed xen range: %llx-%llx\n",
xen_image.start, xen_image.end);
exit(EXIT_FAILURE);
}
+
}
+void opd_create_passive_domain(int id, char const * image_kernel,
+ char const * range, char const * image_xen)
+{
+ char file[64];
+ struct kernel_image * image;
+ int stat;
+
+ image = xmalloc(sizeof(struct kernel_image));
+ image->name = xstrdup(image_kernel);
+ image->start = image->end = 0;
+ stat = sscanf(range, "%llx,%llx", &image->start, &image->end);
+ image->id = id;
+ list_add(&image->list, &passive_vmlinux);
+
+ if ( stat != 2 ) {
+ fprintf(stderr, "error: mis-parsed passive domain range for "
+ "domain %d: %llx-%llx\n", id, image->start, image->end);
+ exit(EXIT_FAILURE);
+ }
+
+ image = xmalloc(sizeof(struct kernel_image));
+ image->name = xstrdup(image_xen);
+ image->start = xen_image.start;
+ image->end = xen_image.end;
+ image->id = id;
+ list_add(&image->list, &passive_xen);
+
+ sprintf(file, "domain%d-apps", id);
+ image = xmalloc(sizeof(struct kernel_image));
+ image->name = xstrdup(file);
+ image->start = 0;
+ image->end = 0;
+ image->id = id;
+ list_add(&image->list, &passive_apps);
+
+ sprintf(file, "domain%d-modules", id);
+ image = xmalloc(sizeof(struct kernel_image));
+ image->name = xstrdup(file);
+ image->start = 0;
+ image->end = 0;
+ stat = sscanf(range, "%llx,%llx", &image->start, &image->end);
+ image->id = id;
+ list_add(&image->list, &passive_modules);
+
+ sprintf(file, "domain%d-xen-unknown", id);
+ image = xmalloc(sizeof(struct kernel_image));
+ image->name = xstrdup(file);
+ image->start = xen_image.start;
+ image->end = xen_image.end;
+ image->id = id;
+ list_add(&image->list, &passive_xen_anon);
+
+}
+
+void opd_create_passive(char const *setup_file)
+{
+ FILE *fp;
+ int id=0;
+ char image_kernel[128+1];
+ char range[128+1];
+ char image_xen[128+1];
+ int stat;
+
+ image_kernel[0] = range[0] = image_xen[0] = 0;
+
+ fp = fopen(setup_file, "r");
+
+ if (!fp) {
+ fprintf(stderr, "error: Could not open Xen passive domain "
+ "setup file %s\n", setup_file);
+ exit(EXIT_FAILURE);
+ }
+
+ while (1) {
+ stat = fscanf(fp, "%d %128s %128s %128s", &id, image_kernel, range,
+ image_xen);
+ if ( stat != 4 )
+ return;
+ opd_create_passive_domain(id, image_kernel, range, image_xen);
+ }
+
+ fclose(fp);
+}
/**
* Allocate and initialise a kernel image description
@@ -210,6 +318,75 @@
struct list_head * pos;
struct kernel_image * image = &vmlinux_image;
+ if (current_domain != COORDINATOR_DOMAIN) {
+ /* we rely on cpu_mode value (i.e. trans->in_kernel)
+ * to search the right image type: xen, kernel or user
+ * We cannot use address ranges since hypervisor does not
+ * share the same address space with fully virtualized guests,
+ * and thus address ranges can overlap */
+ switch ( trans->in_kernel ) {
+
+ /* user mode */
+ case 1:
+ list_for_each(pos, &passive_apps) {
+ image = list_entry(pos, struct kernel_image, list);
+ if (image->id == current_domain)
+ return image;
+ }
+ return NULL;
+
+ /* kernel mode */
+ case 2:
+ list_for_each(pos, &passive_vmlinux) {
+ image = list_entry(pos, struct kernel_image, list);
+ if ( (image->id == current_domain)
+ && ( (image->start == 0 && image->end == 0)
+ || (image->start <= trans->pc
+ && image->end > trans->pc) ) )
+ return image;
+ }
+ /* if not in kernel image range then it should be a module */
+ list_for_each(pos, &passive_modules) {
+ image = list_entry(pos, struct kernel_image, list);
+ if (image->id == current_domain)
+ return image;
+ }
+ /* This should not happen if the kernel and user level
+ oprofile code are sane and in sync */
+ return NULL;
+
+ /* hypervisor mode */
+ case 3:
+ list_for_each(pos, &passive_xen) {
+ image = list_entry(pos, struct kernel_image, list);
+ if (image->id == current_domain
+ && image->start <= trans->pc
+ && image->end > trans->pc)
+ return image;
+ }
+ list_for_each(pos, &passive_xen_anon) {
+ image = list_entry(pos, struct kernel_image, list);
+ if (image->id == current_domain)
+ return image;
+ }
+ return NULL;
+
+ default:
+ printf("Unexpected error on passive mode: CPU mode is "
+ "%d for domain %d\n", trans->in_kernel, current_domain);
+ return NULL;
+ }
+
+
+ }
+
+ if (xen_image.start <= trans->pc && xen_image.end > trans->pc)
+ return &xen_image;
+
+ if (trans->in_kernel == 2) {
+ return &xen_image_anon;
+ }
+
if (no_vmlinux)
return image;
@@ -222,8 +399,5 @@
return image;
}
- if (xen_image.start <= trans->pc && xen_image.end > trans->pc)
- return &xen_image;
-
- return NULL;
+ return &vmlinux_image_anon;
}
diff -Naur oprofile-0.9.3/daemon/opd_kernel.h oprofile-0.9.3-xen-r2/daemon/opd_kernel.h
--- oprofile-0.9.3/daemon/opd_kernel.h 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/daemon/opd_kernel.h 2007-07-30 10:28:09.000000000 -0700
@@ -23,8 +23,12 @@
/** create the kernel image */
void opd_create_vmlinux(char const * name, char const * arg);
+/** create Xen image */
void opd_create_xen(char const * name, char const * arg);
+/** create Xen passive domain images */
+void opd_create_passive(char const *setup_file);
+
/** opd_reread_module_info - parse /proc/modules for kernel modules */
void opd_reread_module_info(void);
@@ -33,6 +37,7 @@
char * name;
vma_t start;
vma_t end;
+ int id;
struct list_head list;
};
diff -Naur oprofile-0.9.3/daemon/opd_perfmon.c oprofile-0.9.3-xen-r2/daemon/opd_perfmon.c
--- oprofile-0.9.3/daemon/opd_perfmon.c 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/daemon/opd_perfmon.c 2007-12-20 12:07:50.000000000 -0800
@@ -380,6 +380,7 @@
close(child->up_pipe[1]);
}
+static struct child* xen_ctx;
void perfmon_init(void)
{
@@ -389,6 +390,24 @@
if (cpu_type == CPU_TIMER_INT)
return;
+ if (!no_xen) {
+ xen_ctx = xmalloc(sizeof(struct child));
+ xen_ctx->pid = getpid();
+ xen_ctx->up_pipe[0] = -1;
+ xen_ctx->up_pipe[1] = -1;
+ xen_ctx->sigusr1 = 0;
+ xen_ctx->sigusr2 = 0;
+ xen_ctx->sigterm = 0;
+
+ create_context(xen_ctx);
+
+ write_pmu(xen_ctx);
+
+ load_context(xen_ctx);
+ return;
+ }
+
+
nr = sysconf(_SC_NPROCESSORS_ONLN);
if (nr == -1) {
fprintf(stderr, "Couldn't determine number of CPUs.\n");
@@ -431,6 +450,9 @@
if (cpu_type == CPU_TIMER_INT)
return;
+ if (!no_xen)
+ return;
+
for (i = 0; i < nr_cpus; ++i) {
kill(children[i].pid, SIGKILL);
waitpid(children[i].pid, NULL, 0);
@@ -445,6 +467,11 @@
if (cpu_type == CPU_TIMER_INT)
return;
+ if (!no_xen) {
+ perfmon_start_child(xen_ctx->ctx_fd);
+ return;
+ }
+
for (i = 0; i < nr_cpus; ++i)
kill(children[i].pid, SIGUSR1);
}
@@ -457,6 +484,11 @@
if (cpu_type == CPU_TIMER_INT)
return;
+ if (!no_xen) {
+ perfmon_stop_child(xen_ctx->ctx_fd);
+ return;
+ }
+
for (i = 0; i < nr_cpus; ++i)
kill(children[i].pid, SIGUSR2);
}
diff -Naur oprofile-0.9.3/daemon/opd_sfile.c oprofile-0.9.3-xen-r2/daemon/opd_sfile.c
--- oprofile-0.9.3/daemon/opd_sfile.c 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/daemon/opd_sfile.c 2007-07-30 10:28:09.000000000 -0700
@@ -234,7 +234,7 @@
}
/* we might need a kernel image start/end to hash on */
- if (trans->in_kernel) {
+ else if (trans->in_kernel) {
ki = find_kernel_image(trans);
if (!ki) {
verbprintf(vsamples, "Lost kernel sample %llx\n", trans->pc);
diff -Naur oprofile-0.9.3/daemon/opd_trans.c oprofile-0.9.3-xen-r2/daemon/opd_trans.c
--- oprofile-0.9.3/daemon/opd_trans.c 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/daemon/opd_trans.c 2007-12-20 12:03:23.000000000 -0800
@@ -31,6 +31,8 @@
#include <stdio.h>
#include <errno.h>
+int32_t current_domain = COORDINATOR_DOMAIN;
+
extern size_t kernel_pointer_size;
@@ -203,6 +205,9 @@
{
verbprintf(vmisc, "KERNEL_ENTER_SWITCH to kernel\n");
trans->in_kernel = 1;
+ /* if in passive domain mode cpu mode should be incremented */
+ if (current_domain != COORDINATOR_DOMAIN)
+ trans->in_kernel++;
clear_trans_current(trans);
/* subtlety: we must keep trans->cookie cached,
* even though it's meaningless for the kernel -
@@ -216,6 +221,9 @@
{
verbprintf(vmisc, "USER_ENTER_SWITCH to user-space\n");
trans->in_kernel = 0;
+ /* if in passive domain mode cpu mode should be incremented */
+ if (current_domain != COORDINATOR_DOMAIN)
+ trans->in_kernel++;
clear_trans_current(trans);
clear_trans_last(trans);
}
@@ -244,15 +252,33 @@
static void code_xen_enter(struct transient * trans)
{
verbprintf(vmisc, "XEN_ENTER_SWITCH to xen\n");
- trans->in_kernel = 1;
+ trans->in_kernel = 2;
+ /* if in passive domain mode cpu mode should be incremented */
+ if (current_domain != COORDINATOR_DOMAIN)
+ trans->in_kernel++;
trans->current = NULL;
/* subtlety: we must keep trans->cookie cached, even though it's
- * meaningless for Xen - we won't necessarily get a cookie switch
- * on Xen exit. See comments in opd_sfile.c. It seems that we can
- * get away with in_kernel = 1 as long as we supply the correct
- * Xen image, and its address range in startup find_kernel_image
- * is modified to look in the Xen image also
+ * meaningless for Xen - same reason as for kernel */
+
+}
+
+static void code_domain_switch(struct transient *trans)
+{
+ /* While processing passive domain samples we ensure (in_kernel!=0)
+ * We do this in order to ignore cookies for passive domain samples
+ * But, we have to remember the kernel value for coordinator domain,
+ * so we do the safe thing: increment when leaving the coordinator
+ * domain and decrement when returning to it
*/
+ if (current_domain == COORDINATOR_DOMAIN)
+ trans->in_kernel++;
+
+ trans->current = NULL;
+ current_domain = (int32_t) pop_buffer_value(trans);
+
+ /* If returning to coordinator domain restore the kernel value */
+ if (current_domain == COORDINATOR_DOMAIN)
+ trans->in_kernel--;
}
extern void code_spu_profiling(struct transient * trans);
@@ -271,8 +297,16 @@
&code_trace_begin,
&code_unknown,
&code_xen_enter,
+/*
+ * Ugly work-around for the unfortunate collision between Xenoprof's
+ * DOMAIN_SWITCH_CODE (in use on x86 and ia64) and Cell's SPU_PROFILING_CODE
+ * (in use with Power):
+ */
+#if !defined(__i386__) && !defined(__x86_64__) && !defined(__ia64__)
&code_spu_profiling,
&code_spu_ctx_switch,
+#endif
+ &code_domain_switch,
};
extern void (*special_processor)(struct transient *);
diff -Naur oprofile-0.9.3/daemon/opd_trans.h oprofile-0.9.3-xen-r2/daemon/opd_trans.h
--- oprofile-0.9.3/daemon/opd_trans.h 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/daemon/opd_trans.h 2007-07-30 10:28:09.000000000 -0700
@@ -21,6 +21,10 @@
#include <stdint.h>
+#define COORDINATOR_DOMAIN -1
+
+extern int32_t current_domain;
+
struct sfile;
struct anon_mapping;
diff -Naur oprofile-0.9.3/daemon/oprofiled.c oprofile-0.9.3-xen-r2/daemon/oprofiled.c
--- oprofile-0.9.3/daemon/oprofiled.c 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/daemon/oprofiled.c 2007-07-30 10:28:09.000000000 -0700
@@ -67,6 +67,7 @@
int no_xen;
char * xenimage;
char * xen_range;
+char * xen_passive_setup;
static char * verbose;
static char * binary_name_filter;
static char * events;
@@ -86,6 +87,7 @@
{ "xen-range", 0, POPT_ARG_STRING, &xen_range, 0, "Xen VMA range", "start-end", },
{ "xen-image", 0, POPT_ARG_STRING, &xenimage, 0, "Xen image", "file", },
{ "image", 0, POPT_ARG_STRING, &binary_name_filter, 0, "image name filter", "profile these comma separated image" },
+ { "xen-passive-setup", 0, POPT_ARG_STRING, &xen_passive_setup, 0, "Xen passive domain setup file", "filename", },
{ "separate-lib", 0, POPT_ARG_INT, &separate_lib, 0, "separate library samples for each distinct application", "[0|1]", },
{ "separate-kernel", 0, POPT_ARG_INT, &separate_kernel, 0, "separate kernel samples for each distinct application", "[0|1]", },
{ "separate-thread", 0, POPT_ARG_INT, &separate_thread, 0, "thread-profiling mode", "[0|1]" },
diff -Naur oprofile-0.9.3/daemon/oprofiled.h oprofile-0.9.3-xen-r2/daemon/oprofiled.h
--- oprofile-0.9.3/daemon/oprofiled.h 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/daemon/oprofiled.h 2007-07-30 10:28:09.000000000 -0700
@@ -64,5 +64,6 @@
extern int no_xen;
extern char * xenimage;
extern char * xen_range;
+extern char * xen_passive_setup;
#endif /* OPROFILED_H */
diff -Naur oprofile-0.9.3/doc/opcontrol.1.in oprofile-0.9.3-xen-r2/doc/opcontrol.1.in
--- oprofile-0.9.3/doc/opcontrol.1.in 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/doc/opcontrol.1.in 2007-07-30 10:28:09.000000000 -0700
@@ -147,12 +147,41 @@
.br
.TP
.BI "--active-domains="<list>
-List of domain ids participating in a multi-domain profiling session. If
+List of domain ids participating in a multi-domain profiling session.
+Each of the specified domains must run an instance of oprofile. The
+sequence of opcontrol commands in each domain must follow a given
+order which is specified in the oprofile user manual. If
more than one domain is specified in <list> they should be separated using
commas. This option can only be used in domain 0 which is the only domain
that can coordinate a multi-domain profiling session. Including domain 0 in
the list of active domains is optional. (e.g. --active-domains=2,5,6 and
---active-domains=0,2,5,6 are equivalent)
+--active-domains=0,2,5,6 are equivalent).
+This option can only be specified
+if --start-daemon is also specified and it is only
+valid for the current run of the oprofile daemon; e.g. the list
+of active domains is not persistent.
+.br
+.TP
+.BI "--passive-domains="<list> or "--domains="<list>
+List of domain ids to be profiled, separated by commas.
+As opposed to the --active-domains option, the domains specified with this
+option do not need to run oprofile. This makes
+profiling multiple domains easier. However, with the passive-domains option,
+samples in user level processes and kernel modules cannot be
+mapped to specific symbols and are aggregated
+under a generic class. Both --active-domains and --passive-domains
+options can be specified in the same command, but the same domain cannot be
+specified in both options. This option can only be specified if either --start
+or --start-daemon is specified on the same command and it is only valid for
+the current run of the oprofile daemon; e.g. the list of passive domains is
+not persistent.
+.br
+.TP
+.BI "--passive-images="<list> or "--domains-images="<list>
+List of kernel images associated with the domains specified in the
+--passive-domains option, also separated by commas. The association
+between the images and domains is based on the order they are
+specified in both options.
.br
.SH ENVIRONMENT
diff -Naur oprofile-0.9.3/utils/opcontrol oprofile-0.9.3-xen-r2/utils/opcontrol
--- oprofile-0.9.3/utils/opcontrol 2007-07-16 11:22:17.000000000 -0700
+++ oprofile-0.9.3-xen-r2/utils/opcontrol 2007-07-30 12:22:19.000000000 -0700
@@ -144,9 +144,16 @@
--cpu-buffer-size=num per-cpu buffer size in units (2.6 only)
--note-table-size kernel notes buffer size in notes units (2.4 only)
- --xen Xen image (for Xen only)
- --active-domains=<list> List of domains in profiling session (for Xen only)
- (list contains domain ids separated by commas)
+ --xen=file Xen image (for Xen only)
+ --active-domains=id[,ids] list of domains in multiple domain profiling session (Xen)
+ (detailed profiling of user level and kernel modules code)
+ (requires running oprofile on these domains)
+ --passive-domains=id[,ids] list of domains to be profiled (Xen).
+ or --domains=id[,ids] (coarse profiling of user level and kernel modules code)
+ (no need to run oprofile on these domains)
+ --passive-images=file[,files] list of kernel images associated with each passive domain
+ or
+ --domain-images=file[,files]
" >&2
}
@@ -289,6 +296,9 @@
SETUP_DIR="/root/.oprofile"
SETUP_FILE="$SETUP_DIR/daemonrc"
+ # location for passing info about passive domains to daemon
+ PASSIVE_SETUP_FILE="$SETUP_DIR/xendomain.setup"
+
# initialize daemon vars
decide_oprofile_device_mount
CPUTYPE=`cat $MOUNT/cpu_type`
@@ -433,7 +443,7 @@
}
-check_valid_args()
+check_valid_vmlinux()
{
if test -z "$VMLINUX"; then
echo "No vmlinux file specified. You must specify the correct vmlinux file, e.g." >&2
@@ -454,8 +464,12 @@
echo "The specified vmlinux file \"$VMLINUX\" doesn't exist." >&2
exit 1
+}
+
# similar check for Xen image
+check_valid_xen()
+{
if test -f "$XENIMAGE"; then
return
fi
@@ -511,6 +525,76 @@
fi
}
+set_passive_domain()
+{
+ DOMAIN_ID=$1
+ FILE_IMAGE=$2
+ XEN_IMAGE=$3
+
+ if test "$FILE_IMAGE" = "none"; then
+ RANGE="0,0"
+ FILE_IMAGE="domain$DOMAIN_ID-kernel"
+ else
+ # Find VMA range for passive domain kernel image
+ range_info=`objdump -h $FILE_IMAGE 2>/dev/null | grep " .text "`
+ tmp1=`echo $range_info | awk '{print $4}'`
+ tmp_length=`echo $range_info | awk '{print $3}'`
+ tmp2=`objdump -h $FILE_IMAGE --adjust-vma=0x$tmp_length 2>/dev/null | grep " .text " | awk '{print $4}'`
+
+ if test -z "$tmp1" -o -z "$tmp2"; then
+ echo "The specified file $FILE_IMAGE does not seem to be valid" >&2
+ echo "Make sure you are using the non-compressed image file (e.g. vmlinux not vmlinuz)" >&2
+ vecho "found start as \"$tmp1\", end as \"$tmp2\"" >&2
+ exit 1
+ fi
+ RANGE="`echo $tmp1`,`echo $tmp2`"
+ fi
+ echo " $DOMAIN_ID $FILE_IMAGE $RANGE $XEN_IMAGE" >> $PASSIVE_SETUP_FILE
+}
+
+
+set_passive_domain_config()
+{
+
+ create_dir "$SETUP_DIR"
+
+ touch $PASSIVE_SETUP_FILE
+ chmod 644 $PASSIVE_SETUP_FILE
+ >$PASSIVE_SETUP_FILE
+
+ NDOMAINS=`echo "$PASSIVE_DOMAINS" | awk -F',' '{print NF}'`
+
+ if test -n "$PASSIVE_IMAGES"; then
+ NIMAGES=`echo "$PASSIVE_IMAGES" | awk -F',' '{print NF}'`
+ if [ $NDOMAINS != $NIMAGES ]; then
+ echo "# of passive domains and # of passive images doesn't match." >&2
+ do_help
+ exit 1
+ fi
+
+ for (( i=1; i<=$NDOMAINS; i++ )); do
+ ID=`echo "$PASSIVE_DOMAINS" | awk -F"," '{print $'$i'}'`
+ FILE=`echo "$PASSIVE_IMAGES" | awk -F',' '{print $'$i'}'`
+ if test ! -f "$FILE"; then
+ echo "Image $FILE for passive domain $ID not found." >&2
+ return 1
+ fi
+ LNK_KERNEL=/boot/domain$ID-kernel
+ ln -sf $FILE $LNK_KERNEL
+ LNK_XEN=/boot/domain$ID-xen
+ ln -sf $XENIMAGE $LNK_XEN
+ set_passive_domain $ID $LNK_KERNEL $LNK_XEN
+ done
+ else
+ for (( i=1; i<=$NDOMAINS; i++ )); do
+ ID=`echo "$PASSIVE_DOMAINS" | awk -F"," '{print $'$i'}'`
+ LNK_XEN=/boot/domain$ID-xen
+ set_passive_domain $ID none $LNK_XEN
+ done
+
+ fi
+}
+
# validate --separate= parameters. This function is called with IFS=,
# so on each argument is splitted
@@ -825,6 +909,16 @@
ACTIVE_DOMAINS=$val
DO_SETUP=yes
;;
+ --passive-domains|--domains)
+ error_if_empty $arg $val
+ PASSIVE_DOMAINS=$val
+ DO_SETUP=yes
+ ;;
+ --passive-images|--domain-images)
+ error_if_empty $arg $val
+ PASSIVE_IMAGES=$val
+ DO_SETUP=yes
+ ;;
--note-table-size)
error_if_empty $arg $val
if test "$KERNEL_SUPPORT" = "yes"; then
@@ -897,6 +991,16 @@
exit 1
fi
fi
+
+ if test -n "$ACTIVE_DOMAINS" -a "$START_DAEMON" != "yes"; then
+ echo "Option \"--active-domains\" can only be used with option \"-start-daemon\"." >&2
+ exit 1
+ fi
+
+ if test -n "$PASSIVE_DOMAINS" -a "$START_DAEMON" != "yes" -a "$START" != "yes"; then
+ echo "Option \"--passive-domains\" or "--domains" can only be used with option \"--start-daemon\" or \"--start\"." >&2
+ exit 1
+ fi
}
@@ -1167,6 +1271,15 @@
fi
fi
+ if test -n "$PASSIVE_DOMAINS"; then
+ if test "$KERNEL_SUPPORT" = "yes"; then
+ echo $PASSIVE_DOMAINS >$MOUNT/passive_domains
+ set_passive_domain_config
+ else
+ echo "passive-domains not supported - ignored" >&2
+ fi
+ fi
+
if test $NOTE_SIZE != 0; then
set_param notesize $NOTE_SIZE
fi
@@ -1284,7 +1397,8 @@
fi
do_setup
- check_valid_args
+ check_valid_vmlinux
+ check_valid_xen
get_image_range "linux"
get_image_range "xen"
do_param_setup
@@ -1312,6 +1426,10 @@
OPD_ARGS="$OPD_ARGS --image=$IMAGE_FILTER"
fi
+ if ! test -z "$PASSIVE_DOMAINS"; then
+ OPD_ARGS="$OPD_ARGS --xen-passive-setup=$PASSIVE_SETUP_FILE"
+ fi
+
if test -n "$VERBOSE"; then
OPD_ARGS="$OPD_ARGS --verbose=$VERBOSE"
fi
@@ -1522,6 +1640,8 @@
move_and_remove $SAMPLES_DIR/current/{root}
hup_daemon
+
+ rm -f /boot/domain-*-kernel /boot/domain-*-xen
}
@@ -1552,7 +1672,8 @@
fi
if test "$SETUP" = "yes"; then
- check_valid_args
+ check_valid_vmlinux
+ check_valid_xen
do_save_setup
fi
oprofile-0.9.3-family10.patch:
--- NEW FILE oprofile-0.9.3-family10.patch ---
Index: events/x86-64/family10/events
===================================================================
RCS file: /cvsroot/oprofile/oprofile/events/x86-64/family10/events,v
retrieving revision 1.1
retrieving revision 1.2
diff -U2 -u -r1.1 -r1.2
--- events/x86-64/family10/events 23 Mar 2007 19:28:59 -0000 1.1
+++ events/x86-64/family10/events 17 Oct 2007 12:01:13 -0000 1.2
@@ -5,23 +5,39 @@
#
# Copyright (c) Advanced Micro Devices, 2006, 2007
-# Contributed by Ray Bryant <raybry at amd.com>, and others.
+# Contributed by Ray Bryant <raybry at amd.com>,
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
#
+
+# default event
event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
+
+# Floating point events
+event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
+event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_FPU_EMPTY : The number of cycles in which the PFU is empty
+event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : The number of FPU operations that use the fast flag interface
+event:0x03 counters:0,1,2,3 um:sse_ops minimum:500 name:RETIRED_SSE_OPS : The number of SSE ops or uops retired
+event:0x04 counters:0,1,2,3 um:move_ops minimum:500 name:RETIRED_MOVE_OPS : The number of move uops retired
+event:0x05 counters:0,1,2,3 um:serial_ops minimum:500 name:RETIRED_SERIALIZING_OPS : The number of serializing uops retired.
+event:0x06 counters:0,1,2,3 um:serial_ops_sched minimum:500 name:SERIAL_UOPS_IN_FP_SCHED : Number of cycles a serializing uop is in the FP scheduler
+
+# Load, Store, and TLB events
+event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
+event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
+event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
+event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 Full
+event:0x24 counters:0,1,2,3 um:lock_ops minimum:500 name:LOCKED_OPS : Locked operations
event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH : Retired CLFLUSH instructions
event:0x27 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID : Retired CPUID instructions
-event:0xc0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
-event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
-event:0x80 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction cache fetches (RevE)
-event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
+event:0x2a counters:0,1,2,3 um:store_to_load minimum:500 name:CANCELLED_STORE_TO_LOAD : Counts the number of cancelled store to load forward operations
+event:0x2b counters:0,1,2,3 um:zero minimum:500 name:SMIS_RECEIVED : Counts the number of SMI received
+
+# Data Cache event
event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
# Note: unit mask 0x01 counts same events as event select 0x43
-event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_SYSTEM : Data cache refills from L2 or system
-event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_SYSTEM : Data cache refills from system
-event:0x44 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_LINES_EVICTED : Data cache lines evicted
-event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
-event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired Mispredicted Branch Instructions
-event:0xc4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS : Retired taken branch instructions
-event:0xc5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED : Retired taken branches mispredicted
+event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE : Data cache refills from L2 or northbridge
+event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_NORTHBRIDGE : Data cache refills from northbridge
+event:0x44 counters:0,1,2,3 um:moesi_gh minimum:500 name:DATA_CACHE_LINES_EVICTED : Data cache lines evicted
event:0x45 counters:0,1,2,3 um:l1_dlb_miss_l2_hit minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
event:0x46 counters:0,1,2,3 um:l1_l2_dlb_miss minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
@@ -29,45 +45,45 @@
event:0x48 counters:0,1,2,3 um:zero minimum:500 name:MICRO_ARCH_LATE_CANCEL_ACCESS : Microarchitectural late cancel of an access
event:0x49 counters:0,1,2,3 um:zero minimum:500 name:MICRO_ARCH_EARLY_CANCEL_ACCESS : Microarchitectural early cancel of an access
-event:0x4a counters:0,1,2,3 um:ecc minimum:500 name:1_BIT_ECC_ERRORs : Single-bit ECC errors recorded by scrubber
+event:0x4a counters:0,1,2,3 um:ecc minimum:500 name:1_BIT_ECC_ERRORS : Single-bit ECC errors recorded by scrubber
event:0x4b counters:0,1,2,3 um:prefetch minimum:500 name:PREFETCH_INSTRUCTIONS_DISPATCHED : The number of prefetch instructions dispatched by the decoder
-event:0x4c counters:0,1,2,3 um:locked_instruction_dcache_miss minimum:500 name:LOCKED_INSTRUCTIONS_DCACHE_MISS : The number of dta cache misses by locked instructions.
-event:0x65 counters:0,1,2,3 um:memory_type_request minimum:500 name:NUMBER_OF_MEMORY_TYPE_REQUEST : Number of memory type requests
-event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB misses (and L2 ITLB hits)
-event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB Miss, L2 ITLB Miss
-event:0xc6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired far control transfers
-event:0xc7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_RESYNCS : Retired branches resyncs (only non-control transfer branches)
-event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
-event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
-event:0xcf counters:0,1,2,3 um:zero minimum:10 name:INTERRUPTS_TAKEN : Number of taken hardware interrupts
-event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
-event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired
-event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
-event:0x07 counters:0,1,2,3 um:control_modified minimum:500 name:CONTROL_MODIFIED : Number of times rounding control or precision control is modified
-event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
-event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
-event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
-event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 Full
-event:0x24 counters:0,1,2,3 um:lock_ops minimum:500 name:LOCKED_OPS : Locked operations
+event:0x4c counters:0,1,2,3 um:locked_instruction_dcache_miss minimum:500 name:LOCKED_INSTRUCTIONS_DCACHE_MISSES : The number of dta cache misses by locked instructions.
+event:0x4d counters:0,1,2,3 um:l1_dtlb_hit minimum:500 name:L1_DTLB_HIT : L1 DTLB hit
+event:0x52 counters:0,1,2,3 um:soft_prefetch minimum:500 name:INEFFECTIVE_SW_PREFETCHES : Number of software prefetches that did not fetch data outside of processor core
+event:0x54 counters:0,1,2,3 um:zero minimum:500 name:GLOBAL_TLB_FLUSHES : The number of global TLB flushes
+
+# L2 Cache and System Interface events
event:0x65 counters:0,1,2,3 um:memreqtype minimum:500 name:MEMORY_REQUESTS : Memory Requests by Type
event:0x67 counters:0,1,2,3 um:dataprefetch minimum:500 name:DATA_PREFETCHES : Data Prefetcher
-event:0x68 counters:0,1,2,3 um:mab_um minimum:500 name:MAB_REQUESTS : Number of L1 Cache misses handled by selected MAB
-event:0x69 counters:0,1,2,3 um:mab_um minimum:500 name:MAB_WAIT_CYCLES : Number of cycles spent waiting for the selected MAB
-event:0x6c counters:0,1,2,3 um:systemreadresponse minimum:500 name:SYSTEM_READ_RESPONSES : System Read Responses by Coherency State
-event:0x6d counters:0,1,2,3 um:quadword_transfer minimum:500 name:QUADWORD_WRITE_TRANSFERS : Quadwords Written to System
-event:0x6e counters:0,1,2,3 um:page_table_walker_1 minimum:500 name:PAGE_TABLE_WALKER_1 : Table walk accesses to the PDC and L2 cache on TLB refills
-event:0x6f counters:0,1,2,3 um:page_table_walker_2 minimum:500 name:PAGE_TABLE_WALKER_2 : Table walk accesses to the PDC and L2 cache on TLB refills
-event:0x73 counters:0,1,2,3 um:probe_hits_um minimum:500 name:Probe_Hits : Cache coherency probe hits by cache
-event:0x75 counters:0,1,2,3 um:cache_cross_invalidates_um minimum:500 name:Cache_Cross_Invalidates : IC or DC misses that hit in the DC or IC causing the line to be invalidated
-event:0x78 counters:0,1,2,3 um:tlb_flush minimum:500 name:TLB_FLUSH : TLB Flushes
+event:0x6c counters:0,1,2,3 um:systemreadresponse minimum:500 name:NORTHBRIDGE_READ_RESPONSES : Northbridge Read Responses by Coherency State
+event:0x6d counters:0,1,2,3 um:quadword_transfer minimum:500 name:OCTWORD_WRITE_TRANSFERS : Octwords Written to System
event:0x7d counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 Cache
event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 Cache Misses
event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 Fill/Writeback
+
+# Instruction Cache events
+event:0x80 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction cache fetches (RevE)
+event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
event:0x82 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_L2 : Instruction Cache Refills from L2
event:0x83 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM : Instruction Cache Refills from System
+event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB misses (and L2 ITLB hits)
+event:0x85 counters:0,1,2,3 um:l1_l2_itlb_miss minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB Miss, L2 ITLB Miss
event:0x86 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE : Pipeline Restart Due to Instruction Stream Probe
event:0x87 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCH_STALL : Instruction fetch stall
event:0x88 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_HITS : Return stack hit
event:0x89 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_OVERFLOWS : Return stack overflow
-event:0x8d counters:0,1,2,3 um:instr_fetch minimum:500 name:INSTRUCTION_FETCH_STALLS : Number of cycles the instruction fetch engine stalled
+event:0x8b counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_VICTIMS : Number of instruction cachelines evicticed to L2
+event:0x8c counters:0,1,2,3 um:icache_invalidated minimum:500 name:INSTRUCTION_CHCHE_INVALIDATED : Instruction cache lines invalidated
+event:0x99 counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS : The number of ITLB reloads requests
+event:0x9a counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS_ABORTED : The number of ITLB reloads aborted
+
+# Execution Unit events
+event:0xc0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
+event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
+event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
+event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired Mispredicted Branch Instructions
+event:0xc4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS : Retired taken branch instructions
+event:0xc5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED : Retired taken branches mispredicted
+event:0xc6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired far control transfers
+event:0xc7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_RESYNCS : Retired branches resyncs (only non-control transfer branches)
event:0xc8 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS : Retired near returns
event:0xc9 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS_MISPREDICTED : Retired near returns mispredicted
@@ -75,4 +91,7 @@
event:0xcb counters:0,1,2,3 um:fpu_instr minimum:500 name:RETIRED_MMX_FP_INSTRUCTIONS : Retired MMX/FP instructions
event:0xcc counters:0,1,2,3 um:fpu_fastpath minimum:500 name:RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS : Retired FastPath double-op instructions
+event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
+event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
+event:0xcf counters:0,1,2,3 um:zero minimum:10 name:INTERRUPTS_TAKEN : Number of taken hardware interrupts
event:0xd0 counters:0,1,2,3 um:zero minimum:500 name:DECODER_EMPTY : Nothing to dispatch (decoder empty)
event:0xd1 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALLS : Dispatch stalls
@@ -87,8 +106,10 @@
event:0xda counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC : Dispatch Stall for Far Transfer or Resync to Retire
event:0xdb counters:0,1,2,3 um:fpu_exceptions minimum:1 name:FPU_EXCEPTIONS : FPU exceptions
-event:0xdc counters:0,1,2,3 um:zero minimum:1 name:DR0_BREAKPOINTS : Number of breakpoints for DR0
-event:0xdd counters:0,1,2,3 um:zero minimum:1 name:DR1_BREAKPOINTS : Number of breakpoints for DR1
-event:0xde counters:0,1,2,3 um:zero minimum:1 name:DR2_BREAKPOINTS : Number of breakpoints for DR2
-event:0xdf counters:0,1,2,3 um:zero minimum:1 name:DR3_BREAKPOINTS : Number of breakpoints for DR3
+event:0xdc counters:0,1,2,3 um:zero minimum:1 name:DR0_BREAKPOINTS : The number of matches on the address in breakpoint register DR0
+event:0xdd counters:0,1,2,3 um:zero minimum:1 name:DR1_BREAKPOINTS : The number of matches on the address in breakpoint register DR1
+event:0xde counters:0,1,2,3 um:zero minimum:1 name:DR2_BREAKPOINTS : The number of matches on the address in breakpoint register DR2
+event:0xdf counters:0,1,2,3 um:zero minimum:1 name:DR3_BREAKPOINTS : The number of matches on the address in breakpoint register DR3
+
+# Memory Controler events
event:0xe0 counters:0,1,2,3 um:page_access minimum:500 name:DRAM_ACCESSES : DRAM Accesses
event:0xe1 counters:0,1,2,3 um:mem_page_overflow minimum:500 name:MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS : Memory controller page table overflows
@@ -96,25 +117,32 @@
event:0xe3 counters:0,1,2,3 um:turnaround minimum:500 name:MEMORY_CONTROLLER_TURNAROUNDS : Memory controller turnarounds
event:0xe4 counters:0,1,2,3 um:saturation minimum:500 name:MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION : Memory controller bypass saturation
-event:0xee counters:0,1,2,3 um:gart minimum:500 name:GART_EVENTS : GART Events
-event:0xe5 counters:0,1,2,3 um:cancel_requests minimum:500 name:MEMORY_CANCEL_REQUESTS : DRAM request cancellation activity, and sized read/write block sizes.
-event:0xe6 counters:0,1,2,3 um:write_combine minimum:500 name:MEMORY_CONTROLLER_WRITES_COMBINED : write-combining done by the memory controller
event:0xe8 counters:0,1,2,3 um:thermal_status minimum:500 name:THERMAL_STATUS : Thermal status
-event:0x1e8 counters:0,1,2,3 um:cpu_apic_2 minimum:500 name:CPU_REQUEST_APIC_2 : CPU requests to APIC
-event:0x1f0 counters:0,1,2,3 um:mem_control_request minimum:500 name:MEMORY_CONTROLLER_REQUESTS : Sized Read/Write activity.
event:0xe9 counters:0,1,2,3 um:cpiorequests minimum:500 name:CPU_IO_REQUESTS_TO_MEMORY_IO : CPU/IO Requests to Memory/IO (RevE)
event:0xea counters:0,1,2,3 um:cacheblock minimum:500 name:CACHE_BLOCK_COMMANDS : Cache Block Commands (RevE)
event:0xeb counters:0,1,2,3 um:sizecmds minimum:500 name:SIZED_COMMANDS : Sized Commands
event:0xec counters:0,1,2,3 um:probe minimum:500 name:PROBE_RESPONSES_AND_UPSTREAM_REQUESTS : Probe Responses and Upstream Requests
-event:0xef counters:0,1,2,3 um:srifull_cycles_1 minimum:500 name:SRI_TO_XBAR_BUFFER_FULL_CYCLES_1 : SRI-to-Crossbar full cycles
-event:0xf3 counters:0,1,2,3 um:srifull_cycles_2 minimum:500 name:SRI_TO_XBAR_BUFFER_FULL_CYCLES_2 : SRI-to-Crossbar full cycles
-event:0xf4 counters:0,1,2,3 um:xbarfull_cycles minimum:500 name:XBAR_TO_MCT_BUFFER_FULL_CYCLES : Crossbar to MCT buffer full cycles
-event:0xf5 counters:0,1,2,3 um:mctfull_cycles minimum:500 name:MCT_TO_XBAR_BUFFER_FULL_CYCLES : MCT to Crossbar buffer full cycles
-event:0xf0 counters:0,1,2,3 um:htfull minimum:500 name:HYPERTRANSPORT_LINK0_FULL_CYCLES : HyperTransport(tm) link 0 buffer full cycles
-event:0xf1 counters:0,1,2,3 um:htfull minimum:500 name:HYPERTRANSPORT_LINK1_FULL_CYCLES : HyperTransport(tm) link 0 buffer full cycles
-event:0xf2 counters:0,1,2,3 um:htfull minimum:500 name:HYPERTRANSPORT_LINK2_FULL_CYCLES : HyperTransport(tm) link 0 buffer full cycles
-event:0xf3 counters:0,1,2,3 um:htfull minimum:500 name:HYPERTRANSPORT_LINK3_FULL_CYCLES : HyperTransport(tm) link 0 buffer full cycles
+event:0xee counters:0,1,2,3 um:gart minimum:500 name:GART_EVENTS : GART Events
+event:0x1f0 counters:0,1,2,3 um:mem_control_request minimum:500 name:MEMORY_CONTROLLER_REQUESTS : Sized Read/Write activity.
+
+# Crossbar events
+event:0x1e0 counters:0,1,2,3 um:cpu_dram_req minimum:500 name:CPU_DRAM_REQUEST_TO_NODE : CPU to DRAM requests to target node
+event:0x1e1 counters:0,1,2,3 um:io_dram_req minimum:500 name:IO_DRAM_REQUEST_TO_NODE : IO to DRAM requests to target node
+event:0x1e2 counters:0,1,2,3 um:cpu_read_lat_0_3 minimum:500 name:CPU_READ_COMMAND_LATENCY_NODE_0_3 : Latency between the local node and remote node
+event:0x1e3 counters:0,1,2,3 um:cpu_read_lat_0_3 minimum:500 name:CPU_READ_COMMAND_REQUEST_NODE_0_3 : Number of requests that a latency measurment is made for Event 0x1E2
+event:0x1e4 counters:0,1,2,3 um:cpu_read_lat_4_7 minimum:500 name:CPU_READ_COMMAND_LATENCY_NODE_4_7 : Latency between the local node and remote node
+event:0x1e5 counters:0,1,2,3 um:cpu_read_lat_4_7 minimum:500 name:CPU_READ_COMMAND_REQUEST_NODE_4_7 : Number of requests that a latency measurment is made for Event 0x1E2
+event:0x1e6 counters:0,1,2,3 um:cpu_comm_lat minimum:500 name:CPU_COMMAND_LATENCY_TARGET : Determine latency between the local node and a remote node.
+event:0x1e7 counters:0,1,2,3 um:cpu_comm_lat minimum:500 name:CPU_REQUEST_TARGET : Number of requests that a latency measurement is made for Event 0x1E6
+
+# Link events
event:0xf6 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
-event:0xf7 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
-event:0xf8 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
-event:0x1f9 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
+event:0xf7 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 1 transmit bandwidth
+event:0xf8 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 2 transmit bandwidth
+event:0x1f9 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 3 transmit bandwidth
+
+# L3 Cache events
+event:0x4e0 counters:0,1,2,3 um:l3_cache minimum:500 name:READ_REQUEST_L3_CACHE : Tracks the red requests from each core to L3 cache
+event:0x4e1 counters:0,1,2,3 um:l3_cache minimum:500 name:L3_CACHE_MISSES : Tracks the L3 cache misses from each core
+event:0x4e2 counters:0,1,2,3 um:l3_fill minimum:500 name:L3_FILLS_CAUSED_BY_L2_EVICTIONS : Tracks the L3 fills caused by L2 evictions per core
+event:0x4e3 counters:0,1,2,3 um:l3_evict minimum:500 name:L3_EVICTIONS : Tracks the state of the L3 line when it was evicted
Index: events/x86-64/family10/unit_masks
===================================================================
RCS file: /cvsroot/oprofile/oprofile/events/x86-64/family10/unit_masks,v
retrieving revision 1.1
retrieving revision 1.2
diff -U2 -u -r1.1 -r1.2
--- events/x86-64/family10/unit_masks 23 Mar 2007 19:28:59 -0000 1.1
+++ events/x86-64/family10/unit_masks 17 Oct 2007 12:01:13 -0000 1.2
@@ -4,5 +4,7 @@
# Copyright OProfile authors
# Copyright (c) Advanced Micro Devices, 2006.
-# Contributed by Ray Bryant <raybry at amd.com>, and others.
+# Contributed by Ray Bryant <raybry at amd.com>
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
#
name:zero type:mandatory default:0x0
@@ -16,21 +18,18 @@
0x1f All cache states
name:moess type:bitmask default:0x1e
- 0x10 (M)odified cache state
- 0x08 (O)wner cache state
- 0x04 (E)xclusive cache state
- 0x02 (S)hared cache state
- 0x01 refill from system
- 0x1e All cache states except Invalid
+ 0x01 Refill from northbridge
+ 0x02 Shared-state line from L2
+ 0x04 Exclusive-state line from L2
+ 0x08 Owner-state line from L2
+ 0x10 Modified-state line from L2
+ 0x1e All cache states except refill from northbridge
name:fpu_ops type:bitmask default:0x3f
- 0x01 Add pipe ops
- 0x02 Multiply pipe
- 0x04 Store pipe ops
- 0x08 Add pipe load ops
- 0x10 Multiply pipe load ops
- 0x20 Store pipe load ops
-name:control_modified type:bitmask default:0x0d
- 0x01 Number of times SSE rounding control is changed
- 0x04 Number of times x87 rounding control is changed
- 0x08 Number of times x87 precision control is changed
+ 0x01 Add pipe ops excluding load ops and SSE move ops
+ 0x02 Multiply pipe ops excluding load ops and SSE move ops
+ 0x04 Store pipe ops excluding load ops and SSE move ops
+ 0x08 Add pipe load ops and SSE move ops
+ 0x10 Multiply pipe load ops and SSE move ops
+ 0x20 Store pipe load ops and SSE move ops
+ 0x3F all ops
name:segregload type:bitmask default:0x7f
0x01 ES register
@@ -41,9 +40,8 @@
0x20 GS register
0x40 HS register
-name:fpu_instr type:bitmask default:0x0f
+name:fpu_instr type:bitmask default:0x07
0x01 x87 instructions
- 0x02 Combined MMX & 3DNow instructions
- 0x04 Combined packed SSE & SSE2 instructions
- 0x08 Combined packed scalar SSE & SSE2 instructions
+ 0x02 MMX & 3DNow instructions
+ 0x04 SSE & SSE2 instructions
name:fpu_fastpath type:bitmask default:0x07
0x01 With low op in position 0
@@ -55,5 +53,5 @@
0x04 SSE reclass microfaults
0x08 SSE and x87 microtraps
-name:page_access type:bitmask default:0x07
+name:page_access type:bitmask default:0xff
0x01 DCT0 Page hit
0x02 DCT0 Page miss
@@ -68,13 +66,13 @@
0x02 DCT1 Page Table Overflow
name:turnaround type:bitmask default:0x3f
- 0x01 DCT0 DIMM turnaround
+ 0x01 DCT0 DIMM (chip select) turnaround
0x02 DCT0 Read to write turnaround
0x04 DCT0 Write to read turnaround
- 0x08 DCT1 DIMM turnaround
+ 0x08 DCT1 DIMM (chip select) turnaround
0x10 DCT1 Read to write turnaround
0x20 DCT1 Write to read turnaround
name:saturation type:bitmask default:0x0f
0x01 Memory controller high priority bypass
- 0x02 Memory controller low priority bypass
+ 0x02 Memory controller medium priority bypass
0x04 DCT0 DCQ bypass
0x08 DCT1 DCQ bypass
@@ -82,16 +80,14 @@
0x01 DCT0 Command slots missed
0x02 DCT2 Command slots missed
- 0x04 DRAM controller interface bypass
- 0x08 DRAM controller queue bypass
name:sizecmds type:bitmask default:0x3f
- 0x01 non-posted write byte
- 0x02 non-posted write dword
- 0x04 posted write byte
- 0x08 posted write dword
+ 0x01 non-posted write byte (1-32 bytes)
+ 0x02 non-posted write dword (1-16 dwords)
+ 0x04 posted write byte (1-32 bytes)
+ 0x08 posted write dword (1-16 dwords)
0x10 read byte (4 bytes)
0x20 read dword (1-16 dwords)
name:probe type:bitmask default:0xff
0x01 Probe miss
- 0x02 Probe hit
+ 0x02 Probe hit clean
0x04 Probe hit dirty without memory cancel
0x08 Probe hit dirty with memory cancel
@@ -100,17 +96,19 @@
0x40 Upstream ISOC writes
0x80 Upstream non-ISOC writes
-name:l2_internal type:bitmask default:0x1f
+name:l2_internal type:bitmask default:0x3f
0x01 IC fill
0x02 DC fill
- 0x04 TLB reload
+ 0x04 TLB fill (page table walks)
0x08 Tag snoop request
0x10 Canceled request
-name:l2_req_miss type:bitmask default:0x07
+ 0x20 Hardware prefetch from data cache
+name:l2_req_miss type:bitmask default:0x0f
0x01 IC fill
- 0x02 DC fill
- 0x04 TLB reload
+ 0x02 DC fill (includes possible replays)
+ 0x04 TLB page table walk
+ 0x08 Hardwareprefetch from data cache
name:l2_fill type:bitmask default:0x03
- 0x01 Dirty L2 victim
- 0x02 Victim from L1
+ 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
+ 0x02 L2 Writebacks to system
name:gart type:bitmask default:0xff
0x01 GART aperture hit on access from CPU
@@ -148,42 +146,11 @@
0x04 Shared
0x10 Data Error
-name:mab_um type:exclusive default:0x09
- 0x01 Buffer 1
- 0x02 Buffer 2
- 0x03 Buffer 3
- 0x04 Buffer 4
- 0x05 Buffer 5
- 0x06 Buffer 6
- 0x07 Buffer 7
- 0x08 Buffer 8
- 0x09 Buffer 9
-name:page_table_walker_1 type:bitmask default:0x41
- 0x01 PDE refill hit in L2 cache
- 0x04 PDPE lookup misses in PDC
- 0x10 PML4E refill hit in L2 cache
- 0x40 PML4E lookup missed in PDC
-name:page_table_walker_2 type:bitmask default:0xd1
- 0x01 PTE refil hit in L2 cache
- 0x10 PDE refill hit in L2 cache
- 0x40 PDE lookup missed in PDC
- 0x80 PDE lookup in PDC
-name:probe_hits_um type:bitmask default:0x03
- 0x01 Probe hit Icache
- 0x02 Probe hit Dcache
-name:cache_cross_invalidates_um type:bitmask default:0x0f
- 0x01 DC Invalidates IC, modification of cached instructions, data too close to code
- 0x02 DC Invalidates DC, aliasing
- 0x04 IC Invalidates IC, aliasing
- 0x08 IC Invalidates DC, execution of recently modified code, modified data too close to code
-name:tlb_flush type:bitmask default:0x03
- 0x01 Actual TLB flushes
- 0x02 TLB flush requests
name:l1_dlb_miss_l2_hit type:bitmask default:0x03
0x01 L2 4K TLB hit
0x02 L2 2M TLB hit
-name:l1_l2_dlb_miss type:bitmask default:0x43
+name:l1_l2_dlb_miss type:bitmask default:0x07
0x01 4K TLB reload
0x02 2M TLB reload
- 0x40 1G TLB reload
+ 0x04 1G TLB reload
name:ecc type:bitmask default:0x0f
0x01 Scrubber error
@@ -199,10 +166,4 @@
name:quadword_transfer type:bitmask default:0x01
0x01 Quadword write transfer
-name:cancel_requests type:bitmask default:0x03
- 0x01 Total MemCancels seen
- 0x02 Read responses successfully canceled
-name:write_combine type:bitmask default:0x03
- 0x01 Sized Writes not combined
- 0x02 Sized writes combined
name:thermal_status type:bitmask default:0x7c
0x04 Number of times the HTC trip point is crossed
@@ -212,66 +173,140 @@
0x40 Number of clocks HTC P-state is active
name:mem_control_request type:bitmask default:0x78
+ 0x01 Write requests
+ 0x02 Read Requests including Prefetch
+ 0x04 Prefetch Request
0x08 32 Bytes Sized Writes
0x10 64 Bytes Sized Writes
0x20 32 Bytes Sized Reads
0x40 64 Byte Sized Reads
-name:srifull_cycles_1 type:bitmask default:0x5f
- 0x01 Request
- 0x02 Posted request
- 0x04 Response
- 0x08 Display refresh
- 0x10 Request data
- 0x40 Response data
-name:srifull_cycles_2 type:bitmask default:0x3f
- 0x01 Upstream request
- 0x02 Upstream posted request
- 0x04 Display refresh
- 0x08 Probe
- 0x10 Downstream request
- 0x20 Downstream posted request
-name:xbarfull_cycles type:bitmask default:0x15
- 0x01 Request
- 0x04 Display Refresh
- 0x10 Request data
-name:mctfull_cycles type:bitmask default:0x4c
- 0x04 Response
- 0x08 Probe
- 0x40 Response data
-name:htfull type:bitmask default:0xdf
- 0x01 Request buffer
- 0x02 Posted request buffer
- 0x04 Response buffer
- 0x08 Probe buffer
- 0x10 Request/posted request data buffer
- 0x40 Response data buffer
- 0x80 Sublink Mask
+ 0x80 Read Requests while writes pending in DCQ
name:httransmit type:bitmask default:0xbf
0x01 Command DWORD sent
- 0x02 Address extension DWORD sent
- 0x04 Data DWORD sent
- 0x08 Buffer release DWORD sent
- 0x10 Nop DW send, idle
+ 0x02 DWORD sent
+ 0x04 Buffer release DWORD sent
+ 0x08 Nop DW sent (idle)
+ 0x10 Address extension DWORD sent
0x20 Per packet CRC sent
0x80 SubLink Mask
-name:memory_type_request type:bitmask default:0xf3
- 0x01 UC
- 0x02 WC
- 0x10 WT
- 0x20 WP
- 0x40 WB
- 0x80 Streaming store
-name:instr_fetch type:bitmask default:0x0f
- 0x01 All stalls except stalls specified the other three unitmasks
- 0x02 Stalls caused when a branch is written to the branch array
- 0x04 Stalls caused when the branch array is full
- 0x08 Stalls caused when the instruction buffer is full
-name:cpu_apic_2 type:bitmask default:0x0f
- 0x01 Local APIC reads
- 0x02 Local APIC writes
- 0x04 APIC TPR writes
- 0x08 Fast APIC TPR writes
-name:lock_ops type:bitmask default:0x07
+name:lock_ops type:bitmask default:0x0f
0x01 Number of locked instructions executed
0x02 Cycles in speculative phase
- 0x04 Cycles in non-speculative phase
-
+ 0x04 Cycles in non-speculative phase (including cache miss penalty)
+ 0x08 Cache miss penalty in cycles
+name:sse_ops type:bitmask default:0x7f
+ 0x01 Single Precision add/subtract ops
+ 0x02 Single precision multiply ops
+ 0x04 Single precision divide/square root ops
+ 0x08 Double precision add/subtract ops
+ 0x10 Double precision multiply ops
+ 0x20 Double precision divide/square root ops
+ 0x40 OP type, 0=uops 1=FLOPS
+name:move_ops type:bitmask default:0x0f
+ 0x01 Merging low quadword move uops
+ 0x02 Merging high quadword move uops
+ 0x04 All other merging move uops
+ 0x08 All other move uops
+name:serial_ops type:bitmask default:0x0f
+ 0x01 SSE bottom-executing uops retired
+ 0x02 SSE bottom-serializing uops retired
+ 0x04 x87 bottom-executing uops retired
+ 0x08 x87 bottom-serializing uops retired
+name:serial_ops_sched type:bitmask default:0x03
+ 0x01 Number of cycles a bottom-execute uops in FP scheduler
+ 0x02 Number of cycles a bottom-serializing uops in FP scheduler
+name:store_to_load type:bitmask default:0x07
+ 0x01 Address mismatches (starting byte not the same)
+ 0x02 Store is smaller than load
+ 0x04 Misaligned
+name:moesi_gh type:bitmask default:0x1f
+ 0x01 (I)nvalid cache state
+ 0x02 (S)hared cache state
+ 0x04 (E)xclusive cache state
+ 0x08 (O)wner cache state
+ 0x10 (M)odified cache state
+ 0x20 Cache line evict brought by PrefetchNTA
+ 0x40 Cache line evict not brought by PrefetchNTA
+ 0x1f All cache states except PrefetchNTA
+name:l1_dtlb_hit type:bitmask default:0x07
+ 0x01 L1 4K TLB hit
+ 0x02 L1 2M TLB hit
+ 0x04 L1 1G TLB hit
+name:soft_prefetch type:bitmask default:0x09
+ 0x01 Hit in L1
+ 0x08 Hit in L2
+name:l1_l2_itlb_miss type:bitmask default:0x03
+ 0x01 Instruction fetches to 4K pages
+ 0x02 Instruction fetches to 2M pages
+name:cpu_dram_req type:bitmask default:0xff
+ 0x01 From local node to node 0
+ 0x02 From local node to node 1
+ 0x04 From local node to node 2
+ 0x08 From local node to node 3
+ 0x10 From local node to node 4
+ 0x20 From local node to node 5
+ 0x40 From local node to node 6
+ 0x80 From local node to node 7
+name:io_dram_req type:bitmask default:0xff
+ 0x01 From local node to node 0
+ 0x02 From local node to node 1
+ 0x04 From local node to node 2
+ 0x08 From local node to node 3
+ 0x10 From local node to node 4
+ 0x20 From local node to node 5
+ 0x40 From local node to node 6
+ 0x80 From local node to node 7
+name:cpu_read_lat_0_3 type:bitmask default:0xff
+ 0x01 Read block
+ 0x02 Read block shared
+ 0x04 Read block modified
+ 0x08 Change to dirty
+ 0x10 From local node to node 0
+ 0x20 From local node to node 1
+ 0x40 From local node to node 2
+ 0x80 From local node to node 3
+name:cpu_read_lat_4_7 type:bitmask default:0xff
+ 0x01 Read block
+ 0x02 Read block shared
+ 0x04 Read block modified
+ 0x08 Change to dirty
+ 0x10 From local node to node 4
+ 0x20 From local node to node 5
+ 0x40 From local node to node 6
+ 0x80 From local node to node 7
+name:cpu_comm_lat type:bitmask default:0xf7
+ 0x01 Read sized
+ 0x02 Write sized
+ 0x04 Victim block
+ 0x08 Node group select. 0=Nodes 0-3. 1=Nodes 4-7
+ 0x10 From local node to node 0/4
+ 0x20 From local node to node 1/5
+ 0x40 From local node to node 2/6
+ 0x80 From local node to node 3/7
+name:l3_cache type:bitmask default:0xf7
+ 0x01 Read Block Exclusive (Data cache read)
+ 0x02 Read Block Shared (Instruciton cache read)
+ 0x04 Read Block Modify
+ 0x10 Core 0 Select
+ 0x20 Core 1 Select
+ 0x40 Core 2 Select
+ 0x80 Core 3 Select
+name:l3_fill type:bitmask default:0xff
+ 0x01 Shared
+ 0x02 Exclusive
+ 0x04 Owned
+ 0x08 Modified
+ 0x10 Core 0 Select
+ 0x20 Core 1 Select
+ 0x40 Core 2 Select
+ 0x80 Core 3 Select
+name:l3_evict type:bitmask default:0x0f
+ 0x01 Shared
+ 0x02 Exclusive
+ 0x04 Owned
+ 0x08 Modified
+name:icache_invalidated type:bitmask default:0x0f
+ 0x01 Invalidating probe that did not hit any in-flight instructions
+ 0x02 Invalidating probe that hit one or more in-flight instructions
+ 0x04 SMC that did not hit any in-flight instructions
+ 0x08 SMC that hit one or more in-flight instructions
+
oprofile-0.9.3-ranges.patch:
--- NEW FILE oprofile-0.9.3-ranges.patch ---
Index: utils/opcontrol
===================================================================
RCS file: /cvsroot/oprofile/oprofile/utils/opcontrol,v
retrieving revision 1.139
retrieving revision 1.140
diff -U2 -u -r1.139 -r1.140
--- utils/opcontrol 13 Jun 2007 15:04:13 -0000 1.139
+++ utils/opcontrol 25 Sep 2007 17:24:32 -0000 1.140
@@ -490,9 +490,8 @@
fi
- # start at the start of .text and then continue to the end
+ # start at the start of .text, and end at _etext
range_info=`objdump -h $FILE_IMAGE 2>/dev/null | grep " .text "`
- tmp1=`echo $range_info | awk '{print $4}'`
- tmp_length=`echo $range_info | awk '{print $3}'`
- tmp2=`objdump -h $FILE_IMAGE --adjust-vma=0x$tmp_length 2>/dev/null | grep " .text " | awk '{print $4}'`
+ tmp1=`echo $range_info | awk '{print $4}'`
+ tmp2=`objdump -t $FILE_IMAGE 2>/dev/null | grep "_etext$" | awk '{ print $1 }'`
if test -z "$tmp1" -o -z "$tmp2"; then
oprofile-0.9.3-970MP.patch:
--- NEW FILE oprofile-0.9.3-970MP.patch ---
diff -paurN oprofile-0.9.2/events/ppc64/970MP/event_mappings oprofile-0.9.2+lost-samples-fixes/events/ppc64/970MP/event_mappings
--- oprofile-0.9.2/events/ppc64/970MP/event_mappings 2007-10-11 07:24:18.000000000 -0700
+++ oprofile-0.9.2+lost-samples-fixes/events/ppc64/970MP/event_mappings 2007-10-11 07:35:09.000000000 -0700
@@ -1,539 +1,519 @@
#
# Copyright OProfile authors
-# Copyright (c) International Business Machines, 2006.
+# Copyright (c) International Business Machines, 2007.
# Contributed by Dave Nomura <dcnltc at us.ibm.com>.
#
#Mapping of event groups to MMCR values
#Group Default
-event:0X001 mmcr0:0X0400C51E mmcr1:0X000000000A46F18C mmcra:0X00002001
+event:0X001 mmcr0:0X0400C51F mmcr1:0X000000000A46F18C mmcra:0X00002001
#Group 1 pm_slice0, Time Slice 0
-event:0X0010 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000
-event:0X0011 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000
-event:0X0012 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000
-event:0X0013 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000
-event:0X0014 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000
-event:0X0015 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000
-event:0X0016 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000
-event:0X0017 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0010 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0011 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0012 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0013 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0014 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0015 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0016 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0017 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
#Group 2 pm_eprof, Group for use with eprof
-event:0X0020 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0021 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0022 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0023 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0024 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0025 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0026 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0027 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0020 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0021 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0022 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0023 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0024 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0025 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0026 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0027 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
#Group 3 pm_basic, Basic performance indicators
-event:0X0030 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0031 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0032 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0033 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0034 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0035 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0036 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000
-event:0X0037 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0030 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0031 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0032 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0033 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0034 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0035 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0036 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0037 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
#Group 4 pm_lsu, Information on the Load Store Unit
-event:0X0040 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000
-event:0X0041 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000
-event:0X0042 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000
-event:0X0043 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000
-event:0X0044 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000
-event:0X0045 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000
-event:0X0046 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000
-event:0X0047 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0040 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0041 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0042 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0043 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0044 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0045 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0046 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0047 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
#Group 5 pm_fpu1, Floating Point events
-event:0X0050 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000
-event:0X0051 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000
-event:0X0052 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000
-event:0X0053 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000
-event:0X0054 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000
-event:0X0055 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000
-event:0X0056 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000
-event:0X0057 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0050 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0051 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0052 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0053 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0054 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0055 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0056 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0057 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
#Group 6 pm_fpu2, Floating Point events
-event:0X0060 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000
-event:0X0061 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000
-event:0X0062 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000
-event:0X0063 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000
-event:0X0064 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000
-event:0X0065 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000
-event:0X0066 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000
-event:0X0067 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0060 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0061 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0062 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0063 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0064 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0065 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0066 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0067 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
#Group 7 pm_isu_rename, ISU Rename Pool Events
-event:0X0070 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000
-event:0X0071 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000
-event:0X0072 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000
-event:0X0073 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000
-event:0X0074 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000
-event:0X0075 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000
-event:0X0076 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000
-event:0X0077 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0070 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0071 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0072 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0073 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0074 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0075 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0076 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0077 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
#Group 8 pm_isu_queues1, ISU Rename Pool Events
-event:0X0080 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000
-event:0X0081 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000
-event:0X0082 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000
-event:0X0083 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000
-event:0X0084 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000
-event:0X0085 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000
-event:0X0086 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000
-event:0X0087 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0080 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0081 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0082 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0083 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0084 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0085 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0086 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0087 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
#Group 9 pm_isu_flow, ISU Instruction Flow Events
-event:0X0090 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
-event:0X0091 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
-event:0X0092 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
-event:0X0093 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
-event:0X0094 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
-event:0X0095 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
-event:0X0096 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
-event:0X0097 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0090 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0091 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0092 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0093 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0094 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0095 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0096 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0097 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
#Group 10 pm_isu_work, ISU Indicators of Work Blockage
-event:0X00A0 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
-event:0X00A1 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
-event:0X00A2 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
-event:0X00A3 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
-event:0X00A4 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
-event:0X00A5 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
-event:0X00A6 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
-event:0X00A7 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A0 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A1 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A2 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A3 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A4 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A5 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A6 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A7 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
#Group 11 pm_fpu3, Floating Point events by unit
-event:0X00B0 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000
-event:0X00B1 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000
-event:0X00B2 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000
-event:0X00B3 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000
-event:0X00B4 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000
-event:0X00B5 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000
-event:0X00B6 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000
-event:0X00B7 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B0 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B1 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B2 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B3 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B4 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B5 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B6 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B7 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
#Group 12 pm_fpu4, Floating Point events by unit
-event:0X00C0 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000
-event:0X00C1 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000
-event:0X00C2 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000
-event:0X00C3 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000
-event:0X00C4 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000
-event:0X00C5 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000
-event:0X00C6 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000
-event:0X00C7 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C0 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C1 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C2 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C3 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C4 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C5 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C6 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C7 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
#Group 13 pm_fpu5, Floating Point events by unit
-event:0X00D0 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000
-event:0X00D1 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000
-event:0X00D2 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000
-event:0X00D3 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000
-event:0X00D4 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000
-event:0X00D5 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000
-event:0X00D6 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000
-event:0X00D7 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D0 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D1 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D2 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D3 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D4 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D5 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D6 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D7 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
#Group 14 pm_fpu7, Floating Point events by unit
-event:0X00E0 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
-event:0X00E1 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
-event:0X00E2 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
-event:0X00E3 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
-event:0X00E4 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
-event:0X00E5 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
-event:0X00E6 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
-event:0X00E7 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E0 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E1 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E2 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E3 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E4 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E5 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E6 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E7 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
#Group 15 pm_lsu_flush, LSU Flush Events
-event:0X00F0 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000
-event:0X00F1 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000
-event:0X00F2 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000
-event:0X00F3 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000
-event:0X00F4 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000
-event:0X00F5 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000
-event:0X00F6 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000
-event:0X00F7 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F0 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F1 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F2 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F3 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F4 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F5 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F6 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F7 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
#Group 16 pm_lsu_load1, LSU Load Events
-event:0X0100 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000
-event:0X0101 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000
-event:0X0102 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000
-event:0X0103 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000
-event:0X0104 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000
-event:0X0105 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000
-event:0X0106 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000
-event:0X0107 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0100 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0101 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0102 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0103 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0104 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0105 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0106 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0107 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
#Group 17 pm_lsu_store1, LSU Store Events
-event:0X0110 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000
-event:0X0111 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000
-event:0X0112 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000
-event:0X0113 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000
-event:0X0114 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000
-event:0X0115 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000
-event:0X0116 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000
-event:0X0117 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0110 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0111 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0112 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0113 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0114 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0115 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0116 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0117 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
#Group 18 pm_lsu_store2, LSU Store Events
-event:0X0120 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
-event:0X0121 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
-event:0X0122 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
-event:0X0123 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
-event:0X0124 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
-event:0X0125 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
-event:0X0126 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
-event:0X0127 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0120 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0121 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0122 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0123 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0124 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0125 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0126 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0127 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
#Group 19 pm_lsu7, Information on the Load Store Unit
-event:0X0130 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000
-event:0X0131 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000
-event:0X0132 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000
-event:0X0133 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000
-event:0X0134 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000
-event:0X0135 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000
-event:0X0136 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000
-event:0X0137 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0130 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0131 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0132 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0133 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0134 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0135 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0136 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0137 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
#Group 20 pm_misc, Misc Events for testing
-event:0X0140 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000
-event:0X0141 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000
-event:0X0142 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000
-event:0X0143 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000
-event:0X0144 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000
-event:0X0145 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000
-event:0X0146 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000
-event:0X0147 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0140 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0141 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0142 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0143 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0144 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0145 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0146 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0147 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
#Group 21 pm_pe_bench1, PE Benchmarker group for FP analysis
-event:0X0150 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000
-event:0X0151 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000
-event:0X0152 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000
-event:0X0153 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000
-event:0X0154 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000
-event:0X0155 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000
-event:0X0156 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000
-event:0X0157 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0150 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0151 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0152 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0153 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0154 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0155 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0156 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0157 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
#Group 22 pm_pe_bench4, PE Benchmarker group for L1 and TLB
-event:0X0160 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0161 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0162 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0163 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0164 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0165 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0166 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0167 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0160 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0161 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0162 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0163 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0164 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0165 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0166 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0167 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
#Group 23 pm_hpmcount1, Hpmcount group for L1 and TLB behavior
-event:0X0170 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0171 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0172 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0173 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0174 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0175 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0176 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000
-event:0X0177 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0170 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0171 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0172 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0173 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0174 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0175 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0176 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0177 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
#Group 24 pm_hpmcount2, Hpmcount group for computation
-event:0X0180 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000
-event:0X0181 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000
-event:0X0182 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000
-event:0X0183 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000
-event:0X0184 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000
-event:0X0185 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000
-event:0X0186 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000
-event:0X0187 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0180 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0181 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0182 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0183 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0184 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0185 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0186 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0187 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
#Group 25 pm_l1andbr, L1 misses and branch misspredict analysis
-event:0X0190 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
-event:0X0191 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
-event:0X0192 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
-event:0X0193 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
-event:0X0194 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
-event:0X0195 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
-event:0X0196 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
-event:0X0197 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0190 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0191 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0192 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0193 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0194 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0195 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0196 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0197 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
#Group 26 pm_imix, Instruction mix: loads, stores and branches
-event:0X01A0 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000
-event:0X01A1 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000
-event:0X01A2 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000
-event:0X01A3 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000
-event:0X01A4 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000
-event:0X01A5 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000
-event:0X01A6 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000
-event:0X01A7 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A0 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A1 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A2 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A3 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A4 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A5 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A6 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A7 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
#Group 27 pm_branch, SLB and branch misspredict analysis
-event:0X01B0 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
-event:0X01B1 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
-event:0X01B2 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
-event:0X01B3 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
-event:0X01B4 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
-event:0X01B5 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
-event:0X01B6 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
-event:0X01B7 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B0 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B1 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B2 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B3 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B4 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B5 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B6 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B7 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
#Group 28 pm_data, data source and LMQ
-event:0X01C0 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000
-event:0X01C1 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000
-event:0X01C2 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000
-event:0X01C3 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000
-event:0X01C4 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000
-event:0X01C5 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000
-event:0X01C6 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000
-event:0X01C7 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002000
+event:0X01C0 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C1 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C2 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C3 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C4 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C5 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C6 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C7 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
#Group 29 pm_tlb, TLB and LRQ plus data prefetch
-event:0X01D0 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
-event:0X01D1 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
-event:0X01D2 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
-event:0X01D3 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
-event:0X01D4 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
-event:0X01D5 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
-event:0X01D6 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
-event:0X01D7 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D0 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D1 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D2 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D3 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D4 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D5 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D6 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D7 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
#Group 30 pm_isource, inst source and tablewalk
-event:0X01E0 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
-event:0X01E1 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
-event:0X01E2 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
-event:0X01E3 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
-event:0X01E4 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
-event:0X01E5 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
-event:0X01E6 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
-event:0X01E7 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E0 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E1 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E2 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E3 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E4 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E5 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E6 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E7 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
#Group 31 pm_sync, Sync and SRQ
-event:0X01F0 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000
-event:0X01F1 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000
-event:0X01F2 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000
-event:0X01F3 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000
-event:0X01F4 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000
-event:0X01F5 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000
-event:0X01F6 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000
-event:0X01F7 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F0 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F1 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F2 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F3 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F4 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F5 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F6 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F7 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
#Group 32 pm_ierat, IERAT
-event:0X0200 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
-event:0X0201 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
-event:0X0202 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
-event:0X0203 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
-event:0X0204 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
-event:0X0205 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
-event:0X0206 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
-event:0X0207 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0200 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0201 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0202 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0203 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0204 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0205 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0206 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0207 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
#Group 33 pm_derat, DERAT
-event:0X0210 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000
-event:0X0211 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000
-event:0X0212 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000
-event:0X0213 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000
-event:0X0214 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000
-event:0X0215 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000
-event:0X0216 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000
-event:0X0217 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0210 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0211 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0212 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0213 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0214 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0215 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0216 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0217 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
#Group 34 pm_mark1, Information on marked instructions
-event:0X0220 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
-event:0X0221 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
-event:0X0222 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
-event:0X0223 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
-event:0X0224 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
-event:0X0225 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
-event:0X0226 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
-event:0X0227 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0220 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0221 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0222 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0223 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0224 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0225 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0226 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0227 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
#Group 35 pm_mark2, Marked Instructions Processing Flow
-event:0X0230 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
-event:0X0231 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
-event:0X0232 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
-event:0X0233 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
-event:0X0234 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
-event:0X0235 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
-event:0X0236 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
-event:0X0237 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0230 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0231 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0232 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0233 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0234 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0235 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0236 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0237 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
#Group 36 pm_mark3, Marked Stores Processing Flow
-event:0X0240 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
-event:0X0241 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
-event:0X0242 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
-event:0X0243 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
-event:0X0244 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
-event:0X0245 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
-event:0X0246 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
-event:0X0247 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0240 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0241 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0242 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0243 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0244 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0245 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0246 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0247 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
#Group 37 pm_lsu_mark1, Load Store Unit Marked Events
-event:0X0250 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
-event:0X0251 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
-event:0X0252 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
-event:0X0253 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
-event:0X0254 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
-event:0X0255 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
-event:0X0256 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
-event:0X0257 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0250 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0251 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0252 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0253 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0254 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0255 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0256 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0257 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
#Group 38 pm_lsu_mark2, Load Store Unit Marked Events
-event:0X0260 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
-event:0X0261 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
-event:0X0262 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
-event:0X0263 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
-event:0X0264 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
-event:0X0265 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
-event:0X0266 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
-event:0X0267 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0260 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0261 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0262 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0263 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0264 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0265 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0266 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0267 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
#Group 39 pm_fxu1, Fixed Point events by unit
-event:0X0270 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000
-event:0X0271 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000
-event:0X0272 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000
-event:0X0273 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000
-event:0X0274 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000
-event:0X0275 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000
-event:0X0276 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000
-event:0X0277 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0270 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0271 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0272 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0273 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0274 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0275 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0276 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0277 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
#Group 40 pm_fxu2, Fixed Point events by unit
-event:0X0280 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000
-event:0X0281 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000
-event:0X0282 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000
-event:0X0283 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000
-event:0X0284 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000
-event:0X0285 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000
-event:0X0286 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000
-event:0X0287 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0280 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0281 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0282 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0283 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0284 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0285 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0286 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0287 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
#Group 41 pm_ifu, pm_ifu
-event:0X0290 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000
-event:0X0291 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000
-event:0X0292 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000
-event:0X0293 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000
-event:0X0294 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000
-event:0X0295 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000
-event:0X0296 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000
-event:0X0297 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0290 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0291 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0292 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0293 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0294 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0295 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0296 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0297 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
#Group 42 pm_cpi_stack1, CPI stack analysis
-event:0X02A0 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
-event:0X02A1 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
-event:0X02A2 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
-event:0X02A3 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
-event:0X02A4 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
-event:0X02A5 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
-event:0X02A6 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
-event:0X02A7 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A0 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A1 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A2 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A3 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A4 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A5 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A6 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A7 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
#Group 43 pm_cpi_stack2, CPI stack analysis
-event:0X02B0 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000
-event:0X02B1 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000
-event:0X02B2 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000
-event:0X02B3 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000
-event:0X02B4 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000
-event:0X02B5 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000
-event:0X02B6 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000
-event:0X02B7 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B0 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B1 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B2 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B3 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B4 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B5 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B6 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B7 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
#Group 44 pm_cpi_stack3, CPI stack analysis
-event:0X02C0 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000
-event:0X02C1 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000
-event:0X02C2 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000
-event:0X02C3 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000
-event:0X02C4 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000
-event:0X02C5 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000
-event:0X02C6 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000
-event:0X02C7 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C0 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C1 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C2 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C3 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C4 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C5 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C6 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C7 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
#Group 45 pm_cpi_stack4, CPI stack analysis
-event:0X02D0 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000
-event:0X02D1 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000
-event:0X02D2 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000
-event:0X02D3 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000
-event:0X02D4 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000
-event:0X02D5 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000
-event:0X02D6 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000
-event:0X02D7 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D0 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D1 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D2 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D3 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D4 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D5 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D6 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D7 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
#Group 46 pm_cpi_stack5, CPI stack analysis
-event:0X02E0 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000
-event:0X02E1 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000
-event:0X02E2 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000
-event:0X02E3 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000
-event:0X02E4 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000
-event:0X02E5 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000
-event:0X02E6 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000
-event:0X02E7 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002000
+event:0X02E0 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E1 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E2 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E3 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E4 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E5 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E6 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E7 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
#Group 47 pm_data2, data source and LMQ
-event:0X02F0 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000
-event:0X02F1 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000
-event:0X02F2 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000
-event:0X02F3 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000
-event:0X02F4 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000
-event:0X02F5 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000
-event:0X02F6 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000
-event:0X02F7 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002000
+event:0X02F0 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F1 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F2 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F3 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F4 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F5 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F6 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F7 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
#Group 48 pm_fetch_branch, Instruction fetch and branch events
-event:0X0300 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
-event:0X0301 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
-event:0X0302 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
-event:0X0303 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
-event:0X0304 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
-event:0X0305 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
-event:0X0306 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
-event:0X0307 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0300 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0301 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0302 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0303 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0304 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0305 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0306 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0307 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
#Group 49 pm_l1l2_miss, L1 and L2 miss events
-event:0X0310 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000
-event:0X0311 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000
-event:0X0312 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000
-event:0X0313 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000
-event:0X0314 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000
-event:0X0315 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000
-event:0X0316 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000
-event:0X0317 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002000
-
-#Group 50 pm_mp_data, data source and LMQ for 970mp
-event:0X0320 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000
-event:0X0321 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000
-event:0X0322 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000
-event:0X0323 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000
-event:0X0324 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000
-event:0X0325 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000
-event:0X0326 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000
-event:0X0327 mmcr0:0X00000712 mmcr1:0X0000300C7BD27F74 mmcra:0X00002000
-
-#Group 51 pm_mp_data2, data source and LMQ for 970mp
-event:0X0330 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000
-event:0X0331 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000
-event:0X0332 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000
-event:0X0333 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000
-event:0X0334 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000
-event:0X0335 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000
-event:0X0336 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000
-event:0X0337 mmcr0:0X0000090E mmcr1:0X0000300C4BCEFF74 mmcra:0X00002000
-
-#Group 52 pm_mp_data_from, Data From L2 instruction for 970mp
-event:0X0340 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000
-event:0X0341 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000
-event:0X0342 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000
-event:0X0343 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000
-event:0X0344 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000
-event:0X0345 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000
-event:0X0346 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000
-event:0X0347 mmcr0:0X0000070E mmcr1:0X000330004BCE7B00 mmcra:0X00002000
-
-#Group 53 pm_mp_mark_data_from, Marked Data From L2 instruction for 970mp
-event:0X0350 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001
-event:0X0351 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001
-event:0X0352 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001
-event:0X0353 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001
-event:0X0354 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001
-event:0X0355 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001
-event:0X0356 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001
-event:0X0357 mmcr0:0X0000070E mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0310 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0311 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0312 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0313 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0314 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0315 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0316 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0317 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+
+#Group 50 pm_data_from, Data From L2 instructions
+event:0X0320 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0321 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0322 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0323 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0324 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0325 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0326 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0327 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+
+#Group 51 pm_mark_data_from, Marked Data From L2 instructions
+event:0X0330 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0331 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0332 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0333 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0334 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0335 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0336 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0337 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
diff -paurN oprofile-0.9.2/events/ppc64/970MP/events oprofile-0.9.2+lost-samples-fixes/events/ppc64/970MP/events
--- oprofile-0.9.2/events/ppc64/970MP/events 2007-10-11 07:24:18.000000000 -0700
+++ oprofile-0.9.2+lost-samples-fixes/events/ppc64/970MP/events 2007-10-11 07:34:34.000000000 -0700
@@ -1,7 +1,7 @@
-#PPC64 PowerPC970 events
+#PPC64 PowerPC970MP events
#
# Copyright OProfile authors
-# Copyright (c) International Business Machines, 2006.
+# Copyright (c) International Business Machines, 2007.
# Contributed by Dave Nomura <dcnltc at us.ibm.com>.
#
#
@@ -291,8 +291,8 @@ event:0X01B7 counters:7 um:zero minimum:
#Group 28 pm_data, data source and LMQ
event:0X01C0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP28 : (Group 28 pm_data) Data loaded from L2
-event:0X01C1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_data) Instructions completed
-event:0X01C2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP28 : (Group 28 pm_data) Data loaded from memory
+event:0X01C1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP28 : (Group 28 pm_data) Data loaded from memory
+event:0X01C2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_data) Instructions completed
event:0X01C3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP28 : (Group 28 pm_data) Processor cycles
event:0X01C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_data) Instructions completed
event:0X01C5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP28 : (Group 28 pm_data) Processor cycles
@@ -480,12 +480,12 @@ event:0X02E6 counters:6 um:zero minimum:
event:0X02E7 counters:7 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP46 : (Group 46 pm_cpi_stack5) Cycles writing to instruction L1
#Group 47 pm_data2, data source and LMQ
-event:0X02F0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 shared
+event:0X02F0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
event:0X02F1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
-event:0X02F2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 modified
+event:0X02F2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
event:0X02F3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
-event:0X02F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
-event:0X02F5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
+event:0X02F4 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 shared
+event:0X02F5 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 modified
event:0X02F6 counters:6 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP47 : (Group 47 pm_data2) LMQ slot 0 allocated
event:0X02F7 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP47 : (Group 47 pm_data2) LMQ slot 0 valid
@@ -501,50 +501,30 @@ event:0X0307 counters:7 um:zero minimum:
#Group 49 pm_l1l2_miss, L1 and L2 miss events
event:0X0310 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from L2
-event:0X0311 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP49 : (Group 49 pm_l1l2_miss) Instructions completed
-event:0X0312 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from memory
+event:0X0311 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from memory
+event:0X0312 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP49 : (Group 49 pm_l1l2_miss) Instructions completed
event:0X0313 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP49 : (Group 49 pm_l1l2_miss) LSU0 L1 D cache load misses
event:0X0314 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP49 : (Group 49 pm_l1l2_miss) One or more PPC instruction completed
event:0X0315 counters:5 um:zero minimum:10000 name:PM_CYC_GRP49 : (Group 49 pm_l1l2_miss) Processor cycles
event:0X0316 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP49 : (Group 49 pm_l1l2_miss) LSU1 L1 D cache load misses
event:0X0317 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP49 : (Group 49 pm_l1l2_miss) L1 D cache load references
-#Group 50 pm_mp_data, data source and LMQ for 970mp
-event:0X0320 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP50 : (Group 50 pm_mp_data) Data loaded from L2
-event:0X0321 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP50 : (Group 50 pm_mp_data) Instructions completed
-event:0X0322 counters:2 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_mp_data) Processor cycles
-event:0X0323 counters:3 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_mp_data) Processor cycles
-event:0X0324 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP50 : (Group 50 pm_mp_data) Instructions completed
-event:0X0325 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP50 : (Group 50 pm_mp_data) Data loaded from memory
-event:0X0326 counters:6 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP50 : (Group 50 pm_mp_data) LMQ slot 0 allocated
-event:0X0327 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP50 : (Group 50 pm_mp_data) LMQ slot 0 valid
-
-#Group 51 pm_mp_data2, data source and LMQ for 970mp
-event:0X0330 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP51 : (Group 51 pm_mp_data2) Instructions completed
-event:0X0331 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP51 : (Group 51 pm_mp_data2) Data loaded from L2.5 shared
-event:0X0332 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP51 : (Group 51 pm_mp_data2) Instructions completed
-event:0X0333 counters:3 um:zero minimum:10000 name:PM_CYC_GRP51 : (Group 51 pm_mp_data2) Processor cycles
-event:0X0334 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP51 : (Group 51 pm_mp_data2) Data loaded from L2.5 modified
-event:0X0335 counters:5 um:zero minimum:10000 name:PM_CYC_GRP51 : (Group 51 pm_mp_data2) Processor cycles
-event:0X0336 counters:6 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP51 : (Group 51 pm_mp_data2) LMQ slot 0 allocated
-event:0X0337 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP51 : (Group 51 pm_mp_data2) LMQ slot 0 valid
-
-#Group 52 pm_mp_data_from, Data From L2 instruction for 970mp
-event:0X0340 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP52 : (Group 52 pm_mp_data_from) Data loaded from L2
-event:0X0341 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP52 : (Group 52 pm_mp_data_from) Data loaded from L2.5 shared
-event:0X0342 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP52 : (Group 52 pm_mp_data_from) Instructions completed
-event:0X0343 counters:3 um:zero minimum:10000 name:PM_CYC_GRP52 : (Group 52 pm_mp_data_from) Processor cycles
-event:0X0344 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP52 : (Group 52 pm_mp_data_from) Data loaded from L2.5 modified
-event:0X0345 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP52 : (Group 52 pm_mp_data_from) Data loaded from memory
-event:0X0346 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP52 : (Group 52 pm_mp_data_from) LSU1 L1 D cache load misses
-event:0X0347 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP52 : (Group 52 pm_mp_data_from) L1 D cache load references
-
-#Group 53 pm_mp_mark_data_from, Marked Data From L2 instruction for 970mp
-event:0X0350 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP53 : (Group 53 pm_mp_mark_data_from) Marked data loaded from L2
-event:0X0351 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP53 : (Group 53 pm_mp_mark_data_from) Marked data loaded from L2.5 shared
-event:0X0352 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP53 : (Group 53 pm_mp_mark_data_from) Instructions completed
-event:0X0353 counters:3 um:zero minimum:10000 name:PM_CYC_GRP53 : (Group 53 pm_mp_mark_data_from) Processor cycles
-event:0X0354 counters:4 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP53 : (Group 53 pm_mp_mark_data_from) Marked data loaded from L2.5 modified
-event:0X0355 counters:5 um:zero minimum:1000 name:PM_MRK_DATA_FROM_MEM_GRP53 : (Group 53 pm_mp_mark_data_from) Marked data loaded from memory
-event:0X0356 counters:6 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP53 : (Group 53 pm_mp_mark_data_from) Marked instruction finished
-event:0X0357 counters:7 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP53 : (Group 53 pm_mp_mark_data_from) Marked L1 reload data source valid
+#Group 50 pm_data_from, Data From L2 instructions
+event:0X0320 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP50 : (Group 50 pm_data_from) Data loaded from L2
+event:0X0321 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP50 : (Group 50 pm_data_from) Data loaded from memory
+event:0X0322 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP50 : (Group 50 pm_data_from) Instructions completed
+event:0X0323 counters:3 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_data_from) Processor cycles
+event:0X0324 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP50 : (Group 50 pm_data_from) Data loaded from L2.5 shared
+event:0X0325 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP50 : (Group 50 pm_data_from) Data loaded from L2.5 modified
+event:0X0326 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP50 : (Group 50 pm_data_from) LSU1 L1 D cache load misses
+event:0X0327 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP50 : (Group 50 pm_data_from) L1 D cache load references
+
+#Group 51 pm_mark_data_from, Marked Data From L2 instructions
+event:0X0330 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP51 : (Group 51 pm_mark_data_from) Marked data loaded from L2
+event:0X0331 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_MEM_GRP51 : (Group 51 pm_mark_data_from) Marked data loaded from memory
+event:0X0332 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP51 : (Group 51 pm_mark_data_from) Instructions completed
+event:0X0333 counters:3 um:zero minimum:10000 name:PM_CYC_GRP51 : (Group 51 pm_mark_data_from) Processor cycles
+event:0X0334 counters:4 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP51 : (Group 51 pm_mark_data_from) Marked data loaded from L2.5 shared
+event:0X0335 counters:5 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP51 : (Group 51 pm_mark_data_from) Marked data loaded from L2.5 modified
+event:0X0336 counters:6 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP51 : (Group 51 pm_mark_data_from) Marked instruction finished
+event:0X0337 counters:7 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP51 : (Group 51 pm_mark_data_from) Marked L1 reload data source valid
oprofile-0.9.3-fmtver.patch:
--- NEW FILE oprofile-0.9.3-fmtver.patch ---
Index: libop/op_config.h
===================================================================
RCS file: /cvsroot/oprofile/oprofile/libop/op_config.h,v
retrieving revision 1.21
retrieving revision 1.22
diff -U2 -u -r1.21 -r1.22
--- libop/op_config.h 18 Nov 2006 01:18:59 -0000 1.21
+++ libop/op_config.h 24 Oct 2007 19:00:58 -0000 1.22
@@ -44,5 +44,5 @@
#define OPD_MAGIC "DAE\n"
-#define OPD_VERSION 0x10
+#define OPD_VERSION 0x11
#define OP_MIN_CPU_BUF_SIZE 2048
Index: libpp/op_header.cpp
===================================================================
RCS file: /cvsroot/oprofile/oprofile/libpp/op_header.cpp,v
retrieving revision 1.24
retrieving revision 1.25
diff -U2 -u -r1.24 -r1.25
--- libpp/op_header.cpp 17 Nov 2006 23:47:29 -0000 1.24
+++ libpp/op_header.cpp 24 Oct 2007 19:00:58 -0000 1.25
@@ -16,4 +16,9 @@
#include <sstream>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include "op_config.h"
#include "op_exception.h"
#include "odb.h"
@@ -100,17 +105,26 @@
opd_header const read_header(string const & sample_filename)
{
- odb_t samples_db;
-
- int rc = odb_open(&samples_db, sample_filename.c_str(), ODB_RDONLY,
- sizeof(struct opd_header));
+ int fd = open(sample_filename.c_str(), O_RDONLY);
+ if (fd < 0)
+ throw op_fatal_error("Can't open sample file:" +
+ sample_filename);
- if (rc)
- throw op_fatal_error(sample_filename + ": " + strerror(rc));
+ opd_header header;
+ if (read(fd, &header, sizeof(header)) != sizeof(header)) {
+ close(fd);
+ throw op_fatal_error("Can't read sample file header:" +
+ sample_filename);
+ }
- opd_header head = *static_cast<opd_header *>(samples_db.data->base_memory);
+ if (memcmp(header.magic, OPD_MAGIC, sizeof(header.magic))) {
+ throw op_fatal_error("Invalid sample file, "
+ "bad magic number: " +
+ sample_filename);
+ close(fd);
+ }
- odb_close(&samples_db);
+ close(fd);
- return head;
+ return header;
}
Index: libpp/profile.cpp
===================================================================
RCS file: /cvsroot/oprofile/oprofile/libpp/profile.cpp,v
retrieving revision 1.26
retrieving revision 1.27
diff -U2 -u -r1.26 -r1.27
--- libpp/profile.cpp 10 May 2007 23:54:35 -0000 1.26
+++ libpp/profile.cpp 24 Oct 2007 19:00:58 -0000 1.27
@@ -71,12 +71,7 @@
void profile_t::open_sample_file(string const & filename, odb_t & db)
{
- int rc = odb_open(&db, filename.c_str(), ODB_RDONLY,
- sizeof(struct opd_header));
-
- if (rc)
- throw op_fatal_error(filename + ": " + strerror(rc));
-
- opd_header const & head =
- *static_cast<opd_header *>(odb_get_data(&db));
+ // Check first if the sample file version is ok else odb_open() can
+ // fail and the error message will be obscure.
+ opd_header head = read_header(filename);
if (head.version != OPD_VERSION) {
@@ -87,4 +82,10 @@
throw op_fatal_error(os.str());
}
+
+ int rc = odb_open(&db, filename.c_str(), ODB_RDONLY,
+ sizeof(struct opd_header));
+
+ if (rc)
+ throw op_fatal_error(filename + ": " + strerror(rc));
}
oprofile-gcc43.patch:
--- NEW FILE oprofile-gcc43.patch ---
diff -up oprofile-gcc43/pp/oparchive.cpp.orig oprofile-gcc43/pp/oparchive.cpp
--- oprofile-gcc43/pp/oparchive.cpp.orig 2007-11-20 15:47:00.000000000 -0500
+++ oprofile-gcc43/pp/oparchive.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -12,6 +12,7 @@
#include <iostream>
#include <fstream>
+#include <cstdlib>
#include <errno.h>
#include <string.h>
diff -up oprofile-gcc43/pp/opgprof_options.cpp.orig oprofile-gcc43/pp/opgprof_options.cpp
--- oprofile-gcc43/pp/opgprof_options.cpp.orig 2007-11-20 15:47:00.000000000 -0500
+++ oprofile-gcc43/pp/opgprof_options.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -13,6 +13,7 @@
#include <list>
#include <iterator>
#include <iostream>
+#include <cstdlib>
#include "opgprof_options.h"
#include "popt_options.h"
diff -up oprofile-gcc43/pp/common_option.cpp.orig oprofile-gcc43/pp/common_option.cpp
--- oprofile-gcc43/pp/common_option.cpp.orig 2007-11-20 15:46:59.000000000 -0500
+++ oprofile-gcc43/pp/common_option.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -12,6 +12,7 @@
#include <iostream>
#include <sstream>
#include <iterator>
+#include <cstdlib>
#include "op_config.h"
#include "locate_images.h"
diff -up oprofile-gcc43/pp/opannotate_options.cpp.orig oprofile-gcc43/pp/opannotate_options.cpp
--- oprofile-gcc43/pp/opannotate_options.cpp.orig 2008-02-13 13:57:22.000000000 -0500
+++ oprofile-gcc43/pp/opannotate_options.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -13,6 +13,7 @@
#include <list>
#include <iterator>
#include <iostream>
+#include <cstdlib>
#include "profile_spec.h"
#include "arrange_profiles.h"
diff -up oprofile-gcc43/libregex/demangle_symbol.cpp.orig oprofile-gcc43/libregex/demangle_symbol.cpp
--- oprofile-gcc43/libregex/demangle_symbol.cpp.orig 2007-06-03 12:50:17.000000000 -0400
+++ oprofile-gcc43/libregex/demangle_symbol.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -8,6 +8,8 @@
* @author John Levon
*/
+#include <cstdlib>
+
#include "config.h"
#include "demangle_symbol.h"
diff -up oprofile-gcc43/libpp/sample_container.cpp.orig oprofile-gcc43/libpp/sample_container.cpp
--- oprofile-gcc43/libpp/sample_container.cpp.orig 2003-08-10 20:59:18.000000000 -0400
+++ oprofile-gcc43/libpp/sample_container.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -9,6 +9,7 @@
* @author John Levon
*/
+#include <climits>
#include <set>
#include <numeric>
#include <algorithm>
diff -up oprofile-gcc43/libpp/profile.cpp.orig oprofile-gcc43/libpp/profile.cpp
--- oprofile-gcc43/libpp/profile.cpp.orig 2007-11-12 16:56:07.000000000 -0500
+++ oprofile-gcc43/libpp/profile.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -15,6 +15,7 @@
#include <iostream>
#include <string>
#include <sstream>
+#include <cstring>
#include <cerrno>
diff -up oprofile-gcc43/libpp/op_header.cpp.orig oprofile-gcc43/libpp/op_header.cpp
--- oprofile-gcc43/libpp/op_header.cpp.orig 2007-11-12 16:56:07.000000000 -0500
+++ oprofile-gcc43/libpp/op_header.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -14,6 +14,7 @@
#include <iomanip>
#include <set>
#include <sstream>
+#include <cstring>
#include <sys/types.h>
#include <sys/stat.h>
diff -up oprofile-gcc43/libabi/opimport.cpp.orig oprofile-gcc43/libabi/opimport.cpp
--- oprofile-gcc43/libabi/opimport.cpp.orig 2005-08-17 15:15:41.000000000 -0400
+++ oprofile-gcc43/libabi/opimport.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -17,6 +17,8 @@
#include <iostream>
#include <vector>
#include <cassert>
+#include <cstring>
+#include <cstdlib>
#include <sys/types.h>
#include <sys/stat.h>
diff -up oprofile-gcc43/gui/oprof_start_util.cpp.orig oprofile-gcc43/gui/oprof_start_util.cpp
--- oprofile-gcc43/gui/oprof_start_util.cpp.orig 2005-08-07 07:15:48.000000000 -0400
+++ oprofile-gcc43/gui/oprof_start_util.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -19,6 +19,7 @@
#include <sstream>
#include <iostream>
#include <fstream>
+#include <cstdlib>
#include <qfiledialog.h>
#include <qmessagebox.h>
diff -up oprofile-gcc43/libutil++/file_manip.cpp.orig oprofile-gcc43/libutil++/file_manip.cpp
--- oprofile-gcc43/libutil++/file_manip.cpp.orig 2007-11-12 16:56:07.000000000 -0500
+++ oprofile-gcc43/libutil++/file_manip.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -15,6 +15,8 @@
#include <dirent.h>
#include <fnmatch.h>
#include <utime.h>
+#include <limits.h>
+#include <stdlib.h>
#include <cstdio>
#include <cerrno>
diff -up oprofile-gcc43/libutil++/bfd_support.cpp.orig oprofile-gcc43/libutil++/bfd_support.cpp
--- oprofile-gcc43/libutil++/bfd_support.cpp.orig 2007-11-12 16:56:07.000000000 -0500
+++ oprofile-gcc43/libutil++/bfd_support.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -19,6 +19,8 @@
#include <fstream>
#include <sstream>
#include <string>
+#include <cstring>
+#include <cstdlib>
using namespace std;
diff -up oprofile-gcc43/libutil++/child_reader.cpp.orig oprofile-gcc43/libutil++/child_reader.cpp
--- oprofile-gcc43/libutil++/child_reader.cpp.orig 2004-01-19 15:00:27.000000000 -0500
+++ oprofile-gcc43/libutil++/child_reader.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -11,10 +11,13 @@
#include <unistd.h>
#include <sys/wait.h>
+#include <limits.h>
#include <cerrno>
#include <sstream>
#include <iostream>
+#include <cstring>
+#include <cstdlib>
#include "op_libiberty.h"
#include "child_reader.h"
diff -up oprofile-gcc43/libutil++/bfd_spu_support.cpp.orig oprofile-gcc43/libutil++/bfd_spu_support.cpp
--- oprofile-gcc43/libutil++/bfd_spu_support.cpp.orig 2008-02-13 13:57:18.000000000 -0500
+++ oprofile-gcc43/libutil++/bfd_spu_support.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -20,6 +20,7 @@
#include <fstream>
#include <sstream>
#include <string>
+#include <cstring>
#include <sys/types.h>
struct spu_elf {
diff -up oprofile-gcc43/libutil++/cverb.cpp.orig oprofile-gcc43/libutil++/cverb.cpp
--- oprofile-gcc43/libutil++/cverb.cpp.orig 2006-11-20 10:01:48.000000000 -0500
+++ oprofile-gcc43/libutil++/cverb.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -13,6 +13,7 @@
#include <iostream>
#include <map>
#include <string>
+#include <cstring>
#include "cverb.h"
diff -up oprofile-gcc43/libutil++/op_spu_bfd.cpp.orig oprofile-gcc43/libutil++/op_spu_bfd.cpp
--- oprofile-gcc43/libutil++/op_spu_bfd.cpp.orig 2008-02-13 13:57:18.000000000 -0500
+++ oprofile-gcc43/libutil++/op_spu_bfd.cpp 2008-02-15 10:58:50.000000000 -0500
@@ -14,6 +14,8 @@
#include <sys/stat.h>
#include <iostream>
+#include <cstring>
+#include <cstdlib>
#include "op_bfd.h"
#include "locate_images.h"
Index: oprofile.spec
===================================================================
RCS file: /cvs/pkgs/rpms/oprofile/F-8/oprofile.spec,v
retrieving revision 1.61
retrieving revision 1.62
diff -u -r1.61 -r1.62
--- oprofile.spec 12 Nov 2007 22:20:50 -0000 1.61
+++ oprofile.spec 23 Jun 2008 20:03:35 -0000 1.62
@@ -3,7 +3,7 @@
Summary: System wide profiler
Name: oprofile
Version: 0.9.3
-Release: 7%{?dist}
+Release: 18%{?dist}
License: GPL
Group: Development/System
#
@@ -12,8 +12,13 @@
Requires: which
Patch10: oprofile-0.4-guess2.patch
Patch63: oprofile-0.7-libs.patch
-Patch83: oprofile-0.9.1-xen.patch
+Patch83: oprofile-0.9.3-xen.patch
Patch92: oprofile-0.9.3-ld_options.patch
+Patch93: oprofile-0.9.3-family10.patch
+Patch94: oprofile-0.9.3-ranges.patch
+Patch95: oprofile-0.9.3-970MP.patch
+Patch96: oprofile-0.9.3-fmtver.patch
+Patch100: oprofile-gcc43.patch
URL: http://oprofile.sf.net
ExclusiveArch: %{ix86} ia64 x86_64 ppc ppc64 s390 s390x alpha alphaev6 sparc sparc64
@@ -67,6 +72,11 @@
#%patch90 -p0 -b .race
#%patch91 -p1 -b .k10
%patch92 -p0 -b .ld_option
+%patch93 -p0 -b .family10
+%patch94 -p0 -b .ranges
+%patch95 -p1 -b .970MP
+%patch96 -p0 -b .fmtver
+%patch100 -p1 -b .gcc43
./autogen.sh
@@ -95,7 +105,8 @@
--mandir=%{_mandir} \
--infodir=%{_infodir} \
--with-separate-debug-dir=/usr/lib/debug \
---enable-abi
+--enable-abi \
+--with-qt-dir=$QTDIR
make CFLAGS="$RPM_OPT_FLAGS"
@@ -181,6 +192,31 @@
%{_bindir}/oprof_start
%changelog
+* Mon Jun 23 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-18
+- Fix default location for vmlinux. rhbz #451539
+
+* Fri Apr 04 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-17
+- Use older qt3-devel. rhbz #440949
+
+* Fri Feb 15 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-16
+- Corrections for compilation with gcc-4.3.
+
+* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-15
+- Deal with xenoprof conlficts with cell. Resolves: rhbz #250852
+
+* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-14
+- Bump format version. Check version properly. Resolves: rhbz #394571
+
+* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-13
+- Disable profiling in hypervisor on 970MP to prevent lost interrupts.
+ Resolves: rhbz #391251
+
+* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-12
+- Use more incluse set of kernel ranges. Resolves: rhbz #307111
+
+* Fri Jan 18 2008 Will Cohen <wcohen at redhat.com> - 0.9.3-11
+- Update AMD family 10h events to match AMD documentation Resolves: rhbz #232956
+
* Mon Nov 12 2007 Will Cohen <wcohen at redhat.com> - 0.9.3-7
- Should correct missing 'test' in patch.
oprofile-0.4-guess2.patch:
Index: oprofile-0.4-guess2.patch
===================================================================
RCS file: /cvs/pkgs/rpms/oprofile/F-8/oprofile-0.4-guess2.patch,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -r1.1 -r1.2
--- oprofile-0.4-guess2.patch 9 Sep 2004 09:43:51 -0000 1.1
+++ oprofile-0.4-guess2.patch 23 Jun 2008 20:03:35 -0000 1.2
@@ -6,7 +6,7 @@
string const version(info.release);
- string const vmlinux_path("/lib/modules/" + version
- + "/build/vmlinux");
-+ std::string const vmlinux_path("/boot/vmlinux-" + version);
++ std::string const vmlinux_path("/usr/lib/debug/lib/modules/" + version + "/vmlinux");
kernel_filename = vmlinux_path;
}
}
--- oprofile-0.9.1-xen.patch DELETED ---
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