rpms/xorg-x11-drv-ati/F-8 mach64-ia64-pagesize.patch, NONE, 1.1 radeon-git-upstream-fixes2.patch, NONE, 1.1 radeon-git-upstream-fixes.patch, 1.6, 1.7 xorg-x11-drv-ati.spec, 1.76, 1.77
Dave Airlie (airlied)
fedora-extras-commits at redhat.com
Mon Mar 31 01:54:40 UTC 2008
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Author: airlied
Update of /cvs/pkgs/rpms/xorg-x11-drv-ati/F-8
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv28497
Modified Files:
radeon-git-upstream-fixes.patch xorg-x11-drv-ati.spec
Added Files:
mach64-ia64-pagesize.patch radeon-git-upstream-fixes2.patch
Log Message:
* Mon Mar 31 2008 Dave Airlie <airlied at redhat.com> 6.8.0-2
- rebase to latest git tree
mach64-ia64-pagesize.patch:
--- NEW FILE mach64-ia64-pagesize.patch ---
>From 89a9ad75f3e50e25275b803617d5e74709ead269 Mon Sep 17 00:00:00 2001
From: Yi Zhan <yi.zhan at intel.com>
Date: Wed, 26 Mar 2008 16:13:08 +1000
Subject: [PATCH] mach64: on IA64 systems the pciaccess page size mapping was getting E2BIG
As the ia64 pagesize was 16k, and aperture was only 4k, this was messing up
on ia64 machines.
Modified fix from RH BZ 438947 - airlied
---
src/atividmem.c | 20 +++++++++++++++-----
1 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/src/atividmem.c b/src/atividmem.c
index 986ac0f..8950f84 100644
--- a/src/atividmem.c
+++ b/src/atividmem.c
@@ -146,7 +146,12 @@ ATIUnmapMMIO
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pMMIO, getpagesize());
#else
- pci_device_unmap_range(pATI->PCIInfo, pATI->pMMIO, getpagesize());
+ unsigned long size;
+
+ size = PCI_REGION_SIZE(pATI->PCIInfo, 2);
+ if (!size || size > getpagesize())
+ size = getpagesize();
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMMIO, size);
#endif
}
@@ -340,10 +345,15 @@ ATIMapApertures
int mode = PCI_DEV_MAP_FLAG_WRITABLE;
- int err = pci_device_map_range(pVideo,
- MMIOBase,
- PageSize,
- mode, &pATI->pMMIO);
+ int err;
+ int size;
+
+ size = PCI_REGION_SIZE(pVideo, 2);
+ if (!size || size > PageSize)
+ size = PageSize;
+
+ err = pci_device_map_range(pVideo, MMIOBase,
+ size, mode, &pATI->pMMIO);
if (err)
{
--
1.5.4.4
radeon-git-upstream-fixes2.patch:
--- NEW FILE radeon-git-upstream-fixes2.patch ---
commit 9c62c820ba45ebc14d5f36f5d7885863800b6adb
Author: Michel Dänzer <michel at tungstengraphics.com>
Date: Fri Mar 28 12:37:29 2008 +0100
Include config.h, so FGL_LINUX can actually be defined when it's tested...
commit a00d9260a85b94a522c442aee24bc5ea4dc31c5c
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Thu Mar 27 20:03:13 2008 -0400
RADEON: fix lid issues on AVIVO chips for real this time :)
commit f0e89c09074b2c7e641f73692bb39b0bf68eb49c
Author: Alex Deucher <alex at botch2.com>
Date: Thu Mar 27 19:15:18 2008 -0400
Revert "RADEON: attempt to fix lid issues"
This reverts commit 9b4473c1d830b88866dd22e8174a07195bd6fcf4.
This doesn't help.
commit 1442d396b938049b83f009a78ddabe2bf85641b6
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Mar 27 14:02:51 2008 +1000
radeon: size bios to max of bar vs 64k.
reported by dwmw2: rhbz 438299
commit de2f609ff0004ef8b74727bfebc2c74fb91205ea
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Wed Mar 26 18:35:21 2008 -0400
AVIVO: no need to call PreinitXv() on AVIVO chips as they have no overlay
commit 75884c257bc2bcfa5b498a77d4c403f09face036
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Wed Mar 26 18:16:47 2008 -0400
XAA: update message about render so as to not confuse users
commit 9b4473c1d830b88866dd22e8174a07195bd6fcf4
Author: Alex Deucher <alex at t41p.hsd1.va.comcast.net>
Date: Wed Mar 26 18:01:29 2008 -0400
RADEON: attempt to fix lid issues
On some laptops the bios attempts to re-program the chip
when a lid event comes in. This should hopefully prevent
the bios from doing that.
commit 8b144830fe9b4a0cee4745023de5e7d387070f60
Author: Alex Deucher <alex at samba.(none)>
Date: Tue Mar 25 01:15:05 2008 -0400
RV250: disable textured video due to HW bug
The YUV->RGB conversion in the texture engine is broken
on RV250 so the colors come out wrong.
commit 1789f11ab91633d3928f8b71988d51ff44bda9d1
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Mar 24 19:03:30 2008 -0400
R3xx/R5xx: flush PVS state before enabling pvs-bypass
commit 305a3310963a5dd07b3495015b06aa8c7c4e6b02
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Mar 24 14:25:03 2008 -0400
R3xx/R5xx: move more VAP, etc. state setup into common init3d() function
Also some minor code cleanups
commit 399b1d405e602c62d6deebea6d7e1f38886cd8e2
Author: Alex Deucher <alex at samba.(none)>
Date: Mon Mar 24 13:04:57 2008 -0400
R3xx/R5xx: use non VAP/TCP for textured video
Just extra state to emit.
commit cd77ec18f32a7b36acb655c927bbfd7044019f97
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Mar 24 18:42:21 2008 +1000
r300: don't bother with VAP/TCL for render.
We just send more data to the card to process per transaction, without getting
any actual gains, as we already pre-compute the vertices without needing
any clipping or transforms from the card.
Perhaps some stuff could be done on-card, but so far the code is a lot
faster if we avoid sending this extra info.
pre: 150000 glyphs/sec
post: 185000 glyphs/sec
commit 301c6739b88676a0c78fc72194e993f894b8dc28
Author: Alex Deucher <alex at botch2.com>
Date: Sun Mar 23 11:14:02 2008 -0400
RS4xx: Revert back to previous fifo settings for now
Setup of these registers needs more investigation.
commit 9bea60b3eb378de5e1d44cc02a2763f4feae7882
Author: Alex Deucher <alex at botch2.com>
Date: Sat Mar 22 11:46:15 2008 -0400
RS4xx: more work on disp/disp2 fifo setup
commit 90f11c3986c28daa7b600b9662da145af325d264
Author: Alex Deucher <alex at botch2.com>
Date: Sat Mar 22 11:29:51 2008 -0400
RS4xx: missed this on the last commit.
commit 6d5066a451017a2683addc9e2496987626795dda
Author: Alex Deucher <alex at samba.(none)>
Date: Fri Mar 21 16:21:54 2008 -0400
RS4xx: attempt to set up disp/disp2 fifos correctly
If you have an XPRESS chip, please test!!!
commit fb1cffac05ae20c8365b25a2042b0ae961880faf
Author: Alex Deucher <alex at samba.(none)>
Date: Fri Mar 21 15:24:36 2008 -0400
RS4xx: attempt to fix TMDS/DVO support
XPRESS chips added a second set of FP control registers.
I don't have the hw to test however.
commit 5e3b21284482df9974c9a58f248f0100def2bb0c
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 19:15:05 2008 -0400
Disable the setting of HARDWARE_CURSOR_BIT_ORDER_MSBFIRST
See bug 11796
commit 17cd42ed31814ba329a6a68edd0d75390a7da40e
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Mar 19 18:17:10 2008 -0400
Enable BSR in Log2 functions
This patch edits RADEONLog2 and ATILog2 to use the x86 BSR instruction instead
of looping through bits. It should provide a somewhat of a speed increase in
this function on x86 and AMD64 architectures.
Note: the BSR instruction was added with the 80386 CPU and is therefore not
compatible with earlier CPUs, though I highly doubt it's even possible to use a
286 in conjunction with a Radeon.
The inline assembly also works with Intel's compiler (icc).
commit c83827b4d2b6f03c54429e757a756eb99ff8be6b
Author: Paulo Cesar Pereira de Andrade <pcpa at mandriva.com.br>
Date: Wed Mar 19 17:58:34 2008 -0400
[PATCH] Compile warning fixes.
Minor changes to avoid declarations mixed with code.
Ansified functions with empty prototype to specify they don't
receive arguments.
Added some prototypes to radeon.h, and major reorder on radeon.h
adding prototypes in alphabetical order and specifying to file that
defines it.
commit bed9754ad21d6c0a7f61067b04ba31c430a7cecb
Merge: 55e446b... f71ac0e...
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 16:06:41 2008 -0400
Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into r3xx-render
commit 55e446b5bc091e6c7b3c2e9ae20b45130555c246
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 13:15:32 2008 -0400
R3xx/R5xx: Make sure to clamp the output of the FS
commit b6aa4279cbe68cc8e4523795e9714fb798b62d98
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 12:45:01 2008 -0400
R5xx: bump textured video limits to 4096
commit 4a445a3e8c4c5ecd9d4ef8daa26906c3ceaa94a1
Author: Alex Deucher <alex at samba.(none)>
Date: Wed Mar 19 12:31:51 2008 -0400
RADEON: add new macros to distinguish between R3xx and R5xx 3D
commit 85d0c9e8d22ccc72bec87b3fd44da5d7609293e0
Author: Alex Deucher <alex at samba.(none)>
[...8597 lines suppressed...]
+/* DO NOT FORGET to setup constants before calling InitTheatre */
+#define xf86_InitTheatre InitTheatre
+_X_EXPORT void InitTheatre(TheatrePtr t);
+#define xf86_RT_SetTint RT_SetTint
+_X_EXPORT void RT_SetTint (TheatrePtr t, int hue);
+#define xf86_RT_SetSaturation RT_SetSaturation
+_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation);
+#define xf86_RT_SetBrightness RT_SetBrightness
+_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness);
+#define xf86_RT_SetSharpness RT_SetSharpness
+_X_EXPORT void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness);
+#define xf86_RT_SetContrast RT_SetContrast
+_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast);
+#define xf86_RT_SetInterlace RT_SetInterlace
+_X_EXPORT void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace);
+#define xf86_RT_SetStandard RT_SetStandard
+_X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard);
+#define xf86_RT_SetOutputVideoSize RT_SetOutputVideoSize
+_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On);
+#define xf86_RT_SetConnector RT_SetConnector
+_X_EXPORT void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag);
+#define xf86_ResetTheatreRegsForNoTVout ResetTheatreRegsForNoTVout
+_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t);
+#define xf86_ResetTheatreRegsForTVout ResetTheatreRegsForTVout
+_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t);
+#define xf86_DumpRageTheatreRegs DumpRageTheatreRegs
+_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t);
+#define xf86_DumpRageTheatreRegsByName DumpRageTheatreRegsByName
+_X_EXPORT void DumpRageTheatreRegsByName(TheatrePtr t);
+#define xf86_ShutdownTheatre ShutdownTheatre
+_X_EXPORT void ShutdownTheatre(TheatrePtr t);
#endif
diff --git a/src/theatre200.c b/src/theatre200.c
index 672f01e..0341c6e 100644
--- a/src/theatre200.c
+++ b/src/theatre200.c
@@ -1492,7 +1492,7 @@ static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg)
* Inputs: int hue - the hue value to be set. *
* Outputs: NONE *
****************************************************************************/
-void RT_SetTint (TheatrePtr t, int hue)
+_X_EXPORT void RT_SetTint (TheatrePtr t, int hue)
{
/* Validate Hue level */
if (hue < -1000)
@@ -1517,7 +1517,7 @@ void RT_SetTint (TheatrePtr t, int hue)
* Inputs: int Saturation - the saturation value to be set. *
* Outputs: NONE *
****************************************************************************/
-void RT_SetSaturation (TheatrePtr t, int Saturation)
+_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation)
{
/* VALIDATE SATURATION LEVEL */
if (Saturation < -1000L)
@@ -1543,7 +1543,7 @@ void RT_SetSaturation (TheatrePtr t, int Saturation)
* Inputs: int Brightness - the brightness value to be set. *
* Outputs: NONE *
****************************************************************************/
-void RT_SetBrightness (TheatrePtr t, int Brightness)
+_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness)
{
/* VALIDATE BRIGHTNESS LEVEL */
if (Brightness < -1000)
@@ -1572,7 +1572,7 @@ void RT_SetBrightness (TheatrePtr t, int Brightness)
* Inputs: CARD16 wSharpness - the sharpness value to be set. *
* Outputs: NONE *
****************************************************************************/
-void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness)
+_X_EXPORT void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness)
{
switch (wSharpness)
{
@@ -1598,7 +1598,7 @@ void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness)
* Inputs: int Contrast - the contrast value to be set. *
* Outputs: NONE *
****************************************************************************/
-void RT_SetContrast (TheatrePtr t, int Contrast)
+_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast)
{
/* VALIDATE CONTRAST LEVEL */
if (Contrast < -1000)
@@ -1626,7 +1626,7 @@ void RT_SetContrast (TheatrePtr t, int Contrast)
* Inputs: CARD8 bInterlace *
* Outputs: NONE *
****************************************************************************/
-void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace)
+_X_EXPORT void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace)
{
switch(bInterlace)
{
@@ -1653,7 +1653,7 @@ void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace)
* Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) *
* Outputs: NONE *
****************************************************************************/
-void RT_SetStandard (TheatrePtr t, CARD16 wStandard)
+_X_EXPORT void RT_SetStandard (TheatrePtr t, CARD16 wStandard)
{
xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n",
wStandard);
@@ -1772,7 +1772,7 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard)
* CARD8 fVBI_Cap_On - enable VBI capture *
* Outputs: NONE *
****************************************************************************/
-void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On)
+_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On)
{
/* VBI is ignored now */
@@ -1792,7 +1792,7 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA
* int tunerFlag
* Outputs: NONE *
****************************************************************************/
-void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag)
+_X_EXPORT void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag)
{
CARD32 data;
@@ -1871,7 +1871,7 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag)
} /* RT_SetConnector ()...*/
-void InitTheatre(TheatrePtr t)
+_X_EXPORT void InitTheatre(TheatrePtr t)
{
CARD32 data;
CARD32 M, N, P;
@@ -1992,7 +1992,7 @@ err_exit:
}
-void ShutdownTheatre(TheatrePtr t)
+_X_EXPORT void ShutdownTheatre(TheatrePtr t)
{
#if 0
WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE);
@@ -2003,7 +2003,7 @@ void ShutdownTheatre(TheatrePtr t)
t->mode=MODE_UNINITIALIZED;
}
-void DumpRageTheatreRegs(TheatrePtr t)
+_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t)
{
int i;
CARD32 data;
@@ -2224,7 +2224,7 @@ void DumpRageTheatreRegsByName(TheatrePtr t)
}
-void ResetTheatreRegsForNoTVout(TheatrePtr t)
+_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t)
{
RT_regw(VIP_CLKOUT_CNTL, 0x0);
RT_regw(VIP_HCOUNT, 0x0);
@@ -2238,7 +2238,7 @@ void ResetTheatreRegsForNoTVout(TheatrePtr t)
}
-void ResetTheatreRegsForTVout(TheatrePtr t)
+_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t)
{
/* RT_regw(VIP_HW_DEBUG, 0x200); */
/* RT_regw(VIP_INT_CNTL, 0x0);
diff --git a/src/theatre_detect.c b/src/theatre_detect.c
index 8770911..79dcfe4 100644
--- a/src/theatre_detect.c
+++ b/src/theatre_detect.c
@@ -43,6 +43,7 @@
#include "generic_bus.h"
#include "theatre.h"
#include "theatre_reg.h"
+#include "theatre_detect.h"
static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data)
{
@@ -64,7 +65,7 @@ static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data)
#define VIP_TYPE "ATI VIP BUS"
-TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b)
+_X_EXPORT TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b)
{
TheatrePtr t;
int i;
diff --git a/src/theatre_detect.h b/src/theatre_detect.h
index 5fed160..53d8d11 100644
--- a/src/theatre_detect.h
+++ b/src/theatre_detect.h
@@ -38,9 +38,9 @@
*/
-TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b);
+#define xf86_DetectTheatre DetectTheatre
+_X_EXPORT TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b);
-#define xf86_DetectTheatre ((TheatrePtr (*)(GENERIC_BUS_Ptr))LoaderSymbol("DetectTheatre"))
#endif
radeon-git-upstream-fixes.patch:
Index: radeon-git-upstream-fixes.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/F-8/radeon-git-upstream-fixes.patch,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -r1.6 -r1.7
--- radeon-git-upstream-fixes.patch 26 Feb 2008 08:52:29 -0000 1.6
+++ radeon-git-upstream-fixes.patch 31 Mar 2008 01:54:02 -0000 1.7
@@ -1,3 +1,57 @@
+commit 68888189cf8d460ef6f8f2f1431a6ffe9fcd8134
+Author: Alex Deucher <alex at samba.(none)>
+Date: Wed Feb 27 03:09:28 2008 -0500
+
+ RADEON: fix textured video uploads
+
+commit 7cfad216a3f1486be194c972b9b6bcf070358586
+Author: Alex Deucher <alex at samba.(none)>
+Date: Wed Feb 27 02:13:10 2008 -0500
+
+ RADEON: fix clipping for textured video
+
+commit a2dca1d68d751def34ef3c6f836574173737bf76
+Author: Alex Deucher <alex at samba.(none)>
+Date: Tue Feb 26 16:38:29 2008 -0500
+
+ RADEON: Convert textured video to use pipelined uploads
+
+commit b4fa1ce9d2da04d94521a82d3c2e95f0fe985ccc
+Author: Alex Deucher <alex at samba.(none)>
+Date: Tue Feb 26 14:45:25 2008 -0500
+
+ R300/R500: fix up clipping
+
+ Based on patch from Peter Zubaj.
+
+commit 44e527a117ab0a363135ff066c7f7e0c12e3dc89
+Author: Alex Deucher <alex at samba.(none)>
+Date: Tue Feb 26 14:33:24 2008 -0500
+
+ R300: fix cordinate clamping in render code
+
+ Based on Peter's fix for textured video
+
+commit 00ec17ad53d7ad43f19c9b723794ac1b8ef86826
+Author: Peter Zubaj <pzubaj at marticonet.sk>
+Date: Tue Feb 26 14:26:14 2008 -0500
+
+ R300: Fix clamping and pitch for textured video
+
+commit 4207793f9b6c891cb17ba715223d2002668885e3
+Author: Alex Deucher <alex at samba.(none)>
+Date: Tue Feb 26 13:16:22 2008 -0500
+
+ R300/R500: set the number graphics pipes properly
+
+ This should fix the checkerboard issues on r300/r350 cards.
+
+commit 823d8bf49e4c0a8c839354179942c5a1944c178d
+Author: Alex Deucher <alex at samba.(none)>
+Date: Tue Feb 26 12:25:14 2008 -0500
+
+ R300/R500: clean up magic numbers in textured video
+
commit 8ea75b268f11794f4a7e7bac52cb256490ed3fd2
Author: Dave Airlie <airlied at linux.ie>
Date: Tue Feb 26 16:29:19 2008 +1000
@@ -353,15 +407,30 @@
info->BiosConnector[i].TMDSType = TMDS_LVTMA;
} else
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
-index 8c4b598..af06735 100644
+index 8c4b598..0250aef 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
-@@ -57,138 +57,153 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
+@@ -30,6 +30,8 @@
+ #include "config.h"
+ #endif
+
++#include "ati_pciids_gen.h"
++
+ #if defined(ACCEL_MMIO) && defined(ACCEL_CP)
+ #error Cannot define both MMIO and CP acceleration!
+ #endif
+@@ -53,142 +55,182 @@
+ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
+ {
+ RADEONInfoPtr info = RADEONPTR(pScrn);
++ CARD32 gb_tile_config;
+ ACCEL_PREAMBLE();
info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
- if (IS_R300_VARIANT) {
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
++
BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
@@ -371,13 +440,35 @@
+ OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN);
FINISH_ACCEL();
++ gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
++
++ if ((info->Chipset == PCI_CHIP_RV410_5E4C) ||
++ (info->Chipset == PCI_CHIP_RV410_5E4F)) {
++ /* RV410 SE chips */
++ gb_tile_config |= R300_PIPE_COUNT_RV350;
++ } else if ((info->ChipFamily == CHIP_FAMILY_RV350) ||
++ (info->ChipFamily == CHIP_FAMILY_RV380) ||
++ (info->ChipFamily == CHIP_FAMILY_RS400)) {
++ /* RV3xx, RS4xx chips */
++ gb_tile_config |= R300_PIPE_COUNT_RV350;
++ } else if ((info->ChipFamily == CHIP_FAMILY_R300) ||
++ (info->ChipFamily == CHIP_FAMILY_R350)) {
++ /* R3xx chips */
++ gb_tile_config |= R300_PIPE_COUNT_R300;
++ } else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
++ (info->ChipFamily == CHIP_FAMILY_RS690)) {
++ /* RV4xx, RS6xx chips */
++ gb_tile_config |= R300_PIPE_COUNT_R420_3P;
++ } else {
++ /* R4xx, R5xx chips */
++ gb_tile_config |= R300_PIPE_COUNT_R420;
++ }
++
BEGIN_ACCEL(3);
- OUT_ACCEL_REG(R300_GB_TILE_CONFIG, 0x10011);
- OUT_ACCEL_REG(R300_GB_SELECT,0x0);
- OUT_ACCEL_REG(R300_GB_ENABLE, 0x0);
-+ OUT_ACCEL_REG(R300_GB_TILE_CONFIG, (R300_ENABLE_TILING |
-+ R300_TILE_SIZE_16 |
-+ R300_SUBPIXEL_1_16));
++ OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
+ OUT_ACCEL_REG(R300_GB_SELECT, 0);
+ OUT_ACCEL_REG(R300_GB_ENABLE, 0);
FINISH_ACCEL();
@@ -422,20 +513,8 @@
- OUT_ACCEL_REG(R300_GA_ROUND_MODE, 0x5);
- OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, 0xAAAA);
- OUT_ACCEL_REG(R300_GA_OFFSET, 0x0);
-+ OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
-+ OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
-+ R300_COLOR_ROUND_NEAREST));
-+ OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
-+ R300_ALPHA0_SHADING_GOURAUD |
-+ R300_RGB1_SHADING_GOURAUD |
-+ R300_ALPHA1_SHADING_GOURAUD |
-+ R300_RGB2_SHADING_GOURAUD |
-+ R300_ALPHA2_SHADING_GOURAUD |
-+ R300_RGB3_SHADING_GOURAUD |
-+ R300_ALPHA3_SHADING_GOURAUD));
-+ OUT_ACCEL_REG(R300_GA_OFFSET, 0);
- FINISH_ACCEL();
-
+- FINISH_ACCEL();
+-
- BEGIN_ACCEL(26);
- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0x0);
- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
@@ -467,8 +546,20 @@
- OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
- OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, 0x10000);
-- FINISH_ACCEL();
--
++ OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
++ OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
++ R300_COLOR_ROUND_NEAREST));
++ OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
++ R300_ALPHA0_SHADING_GOURAUD |
++ R300_RGB1_SHADING_GOURAUD |
++ R300_ALPHA1_SHADING_GOURAUD |
++ R300_RGB2_SHADING_GOURAUD |
++ R300_ALPHA2_SHADING_GOURAUD |
++ R300_RGB3_SHADING_GOURAUD |
++ R300_ALPHA3_SHADING_GOURAUD));
++ OUT_ACCEL_REG(R300_GA_OFFSET, 0);
+ FINISH_ACCEL();
+
- BEGIN_ACCEL(7);
- OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0x0);
- OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0x0);
@@ -571,15 +662,16 @@
+ (8191 << R300_SCISSOR_Y_SHIFT)));
+
+ if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS690)) {
++ /* clip has offset 1440 */
+ OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
+ (1088 << R300_CLIP_Y_SHIFT)));
-+ OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
-+ (2040 << R300_CLIP_Y_SHIFT)));
++ OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2048) << R300_CLIP_X_SHIFT) |
++ ((1080 + 2048) << R300_CLIP_Y_SHIFT)));
+ } else {
+ OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
+ (0 << R300_CLIP_Y_SHIFT)));
+ OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
-+ (2040 << R300_CLIP_Y_SHIFT)));
++ (4080 << R300_CLIP_Y_SHIFT)));
+ }
OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff);
@@ -606,7 +698,7 @@
OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
-@@ -199,11 +214,11 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
+@@ -199,11 +241,11 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
FINISH_ACCEL();
} else {
BEGIN_ACCEL(2);
@@ -623,7 +715,7 @@
OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
RADEON_VTX_ST0_NONPARAMETRIC |
-@@ -217,12 +232,12 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
+@@ -217,12 +259,12 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
@@ -674,13 +766,28 @@
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
-index 3b0c734..4ea451d 100644
+index 3b0c734..4da4841 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
-@@ -120,8 +120,6 @@ RADEONPow2(int num)
- return pot;
+@@ -105,23 +105,6 @@ RADEONLog2(int val)
+ return bits - 1;
}
+-static __inline__ int
+-RADEONPow2(int num)
+-{
+- int pot = 2;
+-
+- if (num <= 2)
+- return num;
+-
+- while (pot < num) {
+- pot *= 2;
+- }
+-
+- return pot;
+-}
+-
-
-
static __inline__ CARD32 F_TO_DW(float val)
@@ -705,10 +812,44 @@
"enabled for R300 type cards.\n");
info->exa->CheckComposite = R300CheckComposite;
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
-index 6003587..b00c013 100644
+index 6003587..9bbccb5 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
-@@ -937,6 +937,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -809,8 +809,8 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+
+ txformat1 = R300TexFormats[i].card_fmt;
+
+- txformat0 = (((RADEONPow2(w) - 1) << R300_TXWIDTH_SHIFT) |
+- ((RADEONPow2(h) - 1) << R300_TXHEIGHT_SHIFT));
++ txformat0 = (((w - 1) << R300_TXWIDTH_SHIFT) |
++ ((h - 1) << R300_TXHEIGHT_SHIFT));
+
+ if (pPict->repeat) {
+ ErrorF("repeat\n");
+@@ -822,15 +822,18 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
+ txformat0 |= R300_TXPITCH_EN;
+
+
+- info->texW[unit] = RADEONPow2(w);
+- info->texH[unit] = RADEONPow2(h);
++ info->texW[unit] = w;
++ info->texH[unit] = h;
++
++ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
++ R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST));
+
+ switch (pPict->filter) {
+ case PictFilterNearest:
+- txfilter = (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST);
++ txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST);
+ break;
+ case PictFilterBilinear:
+- txfilter = (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
++ txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
+ break;
+ default:
+ RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
+@@ -937,6 +940,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
CARD32 txenable, colorpitch;
CARD32 blendcntl;
int pixel_shift;
@@ -716,7 +857,7 @@
ACCEL_PREAMBLE();
TRACE;
-@@ -975,22 +976,216 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -975,22 +979,223 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
RADEON_SWITCH_TO_3D();
@@ -869,7 +1010,14 @@
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
-+ OUT_ACCEL_REG(R300_RS_IP_0, 0x1610000);
++ OUT_ACCEL_REG(R300_RS_IP_0,
++ (R300_RS_TEX_PTR(0) |
++ R300_RS_COL_PTR(0) |
++ R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) |
++ R300_RS_SEL_S(R300_RS_SEL_C0) |
++ R300_RS_SEL_T(R300_RS_SEL_C1) |
++ R300_RS_SEL_R(R300_RS_SEL_K0) |
++ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
+ OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
@@ -947,7 +1095,7 @@
BEGIN_ACCEL(6);
OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
-@@ -1000,7 +1195,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
+@@ -1000,7 +1205,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl);
@@ -956,7 +1104,7 @@
#if 0
/* IN operator: Multiply src by mask components or mask alpha.
-@@ -1094,8 +1289,6 @@ static inline void transformPoint(PictTransform *transform, xPointFixed *point)
+@@ -1094,8 +1299,6 @@ static inline void transformPoint(PictTransform *transform, xPointFixed *point)
}
#endif
@@ -965,7 +1113,7 @@
static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
int srcX, int srcY,
int maskX, int maskY,
-@@ -1103,7 +1296,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
+@@ -1103,7 +1306,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
int w, int h)
{
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
@@ -973,7 +1121,7 @@
int vtx_count;
xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
-@@ -1114,11 +1306,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
+@@ -1114,11 +1316,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
/* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
@@ -985,7 +1133,7 @@
srcTopLeft.x = IntToxFixed(srcX);
srcTopLeft.y = IntToxFixed(srcY);
srcTopRight.x = IntToxFixed(srcX + w);
-@@ -1152,7 +1339,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
+@@ -1152,7 +1349,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
vtx_count = VTX_COUNT;
@@ -994,7 +1142,7 @@
BEGIN_ACCEL(1);
OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
FINISH_ACCEL();
-@@ -1172,7 +1359,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
+@@ -1172,7 +1369,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
} else {
@@ -1003,7 +1151,7 @@
BEGIN_RING(4 * vtx_count + 6);
else
BEGIN_RING(4 * vtx_count + 2);
-@@ -1185,7 +1372,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
+@@ -1185,7 +1382,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
}
#else /* ACCEL_CP */
@@ -1012,7 +1160,7 @@
BEGIN_ACCEL(3 + vtx_count * 4);
else
BEGIN_ACCEL(1 + vtx_count * 4);
-@@ -1202,29 +1389,21 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
+@@ -1202,29 +1399,21 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
}
#endif
@@ -1057,7 +1205,7 @@
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
}
-@@ -1237,7 +1416,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
+@@ -1237,7 +1426,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
LEAVE_DRAW(0);
}
#undef VTX_OUT
@@ -1065,7 +1213,7 @@
#ifdef ONLY_ONCE
static void RadeonDoneComposite(PixmapPtr pDst)
-@@ -1248,3 +1426,4 @@ static void RadeonDoneComposite(PixmapPtr pDst)
+@@ -1248,3 +1436,4 @@ static void RadeonDoneComposite(PixmapPtr pDst)
#endif /* ONLY_ONCE */
#undef ONLY_ONCE
@@ -1142,14 +1290,18 @@
typedef enum
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
-index 61cdb15..893fca4 100644
+index 61cdb15..046c52b 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
-@@ -3819,50 +3819,225 @@
+@@ -3819,53 +3819,265 @@
#define R600_BIOS_7_SCRATCH 0x1740
#define R300_GB_TILE_CONFIG 0x4018
-+# define R300_ENABLE_TILING (1 << 1)
++# define R300_ENABLE_TILING (1 << 0)
++# define R300_PIPE_COUNT_RV350 (0 << 1)
++# define R300_PIPE_COUNT_R300 (3 << 1)
++# define R300_PIPE_COUNT_R420_3P (6 << 1)
++# define R300_PIPE_COUNT_R420 (7 << 1)
+# define R300_TILE_SIZE_8 (0 << 4)
+# define R300_TILE_SIZE_16 (1 << 4)
+# define R300_TILE_SIZE_32 (2 << 4)
@@ -1362,6 +1514,28 @@
+# define R300_RS_COUNT_HIRES_EN (1 << 18)
+
#define R300_RS_IP_0 0x4310
++# define R300_RS_TEX_PTR(x) (x << 0)
++# define R300_RS_COL_PTR(x) (x << 6)
++# define R300_RS_COL_FMT(x) (x << 9)
++# define R300_RS_COL_FMT_RGBA 0
++# define R300_RS_COL_FMT_RGB0 2
++# define R300_RS_COL_FMT_RGB1 3
++# define R300_RS_COL_FMT_000A 4
++# define R300_RS_COL_FMT_0000 5
++# define R300_RS_COL_FMT_0001 6
++# define R300_RS_COL_FMT_111A 8
++# define R300_RS_COL_FMT_1110 9
++# define R300_RS_COL_FMT_1111 10
++# define R300_RS_SEL_S(x) (x << 13)
++# define R300_RS_SEL_T(x) (x << 16)
++# define R300_RS_SEL_R(x) (x << 19)
++# define R300_RS_SEL_Q(x) (x << 22)
++# define R300_RS_SEL_C0 0
++# define R300_RS_SEL_C1 1
++# define R300_RS_SEL_C2 2
++# define R300_RS_SEL_C3 3
++# define R300_RS_SEL_K0 4
++# define R300_RS_SEL_K1 5
#define R300_RS_INST_COUNT 0x4304
+# define R300_INST_COUNT_RS(x) (x << 0)
+# define R300_RS_W_EN (1 << 4)
@@ -1371,7 +1545,21 @@
#define R300_TX_INVALTAGS 0x4100
#define R300_TX_FILTER0_0 0x4400
-@@ -3901,6 +4076,8 @@
++# define R300_TX_CLAMP_S(x) (x << 0)
++# define R300_TX_CLAMP_T(x) (x << 3)
++# define R300_TX_CLAMP_R(x) (x << 6)
++# define R300_TX_CLAMP_WRAP 0
++# define R300_TX_CLAMP_MIRROR 1
++# define R300_TX_CLAMP_CLAMP_LAST 2
++# define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3
++# define R300_TX_CLAMP_CLAMP_BORDER 4
++# define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5
++# define R300_TX_CLAMP_CLAMP_GL 6
++# define R300_TX_CLAMP_MIRROR_CLAMP_GL 7
+ # define R300_TX_MAG_FILTER_NEAREST (1 << 9)
+ # define R300_TX_MIN_FILTER_NEAREST (1 << 11)
+ # define R300_TX_MAG_FILTER_LINEAR (2 << 9)
+@@ -3901,6 +4113,8 @@
# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
@@ -1380,7 +1568,7 @@
# define R300_TX_FORMAT_X24_Y8 0x1e
# define R300_TX_FORMAT_X32 0x1e
/* Floating point formats */
-@@ -3945,6 +4122,10 @@
+@@ -3945,6 +4159,10 @@
| (R300_TX_FORMAT_##FMT) \
)
@@ -1391,7 +1579,7 @@
#define R300_TX_FORMAT2_0 0x4500
#define R300_TX_OFFSET_0 0x4540
# define R300_ENDIAN_SWAP_16_BIT (1 << 0)
-@@ -3961,9 +4142,53 @@
+@@ -3961,9 +4179,53 @@
#define R300_US_OUT_FMT_2 0x46ac
#define R300_US_OUT_FMT_3 0x46b0
#define R300_US_OUT_FMT_0 0x46a4
@@ -1445,7 +1633,7 @@
#define R300_US_CODE_ADDR_0 0x4610
#define R300_US_CODE_ADDR_1 0x4614
#define R300_US_CODE_ADDR_2 0x4618
-@@ -3979,8 +4204,14 @@
+@@ -3979,8 +4241,14 @@
#define R300_FG_ALPHA_FUNC 0x4bd4
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
@@ -1460,7 +1648,7 @@
#define R300_RB3D_ZSTENCILCNTL 0x4f04
#define R300_RB3D_ZCACHE_CTLSTAT 0x4f18
#define R300_RB3D_BW_CNTL 0x4f1c
-@@ -4009,6 +4240,10 @@
+@@ -4009,6 +4277,10 @@
#define R300_RB3D_AARESOLVE_CTL 0x4e88
#define R300_RB3D_COLOR_CHANNEL_MASK 0x4e0c
@@ -1471,7 +1659,7 @@
#define R300_RB3D_COLOR_CLEAR_VALUE 0x4e14
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
#define R300_RB3D_CCTL 0x4e00
-@@ -4017,9 +4252,524 @@
+@@ -4017,9 +4289,524 @@
#define R300_SC_EDGERULE 0x43a8
#define R300_SC_SCISSOR0 0x43e0
#define R300_SC_SCISSOR1 0x43e4
@@ -1998,10 +2186,10 @@
#endif
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
new file mode 100644
-index 0000000..8a14024
+index 0000000..329a834
--- /dev/null
+++ b/src/radeon_textured_video.c
-@@ -0,0 +1,596 @@
+@@ -0,0 +1,383 @@
+/*
+ * Copyright 2008 Alex Deucher
+ *
@@ -2071,21 +2259,6 @@
+ }
+}
+
-+static __inline__ int
-+RADEONPow2(int num)
-+{
-+ int pot = 2;
-+
-+ if (num <= 2)
-+ return num;
-+
-+ while (pot < num) {
-+ pot *= 2;
-+ }
-+
-+ return pot;
-+}
-+
+static __inline__ CARD32 F_TO_DW(float val)
+{
+ union {
@@ -2126,147 +2299,6 @@
+
+#endif /* XF86DRI */
+
-+static void
-+RADEONXVCopyPlanarData(CARD8 *src, CARD8 *dst, int randr,
-+ int srcPitch, int srcPitch2, int dstPitch,
-+ int srcW, int srcH, int height,
-+ int top, int left, int h, int w, int id)
-+{
-+ int i, j;
-+ CARD8 *src1, *src2, *src3, *dst1;
-+ int srcDown = srcPitch, srcDown2 = srcPitch2;
-+ int srcRight = 2, srcRight2 = 1, srcNext = 1;
-+
-+ /* compute source data pointers */
-+ src1 = src;
-+ src2 = src1 + height * srcPitch;
-+ src3 = src2 + (height >> 1) * srcPitch2;
-+ switch (randr) {
-+ case RR_Rotate_0:
-+ srcDown = srcPitch;
-+ srcDown2 = srcPitch2;
-+ srcRight = 2;
-+ srcRight2 = 1;
-+ srcNext = 1;
-+ break;
-+ case RR_Rotate_90:
-+ src1 = src1 + srcH - 1;
-+ src2 = src2 + (srcH >> 1) - 1;
-+ src3 = src3 + (srcH >> 1) - 1;
-+ srcDown = -1;
-+ srcDown2 = -1;
-+ srcRight = srcPitch * 2;
-+ srcRight2 = srcPitch2;
-+ srcNext = srcPitch;
-+ break;
-+ case RR_Rotate_180:
-+ src1 = src1 + srcPitch * (srcH - 1) + (srcW - 1);
-+ src2 = src2 + srcPitch2 * ((srcH >> 1) - 1) + ((srcW >> 1) - 1);
-+ src3 = src3 + srcPitch2 * ((srcH >> 1) - 1) + ((srcW >> 1) - 1);
-+ srcDown = -srcPitch;
-+ srcDown2 = -srcPitch2;
-+ srcRight = -2;
-+ srcRight2 = -1;
-+ srcNext = -1;
-+ break;
-+ case RR_Rotate_270:
-+ src1 = src1 + srcPitch * (srcW - 1);
-+ src2 = src2 + srcPitch2 * ((srcW >> 1) - 1);
-+ src3 = src3 + srcPitch2 * ((srcW >> 1) - 1);
-+ srcDown = 1;
-+ srcDown2 = 1;
-+ srcRight = -srcPitch * 2;
-+ srcRight2 = -srcPitch2;
-+ srcNext = -srcPitch;
-+ break;
-+ }
-+
-+ /* adjust for origin */
-+ src1 += top * srcDown + left * srcNext;
-+ src2 += (top >> 1) * srcDown2 + (left >> 1) * srcRight2;
-+ src3 += (top >> 1) * srcDown2 + (left >> 1) * srcRight2;
-+
-+ if (id == FOURCC_I420) {
-+ CARD8 *srct = src2;
-+ src2 = src3;
-+ src3 = srct;
-+ }
-+
-+ dst1 = dst;
-+
-+ w >>= 1;
-+ for (j = 0; j < h; j++) {
-+ CARD32 *dst = (CARD32 *)dst1;
-+ CARD8 *s1l = src1;
-+ CARD8 *s1r = src1 + srcNext;
-+ CARD8 *s2 = src2;
-+ CARD8 *s3 = src3;
-+
-+ for (i = 0; i < w; i++) {
-+ *dst++ = *s1l | (*s1r << 16) | (*s3 << 8) | (*s2 << 24);
-+ s1l += srcRight;
-+ s1r += srcRight;
-+ s2 += srcRight2;
-+ s3 += srcRight2;
-+ }
-+ src1 += srcDown;
-+ dst1 += dstPitch;
-+ if (j & 1) {
-+ src2 += srcDown2;
-+ src3 += srcDown2;
-+ }
-+ }
-+}
-+
-+static void
-+RADEONXVCopyPackedData(CARD8 *src, CARD8 *dst, int randr,
-+ int srcPitch, int dstPitch,
-+ int srcW, int srcH, int top, int left,
-+ int h, int w)
-+{
-+ int srcDown = srcPitch, srcRight = 2, srcNext;
-+ int p;
-+
-+ switch (randr) {
-+ case RR_Rotate_0:
-+ srcDown = srcPitch;
-+ srcRight = 2;
-+ break;
-+ case RR_Rotate_90:
-+ src += (srcH - 1) * 2;
-+ srcDown = -2;
-+ srcRight = srcPitch;
-+ break;
-+ case RR_Rotate_180:
-+ src += srcPitch * (srcH - 1) + (srcW - 1) * 2;
-+ srcDown = -srcPitch;
-+ srcRight = -2;
-+ break;
-+ case RR_Rotate_270:
-+ src += srcPitch * (srcW - 1);
-+ srcDown = 2;
-+ srcRight = -srcPitch;
-+ break;
-+ }
-+
-+ src = src + top * srcDown + left * srcRight;
-+
-+ w >>= 1;
-+ /* srcRight >>= 1; */
-+ srcNext = srcRight >> 1;
-+ while (h--) {
-+ CARD16 *s = (CARD16 *)src;
-+ CARD32 *d = (CARD32 *)dst;
-+ p = w;
-+ while (p--) {
-+ *d++ = s[0] | (s[srcNext] << 16);
-+ s += srcRight;
-+ }
-+ src += srcPitch;
-+ dst += dstPitch;
-+ }
-+}
-+
+static int
+RADEONPutImageTextured(ScrnInfoPtr pScrn,
+ short src_x, short src_y,
@@ -2286,14 +2318,14 @@
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data;
+ INT32 x1, x2, y1, y2;
-+ int randr = RR_Rotate_0 /* XXX */;
+ int srcPitch, srcPitch2, dstPitch;
++ int s2offset, s3offset, tmp;
+ int top, left, npixels, nlines, size;
+ BoxRec dstBox;
+ int dst_width = width, dst_height = height;
-+ int rot_x1, rot_y1, rot_x2, rot_y2;
-+ int dst_x1, dst_y1, dst_x2, dst_y2;
-+ int rot_src_w, rot_src_h, rot_drw_w, rot_drw_h;
++
++ /* make the compiler happy */
++ s2offset = s3offset = srcPitch2 = 0;
+
+ /* Clip */
+ x1 = src_x;
@@ -2317,66 +2349,6 @@
+ if ((x1 >= x2) || (y1 >= y2))
+ return Success;
+
-+ if (randr & (RR_Rotate_0|RR_Rotate_180)) {
-+ dst_width = width;
-+ dst_height = height;
-+ rot_src_w = src_w;
-+ rot_src_h = src_h;
-+ rot_drw_w = drw_w;
-+ rot_drw_h = drw_h;
-+ } else {
-+ dst_width = height;
-+ dst_height = width;
-+ rot_src_w = src_h;
-+ rot_src_h = src_w;
-+ rot_drw_w = drw_h;
-+ rot_drw_h = drw_w;
-+ }
-+
-+ switch (randr) {
-+ case RR_Rotate_0:
-+ default:
-+ dst_x1 = dstBox.x1;
-+ dst_y1 = dstBox.y1;
-+ dst_x2 = dstBox.x2;
-+ dst_y2 = dstBox.y2;
-+ rot_x1 = x1;
-+ rot_y1 = y1;
-+ rot_x2 = x2;
-+ rot_y2 = y2;
-+ break;
-+ case RR_Rotate_90:
-+ dst_x1 = dstBox.y1;
-+ dst_y1 = pScrn->virtualY - dstBox.x2;
-+ dst_x2 = dstBox.y2;
-+ dst_y2 = pScrn->virtualY - dstBox.x1;
-+ rot_x1 = y1;
-+ rot_y1 = (src_w << 16) - x2;
-+ rot_x2 = y2;
-+ rot_y2 = (src_w << 16) - x1;
-+ break;
-+ case RR_Rotate_180:
-+ dst_x1 = pScrn->virtualX - dstBox.x2;
-+ dst_y1 = pScrn->virtualY - dstBox.y2;
-+ dst_x2 = pScrn->virtualX - dstBox.x1;
-+ dst_y2 = pScrn->virtualY - dstBox.y1;
-+ rot_x1 = (src_w << 16) - x2;
-+ rot_y1 = (src_h << 16) - y2;
-+ rot_x2 = (src_w << 16) - x1;
-+ rot_y2 = (src_h << 16) - y1;
-+ break;
-+ case RR_Rotate_270:
-+ dst_x1 = pScrn->virtualX - dstBox.y2;
-+ dst_y1 = dstBox.x1;
-+ dst_x2 = pScrn->virtualX - dstBox.y1;
-+ dst_y2 = dstBox.x2;
-+ rot_x1 = (src_h << 16) - y2;
-+ rot_y1 = x1;
-+ rot_x2 = (src_h << 16) - y1;
-+ rot_y2 = x2;
-+ break;
-+ }
-+
+ switch(id) {
+ case FOURCC_YV12:
+ case FOURCC_I420:
@@ -2395,6 +2367,14 @@
+ break;
+ }
+
++#ifdef XF86DRI
++ if (info->directRenderingEnabled && info->DMAForXv)
++ /* The upload blit only supports multiples of 64 bytes */
++ dstPitch = (dstPitch + 63) & ~63;
++ else
++#endif
++ dstPitch = (dstPitch + 15) & ~15;
++
+ if (pPriv->video_memory != NULL && size != pPriv->size) {
+ RADEONFreeMemory(pScrn, pPriv->video_memory);
+ pPriv->video_memory = NULL;
@@ -2430,8 +2410,13 @@
+ return BadAlloc;
+ }
+
++ /* copy data */
++ top = y1 >> 16;
++ left = (x1 >> 16) & ~1;
++ npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left;
++
+ pPriv->src_offset = pPriv->video_offset + info->fbLocation;
-+ pPriv->src_addr = (CARD8 *)(info->FB + pPriv->video_offset);
++ pPriv->src_addr = (CARD8 *)(info->FB + pPriv->video_offset + (top * dstPitch));
+ pPriv->src_pitch = dstPitch;
+ pPriv->size = size;
+ pPriv->pDraw = pDraw;
@@ -2442,38 +2427,32 @@
+ ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch);
+#endif
+
-+ /* copy data */
-+ top = rot_y1 >> 16;
-+ left = (rot_x1 >> 16) & ~1;
-+ npixels = ((((rot_x2 + 0xffff) >> 16) + 1) & ~1) - left;
-+
-+ /* Since we're probably overwriting the area that might still be used
-+ * for the last PutImage request, wait for idle.
-+ */
-+#ifdef XF86DRI
-+ if (info->directRenderingEnabled)
-+ RADEONWaitForIdleCP(pScrn);
-+ else
-+#endif
-+ RADEONWaitForIdleMMIO(pScrn);
-+
-+
+ switch(id) {
+ case FOURCC_YV12:
+ case FOURCC_I420:
+ top &= ~1;
-+ nlines = ((((rot_y2 + 0xffff) >> 16) + 1) & ~1) - top;
-+ RADEONXVCopyPlanarData(buf, pPriv->src_addr, randr,
-+ srcPitch, srcPitch2, dstPitch, rot_src_w, rot_src_h,
-+ height, top, left, nlines, npixels, id);
++ nlines = ((((y2 + 0xffff) >> 16) + 1) & ~1) - top;
++ s2offset = srcPitch * height;
++ s3offset = (srcPitch2 * (height >> 1)) + s2offset;
++ top &= ~1;
++ pPriv->src_addr += left << 1;
++ tmp = ((top >> 1) * srcPitch2) + (left >> 1);
++ s2offset += tmp;
++ s3offset += tmp;
++ if (id == FOURCC_I420) {
++ tmp = s2offset;
++ s2offset = s3offset;
++ s3offset = tmp;
++ }
++ RADEONCopyMungedData(pScrn, buf + (top * srcPitch) + left,
++ buf + s2offset, buf + s3offset, pPriv->src_addr,
++ srcPitch, srcPitch2, dstPitch, nlines, npixels);
+ break;
+ case FOURCC_UYVY:
+ case FOURCC_YUY2:
+ default:
-+ nlines = ((rot_y2 + 0xffff) >> 16) - top;
-+ RADEONXVCopyPackedData(buf, pPriv->src_addr, randr,
-+ srcPitch, dstPitch, rot_src_w, rot_src_h, top, left,
-+ nlines, npixels);
++ nlines = ((y2 + 0xffff) >> 16) - top;
++ RADEONCopyData(pScrn, buf, pPriv->src_addr, srcPitch, dstPitch, nlines, npixels, 2);
+ break;
+ }
+
@@ -2483,18 +2462,14 @@
+ }
+
+ pPriv->id = id;
-+ pPriv->src_x1 = rot_x1;
-+ pPriv->src_y1 = rot_y1;
-+ pPriv->src_x2 = rot_x2;
-+ pPriv->src_y2 = rot_y2;
-+ pPriv->src_w = rot_src_w;
-+ pPriv->src_h = rot_src_h;
-+ pPriv->dst_x1 = dst_x1;
-+ pPriv->dst_y1 = dst_y1;
-+ pPriv->dst_x2 = dst_x2;
-+ pPriv->dst_y2 = dst_y2;
-+ pPriv->dst_w = rot_drw_w;
-+ pPriv->dst_h = rot_drw_h;
++ pPriv->src_w = src_w;
++ pPriv->src_h = src_h;
++ pPriv->drw_x = drw_x;
++ pPriv->drw_y = drw_y;
++ pPriv->dst_w = drw_w;
++ pPriv->dst_h = drw_h;
++ pPriv->w = width;
++ pPriv->h = height;
+
+#ifdef XF86DRI
+ if (info->directRenderingEnabled)
@@ -2600,10 +2575,10 @@
+
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
new file mode 100644
-index 0000000..36951d5
+index 0000000..e0f3bba
--- /dev/null
+++ b/src/radeon_textured_videofuncs.c
-@@ -0,0 +1,523 @@
+@@ -0,0 +1,596 @@
+/*
+ * Copyright 2008 Alex Deucher
+ *
@@ -2627,7 +2602,7 @@
+ * SOFTWARE.
+ *
+ *
-+ * Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt
++ * Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt, et al.
+ *
+ */
+
@@ -2734,7 +2709,8 @@
+ FINISH_VIDEO();
+
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
-+ int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400);
++ int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400);
++
+ switch (pPixmap->drawable.bitsPerPixel) {
+ case 16:
+ if (pPixmap->drawable.depth == 15)
@@ -2762,25 +2738,27 @@
+
+ txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP;
+
-+ txformat0 = (((RADEONPow2(pPriv->src_w) - 1) << R300_TXWIDTH_SHIFT) |
-+ ((RADEONPow2(pPriv->src_h) - 1) << R300_TXHEIGHT_SHIFT));
++ txformat0 = (((pPriv->w - 1) << R300_TXWIDTH_SHIFT) |
++ ((pPriv->h - 1) << R300_TXHEIGHT_SHIFT));
+
+ txformat0 |= R300_TXPITCH_EN;
+
-+ info->texW[0] = RADEONPow2(pPriv->src_w);
-+ info->texH[0] = RADEONPow2(pPriv->src_h);
++ info->texW[0] = pPriv->w;
++ info->texH[0] = pPriv->h;
+
-+ txfilter = (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
++ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
++ R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) |
++ R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
+
-+ txpitch = pPriv->src_w * 4;
-+ txpitch >>= pixel_shift;
++ /* pitch is in pixels */
++ txpitch = pPriv->src_pitch / 2;
+ txpitch -= 1;
+
+ txoffset = pPriv->src_offset;
+
+ BEGIN_VIDEO(6);
+ OUT_VIDEO_REG(R300_TX_FILTER0_0, txfilter);
-+ OUT_VIDEO_REG(R300_TX_FILTER1_0, 0x0);
++ OUT_VIDEO_REG(R300_TX_FILTER1_0, 0);
+ OUT_VIDEO_REG(R300_TX_FORMAT0_0, txformat0);
+ OUT_VIDEO_REG(R300_TX_FORMAT1_0, txformat1);
+ OUT_VIDEO_REG(R300_TX_FORMAT2_0, txpitch);
@@ -2789,32 +2767,85 @@
+
+ txenable = R300_TEX_0_ENABLE;
+
-+ /* setup vertex shader */
++ /* setup the VAP */
+ if (has_tcl) {
+ BEGIN_VIDEO(26);
-+ OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0x0);
-+ OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
-+ OUT_VIDEO_REG(R300_VAP_CNTL, 0x300456);
++ OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0);
++ OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
++ OUT_VIDEO_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
++ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
++ (4 << R300_PVS_NUM_FPUS_SHIFT) |
++ (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
+ } else {
+ BEGIN_VIDEO(8);
-+ OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 1<<8);
-+ OUT_VIDEO_REG(R300_VAP_CNTL, 0x14045a);
++ OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
++ OUT_VIDEO_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
++ (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
++ (4 << R300_PVS_NUM_FPUS_SHIFT) |
++ (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
+ }
+
-+ OUT_VIDEO_REG(R300_VAP_VTE_CNTL, 0x300);
-+ OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0x0);
-+
++ OUT_VIDEO_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
++ OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
++
+ if (has_tcl) {
-+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x6a014001);
-+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688);
++ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
++ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
++ (0 << R300_SKIP_DWORDS_0_SHIFT) |
++ (0 << R300_DST_VEC_LOC_0_SHIFT) |
++ R300_SIGNED_0 |
++ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
++ (0 << R300_SKIP_DWORDS_1_SHIFT) |
++ (10 << R300_DST_VEC_LOC_1_SHIFT) |
++ R300_LAST_VEC_1 |
++ R300_SIGNED_1));
++ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
++ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
++ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
++ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
++ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
++ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
++ << R300_WRITE_ENA_0_SHIFT) |
++ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
++ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
++ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
++ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
++ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
++ << R300_WRITE_ENA_1_SHIFT)));
+ } else {
-+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x66014001);
-+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0x3b083b08);
++ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
++ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
++ (0 << R300_SKIP_DWORDS_0_SHIFT) |
++ (0 << R300_DST_VEC_LOC_0_SHIFT) |
++ R300_SIGNED_0 |
++ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
++ (0 << R300_SKIP_DWORDS_1_SHIFT) |
++ (6 << R300_DST_VEC_LOC_1_SHIFT) |
++ R300_LAST_VEC_1 |
++ R300_SIGNED_1));
++ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
++ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
++ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
++ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
++ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
++ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
++ << R300_WRITE_ENA_0_SHIFT) |
++ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
++ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
++ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
++ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
++ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
++ << R300_WRITE_ENA_1_SHIFT)));
+ }
+
++ /* setup vertex shader */
+ if (has_tcl) {
-+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400);
-+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1);
++ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
++ ((0 << R300_PVS_FIRST_INST_SHIFT) |
++ (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
++ (1 << R300_PVS_LAST_INST_SHIFT)));
++ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
++ (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
@@ -2824,33 +2855,46 @@
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
-+ OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0);
++ OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
+
+
+ OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
+ OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
+ OUT_VIDEO_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
+ OUT_VIDEO_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
-+ OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, 0x10000);
++ OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
+ }
+
-+ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, 0x1);
-+ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, 0x2);
++ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
++ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
+ FINISH_VIDEO();
+
+ /* setup pixel shader */
+ if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
+ BEGIN_VIDEO(16);
-+ OUT_VIDEO_REG(R300_RS_COUNT, 0x40002);
-+ OUT_VIDEO_REG(R300_RS_IP_0, 0x1610000);
-+ OUT_VIDEO_REG(R300_RS_INST_COUNT, 0xC0);
++ OUT_VIDEO_REG(R300_RS_COUNT,
++ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
++ R300_RS_COUNT_HIRES_EN));
++ OUT_VIDEO_REG(R300_RS_IP_0,
++ (R300_RS_TEX_PTR(0) |
++ R300_RS_COL_PTR(0) |
++ R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) |
++ R300_RS_SEL_S(R300_RS_SEL_C0) |
++ R300_RS_SEL_T(R300_RS_SEL_C1) |
++ R300_RS_SEL_R(R300_RS_SEL_K0) |
++ R300_RS_SEL_Q(R300_RS_SEL_K1)));
++ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
+ OUT_VIDEO_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
-+ OUT_VIDEO_REG(R300_US_CONFIG, 0x8);
-+ OUT_VIDEO_REG(R300_US_PIXSIZE, 0x0);
-+ OUT_VIDEO_REG(R300_US_CODE_OFFSET, 0x40040);
-+ OUT_VIDEO_REG(R300_US_CODE_ADDR_0, 0x0);
-+ OUT_VIDEO_REG(R300_US_CODE_ADDR_1, 0x0);
-+ OUT_VIDEO_REG(R300_US_CODE_ADDR_2, 0x0);
++ OUT_VIDEO_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
++ OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
++ OUT_VIDEO_REG(R300_US_CODE_OFFSET,
++ (R300_ALU_CODE_OFFSET(0) |
++ R300_ALU_CODE_SIZE(1) |
++ R300_TEX_CODE_OFFSET(0) |
++ R300_TEX_CODE_SIZE(1)));
++ OUT_VIDEO_REG(R300_US_CODE_ADDR_0, 0);
++ OUT_VIDEO_REG(R300_US_CODE_ADDR_1, 0);
++ OUT_VIDEO_REG(R300_US_CODE_ADDR_2, 0);
+ OUT_VIDEO_REG(R300_US_CODE_ADDR_3, 0x400000);
+ OUT_VIDEO_REG(R300_US_TEX_INST_0, 0x8000);
+ OUT_VIDEO_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000);
@@ -2860,19 +2904,21 @@
+ FINISH_VIDEO();
+ } else {
+ BEGIN_VIDEO(22);
-+ OUT_VIDEO_REG(R300_RS_COUNT, 0x40002);
++ OUT_VIDEO_REG(R300_RS_COUNT,
++ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
++ R300_RS_COUNT_HIRES_EN));
+ OUT_VIDEO_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
-+
-+ OUT_VIDEO_REG(R300_RS_INST_COUNT, 0x0);
++
++ OUT_VIDEO_REG(R300_RS_INST_COUNT, 0);
+ OUT_VIDEO_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
-+ OUT_VIDEO_REG(R300_US_CONFIG, 0x2);
-+ OUT_VIDEO_REG(R300_US_PIXSIZE, 0x0);
-+ OUT_VIDEO_REG(R500_US_FC_CTRL, 0x0);
-+ OUT_VIDEO_REG(R500_US_CODE_ADDR, 0x10000);
-+ OUT_VIDEO_REG(R500_US_CODE_RANGE, 0x10000);
-+ OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0x0);
-+ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0x0);
++ OUT_VIDEO_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
++ OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
++ OUT_VIDEO_REG(R500_US_FC_CTRL, 0);
++ OUT_VIDEO_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
++ OUT_VIDEO_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
++ OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
++ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00007807);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x06400000);
+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0xe4000400);
@@ -2889,7 +2935,7 @@
+ }
+
+ BEGIN_VIDEO(6);
-+ OUT_VIDEO_REG(R300_TX_INVALTAGS, 0x0);
++ OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
+ OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
+
+ OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, dst_offset);
@@ -2897,7 +2943,7 @@
+
+ blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO;
+ OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl);
-+ OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0x0);
++ OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0);
+ FINISH_VIDEO();
+
+ BEGIN_VIDEO(1);
@@ -2954,8 +3000,8 @@
+ (info->ChipFamily == CHIP_FAMILY_RS300) ||
+ (info->ChipFamily == CHIP_FAMILY_R200)) {
+
-+ info->texW[0] = pPriv->src_w;
-+ info->texH[0] = pPriv->src_h;
++ info->texW[0] = pPriv->w;
++ info->texH[0] = pPriv->h;
+
+ BEGIN_VIDEO(12);
+
@@ -2970,8 +3016,8 @@
+ OUT_VIDEO_REG(R200_PP_TXFORMAT_0, txformat);
+ OUT_VIDEO_REG(R200_PP_TXFORMAT_X_0, 0);
+ OUT_VIDEO_REG(R200_PP_TXSIZE_0,
-+ (pPriv->src_w - 1) |
-+ ((pPriv->src_h - 1) << RADEON_TEX_VSIZE_SHIFT));
++ (pPriv->w - 1) |
++ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
+ OUT_VIDEO_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
+
+ OUT_VIDEO_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
@@ -3020,8 +3066,8 @@
+ RADEON_CLAMP_TX);
+
+ OUT_VIDEO_REG(RADEON_PP_TEX_SIZE_0,
-+ (pPriv->src_w - 1) |
-+ ((pPriv->src_h - 1) << RADEON_TEX_VSIZE_SHIFT));
++ (pPriv->w - 1) |
++ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
+ OUT_VIDEO_REG(RADEON_PP_TEX_PITCH_0,
+ pPriv->src_pitch - 32);
+ FINISH_VIDEO();
@@ -3036,10 +3082,11 @@
+ dstY = pBox->y1 + dstyoff;
+ dstw = pBox->x2 - pBox->x1;
+ dsth = pBox->y2 - pBox->y1;
-+ srcX = (pBox->x1 - pPriv->dst_x1) *
-+ pPriv->src_w / pPriv->dst_w;
-+ srcY = (pBox->y1 - pPriv->dst_y1) *
-+ pPriv->src_h / pPriv->dst_h;
++
++ srcX = ((pBox->x1 - pPriv->drw_x) *
++ pPriv->src_w) / pPriv->dst_w;
++ srcY = ((pBox->y1 - pPriv->drw_y) *
++ pPriv->src_h) / pPriv->dst_h;
+
+ srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
+ srch = (pPriv->src_h * dsth) / pPriv->dst_h;
@@ -3053,6 +3100,7 @@
+ srcBottomRight.x = IntToxFixed(srcX + srcw);
+ srcBottomRight.y = IntToxFixed(srcY + srch);
+
++
+#if 0
+ ErrorF("dst: %d, %d, %d, %d\n", dstX, dstY, dstw, dsth);
+ ErrorF("src: %d, %d, %d, %d\n", srcX, srcY, srcw, srch);
@@ -3109,7 +3157,7 @@
+ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]);
+
+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
-+ OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
++ OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
+ OUT_VIDEO_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+ }
+
@@ -3128,7 +3176,7 @@
+#undef VTX_OUT
+#undef FUNC_NAME
diff --git a/src/radeon_video.c b/src/radeon_video.c
-index 0b3f6ca..487f064 100644
+index 0b3f6ca..7502e1e 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -74,19 +74,10 @@
@@ -3308,6 +3356,24 @@
*p_w = drw_w;
*p_h = drw_h;
+@@ -2132,7 +2147,7 @@ static struct {
+ {1.00, {{ 0, 32, 0, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-4, 24, 14, -2}, {-3, 19, 19, -3}, }}
+ };
+
+-static void
++void
+ RADEONCopyData(
+ ScrnInfoPtr pScrn,
+ unsigned char *src,
+@@ -2300,7 +2315,7 @@ static void RADEON_420_422(
+ }
+ #endif
+
+-static void
++void
+ RADEONCopyMungedData(
+ ScrnInfoPtr pScrn,
+ unsigned char *src1,
@@ -2405,7 +2420,7 @@ RADEONCopyMungedData(
* is measured in bytes, and the offset from the beginning of card space is
* returned.
@@ -3336,7 +3402,7 @@
ScrnInfoPtr pScrn,
int id,
diff --git a/src/radeon_video.h b/src/radeon_video.h
-index 072f40e..a9e9e7d 100644
+index 072f40e..f897e07 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -81,8 +81,8 @@ typedef struct {
@@ -3364,13 +3430,13 @@
+ CARD8 *src_addr;
+
+ int id;
-+ int src_x1, src_y1, src_x2, src_y2;
-+ int dst_x1, dst_y1, dst_x2, dst_y2;
+ int src_w, src_h, dst_w, dst_h;
++ int w, h;
++ int drw_x, drw_y;
} RADEONPortPrivRec, *RADEONPortPrivPtr;
-@@ -99,5 +113,20 @@ void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
+@@ -99,5 +113,33 @@ void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
@@ -3389,5 +3455,18 @@
+
+XF86VideoAdaptorPtr
+RADEONSetupImageTexturedVideo(ScreenPtr pScreen);
++
++void
++RADEONCopyData(ScrnInfoPtr pScrn,
++ unsigned char *src, unsigned char *dst,
++ unsigned int srcPitch, unsigned int dstPitch,
++ unsigned int h, unsigned int w, unsigned int bpp);
++
++void
++RADEONCopyMungedData(ScrnInfoPtr pScrn,
++ unsigned char *src1, unsigned char *src2,
++ unsigned char *src3, unsigned char *dst1,
++ unsigned int srcPitch, unsigned int srcPitch2,
++ unsigned int dstPitch, unsigned int h, unsigned int w);
#endif
Index: xorg-x11-drv-ati.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/F-8/xorg-x11-drv-ati.spec,v
retrieving revision 1.76
retrieving revision 1.77
diff -u -r1.76 -r1.77
--- xorg-x11-drv-ati.spec 26 Feb 2008 08:52:29 -0000 1.76
+++ xorg-x11-drv-ati.spec 31 Mar 2008 01:54:02 -0000 1.77
@@ -5,7 +5,7 @@
Summary: Xorg X11 ati video driver
Name: xorg-x11-drv-ati
Version: 6.8.0
-Release: 1%{?dist}
+Release: 2%{?dist}
URL: http://www.x.org
License: MIT
Group: User Interface/X Hardware Support
@@ -18,9 +18,12 @@
# Radeon patches (0-99)
Patch3: radeon-git-upstream-fixes.patch
+Patch4: radeon-git-upstream-fixes2.patch
+
# Rage 128 patches (100-199)
# mach64 patches (200-299)
+Patch200: mach64-ia64-pagesize.patch
# ati wrapperloader patches (300-399)
@@ -42,6 +45,8 @@
%setup -q -n %{tarball}-%{version}
%patch3 -p1 -b .fixes
+%patch4 -p1 -b .fixes2
+%patch200 -p1 -b .ia64
%build
aclocal ; automake -a ; autoconf
@@ -83,6 +88,9 @@
%{_mandir}/man4/radeon.4*
%changelog
+* Mon Mar 31 2008 Dave Airlie <airlied at redhat.com> 6.8.0-2
+- rebase to latest git tree
+
* Thu Feb 26 2008 Dave Airlie <airlied at redhat.com> 6.8.0-1
- rebase to 6.8.0 + git fixes
- Previous message (by thread): rpms/ltsp/devel .cvsignore,1.3,1.4 sources,1.7,1.8
- Next message (by thread): devel/anaconda .cvsignore, 1.520, 1.521 anaconda.spec, 1.660, 1.661 sources, 1.652, 1.653
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