rpms/kernel/F-10 drm-modesetting-radeon.patch, 1.49, 1.50 kernel.spec, 1.1123, 1.1124
Dave Airlie
airlied at fedoraproject.org
Sat Nov 8 04:49:48 UTC 2008
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Author: airlied
Update of /cvs/pkgs/rpms/kernel/F-10
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv14014
Modified Files:
drm-modesetting-radeon.patch kernel.spec
Log Message:
- radeon modesetting - fix mouse on second head and 3 second hangs hopefully
drm-modesetting-radeon.patch:
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-10/drm-modesetting-radeon.patch,v
retrieving revision 1.49
retrieving revision 1.50
diff -u -r1.49 -r1.50
--- drm-modesetting-radeon.patch 3 Nov 2008 01:28:04 -0000 1.49
+++ drm-modesetting-radeon.patch 8 Nov 2008 04:49:47 -0000 1.50
@@ -1,3 +1,66 @@
+commit 92c626a8e7c8c61c80acf3c687f4d7dbacc6f354
+Author: Dave Airlie <airlied at redhat.com>
+Date: Sat Nov 8 14:39:41 2008 +1000
+
+ radeon: fix fence race condition hopefully
+
+ For some reason reading the SCRATCH reg from RAM causes some race to occur.
+ Hopefully fix this.
+
+commit bb1fe264b4a57713e8f0ee5e04d29f5061e45e15
+Author: Dave Airlie <airlied at redhat.com>
+Date: Sat Nov 8 11:31:03 2008 +1000
+
+ drm/radeon: add dpms connector functions
+
+commit 0e88e45a884a1c38084b060c8dc588ead17a3382
+Author: Dave Airlie <airlied at redhat.com>
+Date: Fri Nov 7 16:22:22 2008 +1000
+
+ radeon: avivo cursors are across the full surface.
+
+ fixes cursor on second head
+
+commit 898c6e16d6390e1aea99d45e15e86a6c4ddd38e8
+Author: Dave Airlie <airlied at redhat.com>
+Date: Fri Nov 7 16:21:03 2008 +1000
+
+ modesetting: set the crtc x,y after the mode base change
+
+commit 34bfe1d2d06576aa8d7a6b2c689fa8fb43545407
+Author: Dave Airlie <airlied at redhat.com>
+Date: Wed Nov 5 10:23:35 2008 +1000
+
+ drm/radeon: add uncached allocator to drm ttm code.
+
+ This allows re-use of uc/wc marked pages
+
+commit dca718feb536730d005b32d081737e191e05ce60
+Author: Dave Airlie <airlied at redhat.com>
+Date: Wed Nov 5 10:22:27 2008 +1000
+
+ radeon: fix ring tail overflow issue since alignment
+
+commit d115749300ee625cd23e6ff50d4f3e14c4616d35
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Nov 4 13:18:02 2008 +1000
+
+ radeon: disable HDP read cache for now
+
+commit df1c660505fcecaba8e6d76430da0be80c67923a
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Nov 4 12:02:55 2008 +1000
+
+ radeon: force all ring writes to 16-dword alignment.
+
+ Also set the fetch size to what tcore/fglrx uses.
+
+commit 3cacc2f41bbd6f46d7eb13948db318c7c13e5c60
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Nov 3 15:43:08 2008 +1000
+
+ radeon: fixup vram visible calculation to take a/c pinned objects for now
+
commit 96b17b8573d9d8d9507602c9dfb0a1b87e6ff1f5
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 3 09:56:02 2008 +1100
@@ -1294,20 +1357,22 @@
tristate "Intel I810"
depends on DRM && AGP && AGP_INTEL
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
-index 74da994..48567a9 100644
+index 74da994..cf6af69 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
-@@ -9,7 +9,9 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \
+@@ -9,8 +9,10 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \
drm_drv.o drm_fops.o drm_gem.o drm_ioctl.o drm_irq.o \
drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \
drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \
- drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o
+-
+ drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o \
+ drm_fence.o drm_bo.o drm_ttm.o drm_bo_move.o \
-+ drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o
-
++ drm_crtc.o drm_crtc_helper.o drm_modes.o drm_edid.o drm_uncached.o
++
drm-$(CONFIG_COMPAT) += drm_ioc32.o
+ obj-$(CONFIG_DRM) += drm.o
diff --git a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
index c533d0c..adc57dd 100644
--- a/drivers/gpu/drm/ati_pcigart.c
@@ -1920,10 +1985,10 @@
return -EINVAL;
diff --git a/drivers/gpu/drm/drm_bo.c b/drivers/gpu/drm/drm_bo.c
new file mode 100644
-index 0000000..5cec5a0
+index 0000000..3d7c623
--- /dev/null
+++ b/drivers/gpu/drm/drm_bo.c
-@@ -0,0 +1,2116 @@
+@@ -0,0 +1,2119 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
@@ -3763,6 +3828,7 @@
+ if (bm->dummy_read_page)
+ __free_page(bm->dummy_read_page);
+
++ drm_uncached_fini();
+out:
+ mutex_unlock(&dev->struct_mutex);
+ return ret;
@@ -3782,6 +3848,8 @@
+ struct drm_buffer_manager *bm = &dev->bm;
+ int ret = -EINVAL;
+
++ drm_uncached_init();
++
+ bm->dummy_read_page = NULL;
+ mutex_lock(&dev->struct_mutex);
+ if (!driver)
@@ -4911,7 +4979,7 @@
dev->driver->context_dtor(dev, ctx->handle);
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
new file mode 100644
-index 0000000..15b9f3e
+index 0000000..558de02
--- /dev/null
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -0,0 +1,2391 @@
@@ -6338,7 +6406,7 @@
+ set.mode = mode;
+ set.connectors = connector_set;
+ set.num_connectors = crtc_req->count_connectors;
-+ set.fb =fb;
++ set.fb = fb;
+ ret = crtc->funcs->set_config(&set);
+
+out:
@@ -7308,10 +7376,10 @@
+}
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
new file mode 100644
-index 0000000..776a98e
+index 0000000..ebb4479
--- /dev/null
+++ b/drivers/gpu/drm/drm_crtc_helper.c
-@@ -0,0 +1,804 @@
+@@ -0,0 +1,833 @@
+/* (c) 2006-2007 Intel Corporation
+ * Copyright (c) 2007 Dave Airlie <airlied at linux.ie>
+ *
@@ -7997,6 +8065,8 @@
+ if (set->crtc->fb != set->fb)
+ set->crtc->fb = set->fb;
+ crtc_funcs->mode_set_base(set->crtc, set->x, set->y);
++ set->crtc->x = set->x;
++ set->crtc->y = set->y;
+ }
+
+ kfree(save_encoders);
@@ -8116,6 +8186,33 @@
+ return 0;
+}
+EXPORT_SYMBOL(drm_helper_resume_force_mode);
++
++void drm_helper_set_connector_dpms(struct drm_connector *connector,
++ int dpms_mode)
++{
++ int i = 0;
++ struct drm_encoder *encoder;
++ struct drm_encoder_helper_funcs *encoder_funcs;
++ struct drm_mode_object *obj;
++
++ for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
++ if (connector->encoder_ids[i] == 0)
++ break;
++
++ obj = drm_mode_object_find(connector->dev,
++ connector->encoder_ids[i],
++ DRM_MODE_OBJECT_ENCODER);
++ if (!obj)
++ continue;
++
++ encoder = obj_to_encoder(obj);
++ encoder_funcs = encoder->helper_private;
++ if (encoder_funcs->dpms)
++ encoder_funcs->dpms(encoder, dpms_mode);
++
++ }
++}
++EXPORT_SYMBOL(drm_helper_set_connector_dpms);
diff --git a/drivers/gpu/drm/drm_dma.c b/drivers/gpu/drm/drm_dma.c
index 7a8e2fb..0b2df71 100644
--- a/drivers/gpu/drm/drm_dma.c
@@ -11594,10 +11691,10 @@
}
diff --git a/drivers/gpu/drm/drm_ttm.c b/drivers/gpu/drm/drm_ttm.c
new file mode 100644
-index 0000000..4e4c0b8
+index 0000000..0fe40e6
--- /dev/null
+++ b/drivers/gpu/drm/drm_ttm.c
-@@ -0,0 +1,462 @@
+@@ -0,0 +1,473 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
@@ -11670,14 +11767,18 @@
+ ttm->pages = NULL;
+}
+
-+static struct page *drm_ttm_alloc_page(void)
++static struct page *drm_ttm_alloc_page(struct drm_ttm *ttm)
+{
+ struct page *page;
+
+ if (drm_alloc_memctl(PAGE_SIZE))
+ return NULL;
+
-+ page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
++ if (ttm->dev->bm.allocator_type == _DRM_BM_ALLOCATOR_UNCACHED)
++ page = drm_get_uncached_page();
++ else
++ page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
++
+ if (!page) {
+ drm_free_memctl(PAGE_SIZE);
+ return NULL;
@@ -11695,6 +11796,9 @@
+ int i;
+ struct page **cur_page;
+
++ if (ttm->dev->bm.allocator_type == _DRM_BM_ALLOCATOR_UNCACHED)
++ return 0;
++
+ if ((ttm->page_flags & DRM_TTM_PAGE_UNCACHED) == noncached)
+ return 0;
+
@@ -11762,11 +11866,15 @@
+ for (i = 0; i < ttm->num_pages; ++i) {
+ cur_page = ttm->pages + i;
+ if (*cur_page) {
-+ if (page_count(*cur_page) != 1)
-+ DRM_ERROR("Erroneous page count. Leaking pages.\n");
-+ if (page_mapped(*cur_page))
-+ DRM_ERROR("Erroneous map count. Leaking page mappings.\n");
-+ __free_page(*cur_page);
++ if (ttm->dev->bm.allocator_type == _DRM_BM_ALLOCATOR_UNCACHED)
++ drm_put_uncached_page(*cur_page);
++ else {
++ if (page_count(*cur_page) != 1)
++ DRM_ERROR("Erroneous page count. Leaking pages.\n");
++ if (page_mapped(*cur_page))
++ DRM_ERROR("Erroneous map count. Leaking page mappings.\n");
++ __free_page(*cur_page);
++ }
+ drm_free_memctl(PAGE_SIZE);
+ --bm->cur_pages;
+ }
@@ -11812,7 +11920,7 @@
+ struct drm_buffer_manager *bm = &ttm->dev->bm;
+
+ while(NULL == (p = ttm->pages[index])) {
-+ p = drm_ttm_alloc_page();
++ p = drm_ttm_alloc_page(ttm);
+ if (!p)
+ return NULL;
+
@@ -12060,6 +12168,150 @@
+ return 0;
+}
+EXPORT_SYMBOL(drm_ttm_bind);
+diff --git a/drivers/gpu/drm/drm_uncached.c b/drivers/gpu/drm/drm_uncached.c
+new file mode 100644
+index 0000000..9c7183b
+--- /dev/null
++++ b/drivers/gpu/drm/drm_uncached.c
+@@ -0,0 +1,138 @@
++/*
++ * Copyright (c) Red Hat Inc.
++
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sub license,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
++ * DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: Dave Airlie <airlied at redhat.com>
++ */
++
++/* simple list based uncached page allocator
++ * - Add chunks of 1MB to the allocator at a time.
++ * - Use page->lru to keep a free list
++ * - doesn't track currently in use pages
++ *
++ * TODO: Add shrinker support
++ */
++
++#include "drmP.h"
++#include <asm/agp.h>
++
++static struct list_head uncached_free_list;
++
++static struct mutex uncached_mutex;
++static int uncached_inited;
++static int total_uncached_pages;
++
++/* add 1MB at a time */
++#define NUM_PAGES_TO_ADD 256
++
++static void drm_uncached_page_put(struct page *page)
++{
++ unmap_page_from_agp(page);
++ put_page(page);
++ __free_page(page);
++}
++
++int drm_uncached_add_pages_locked(int num_pages)
++{
++ struct page *page;
++ int i;
++
++ DRM_DEBUG("adding uncached memory %ld\n", num_pages * PAGE_SIZE);
++ for (i = 0; i < num_pages; i++) {
++
++ page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
++ if (!page) {
++ DRM_ERROR("unable to get page %d\n", i);
++ return i;
++ }
++
++ get_page(page);
++#ifdef CONFIG_X86
++ set_memory_wc((unsigned long)page_address(page), 1);
++#else
++ map_page_into_agp(page);
++#endif
++
++ list_add(&page->lru, &uncached_free_list);
++ total_uncached_pages++;
++ }
++ return i;
++}
++
++struct page *drm_get_uncached_page(void)
++{
++ struct page *page = NULL;
++ int ret;
++
++ mutex_lock(&uncached_mutex);
++ if (list_empty(&uncached_free_list)) {
++ ret = drm_uncached_add_pages_locked(NUM_PAGES_TO_ADD);
++ if (ret == 0)
++ return NULL;
++ }
++
++ page = list_first_entry(&uncached_free_list, struct page, lru);
++ list_del(&page->lru);
++
++ mutex_unlock(&uncached_mutex);
++ return page;
++}
++
++void drm_put_uncached_page(struct page *page)
++{
++ mutex_lock(&uncached_mutex);
++ list_add(&page->lru, &uncached_free_list);
++ mutex_unlock(&uncached_mutex);
++}
++
++void drm_uncached_release_all_pages(void)
++{
++ struct page *page, *tmp;
++
++ list_for_each_entry_safe(page, tmp, &uncached_free_list, lru) {
++ list_del(&page->lru);
++ drm_uncached_page_put(page);
++ }
++}
++
++int drm_uncached_init(void)
++{
++
++ if (uncached_inited)
++ return 0;
++
++ INIT_LIST_HEAD(&uncached_free_list);
++
++ mutex_init(&uncached_mutex);
++ uncached_inited = 1;
++ return 0;
++
++}
++
++void drm_uncached_fini(void)
++{
++ if (!uncached_inited)
++ return;
++
++ uncached_inited = 0;
++ drm_uncached_release_all_pages();
++}
++
diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
index c234c6f..e37ee29 100644
--- a/drivers/gpu/drm/drm_vm.c
@@ -22928,10 +23180,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
new file mode 100644
-index 0000000..18873f0
+index 0000000..be1dbae
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
-@@ -0,0 +1,373 @@
+@@ -0,0 +1,392 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -23011,6 +23263,22 @@
+ return mode;
+}
+
++int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property,
++ uint64_t val)
++{
++ struct drm_device *dev = connector->dev;
++
++ if (property == dev->mode_config.dpms_property) {
++ if (val > 3)
++ return -EINVAL;
++
++ drm_helper_set_connector_dpms(connector, val);
++
++ }
++ return 0;
++}
++
++
+static int radeon_lvds_get_modes(struct drm_connector *connector)
+{
+ struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -23080,6 +23348,7 @@
+ .detect = radeon_lvds_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = radeon_connector_destroy,
++ .set_property = radeon_connector_set_property,
+};
+
+static int radeon_vga_get_modes(struct drm_connector *connector)
@@ -23131,6 +23400,7 @@
+ .detect = radeon_vga_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = radeon_connector_destroy,
++ .set_property = radeon_connector_set_property,
+};
+
+
@@ -23223,6 +23493,7 @@
+struct drm_connector_funcs radeon_dvi_connector_funcs = {
+ .detect = radeon_dvi_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
++ .set_property = radeon_connector_set_property,
+ .destroy = radeon_connector_destroy,
+};
+
@@ -23306,7 +23577,7 @@
+ return NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index 59a2132..f3810bc 100644
+index 59a2132..819c6a3 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -31,6 +31,7 @@
@@ -23442,7 +23713,9 @@
+ RADEON_WRITE(RADEON_BUS_CNTL, tmp);
+ } /* PCIE cards appears to not need this */
+}
-+
+
+- RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
+- return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+void radeon_pll_errata_after_index(struct drm_radeon_private *dev_priv)
+{
+ if (!(dev_priv->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS))
@@ -23479,9 +23752,7 @@
+u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr)
+{
+ uint32_t data;
-
-- RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
-- return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
++
+ RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
+ radeon_pll_errata_after_index(dev_priv);
+ data = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
@@ -23717,23 +23988,23 @@
+
+ dev_priv->scratch[1] = 0;
+ RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
-+
-+ dev_priv->scratch[2] = 0;
-+ RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
- dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
- RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
-+ dev_priv->scratch[3] = 0;
-+ RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
++ dev_priv->scratch[2] = 0;
++ RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
- dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
- RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
- dev_priv->sarea_priv->last_dispatch);
-+ dev_priv->scratch[4] = 0;
-+ RADEON_WRITE(RADEON_SCRATCH_REG4, 0);
++ dev_priv->scratch[3] = 0;
++ RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
- dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
- RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
++ dev_priv->scratch[4] = 0;
++ RADEON_WRITE(RADEON_SCRATCH_REG4, 0);
++
+ dev_priv->scratch[6] = 0;
+ RADEON_WRITE(RADEON_SCRATCH_REG6, 0);
@@ -23947,7 +24218,17 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
drm_core_ioremap(dev_priv->cp_ring, dev);
-@@ -1167,28 +1345,41 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1151,8 +1329,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+ dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
+ dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
+
+- dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
+- dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
++ dev_priv->ring.fetch_size_l2ow = 2;
+ dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
+
+ dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
+@@ -1167,28 +1344,41 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
/* if we have an offset set from userspace */
if (dev_priv->pcigart_offset_set) {
@@ -24009,7 +24290,7 @@
if (dev_priv->flags & RADEON_IS_IGPGART)
dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
else
-@@ -1197,12 +1388,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1197,12 +1387,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
DRM_ATI_GART_MAIN;
dev_priv->gart_info.addr = NULL;
dev_priv->gart_info.bus_addr = 0;
@@ -24023,7 +24304,7 @@
}
if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
-@@ -1215,6 +1401,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1215,6 +1400,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
radeon_set_pcigart(dev_priv, 1);
}
@@ -24033,7 +24314,7 @@
radeon_cp_load_microcode(dev_priv);
radeon_cp_init_ring_buffer(dev, dev_priv);
-@@ -1259,14 +1448,16 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
+@@ -1259,14 +1447,16 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
if (dev_priv->gart_info.bus_addr) {
/* Turn off PCI GART */
radeon_set_pcigart(dev_priv, 0);
@@ -24054,7 +24335,7 @@
}
}
/* only clear to the start of flags */
-@@ -1318,6 +1509,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
+@@ -1318,6 +1508,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_init_t *init = data;
@@ -24065,7 +24346,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
-@@ -1328,7 +1523,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1328,7 +1522,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
case RADEON_INIT_CP:
case RADEON_INIT_R200_CP:
case RADEON_INIT_R300_CP:
@@ -24074,7 +24355,7 @@
case RADEON_CLEANUP_CP:
return radeon_do_cleanup_cp(dev);
}
-@@ -1341,6 +1536,9 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -1341,6 +1535,9 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -24084,7 +24365,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (dev_priv->cp_running) {
-@@ -1368,6 +1566,9 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1368,6 +1565,9 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
int ret;
DRM_DEBUG("\n");
@@ -24094,7 +24375,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv->cp_running)
-@@ -1406,6 +1607,9 @@ void radeon_do_release(struct drm_device * dev)
+@@ -1406,6 +1606,9 @@ void radeon_do_release(struct drm_device * dev)
drm_radeon_private_t *dev_priv = dev->dev_private;
int i, ret;
@@ -24104,7 +24385,7 @@
if (dev_priv) {
if (dev_priv->cp_running) {
/* Stop the cp */
-@@ -1439,6 +1643,9 @@ void radeon_do_release(struct drm_device * dev)
+@@ -1439,6 +1642,9 @@ void radeon_do_release(struct drm_device * dev)
radeon_mem_takedown(&(dev_priv->gart_heap));
radeon_mem_takedown(&(dev_priv->fb_heap));
@@ -24114,7 +24395,7 @@
/* deallocate kernel resources */
radeon_do_cleanup_cp(dev);
}
-@@ -1451,6 +1658,9 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -1451,6 +1657,9 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -24124,7 +24405,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv) {
-@@ -1471,7 +1681,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1471,7 +1680,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -24135,7 +24416,7 @@
return radeon_do_cp_idle(dev_priv);
}
-@@ -1481,6 +1693,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1481,6 +1692,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
@@ -24145,7 +24426,7 @@
return radeon_do_resume_cp(dev);
}
-@@ -1488,6 +1703,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
+@@ -1488,6 +1702,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
{
DRM_DEBUG("\n");
@@ -24155,7 +24436,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
return radeon_do_engine_reset(dev);
-@@ -1710,6 +1928,713 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
+@@ -1710,6 +1927,715 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
return ret;
}
@@ -24753,8 +25034,7 @@
+ dev_priv->ring.size_l2qw = drm_order(dev_priv->ring.size / 8);
+ dev_priv->ring.rptr_update = 4096;
+ dev_priv->ring.rptr_update_l2qw = drm_order(4096 / 8);
-+ dev_priv->ring.fetch_size = 32;
-+ dev_priv->ring.fetch_size_l2ow = drm_order(32 / 16);
++ dev_priv->ring.fetch_size_l2ow = 2; /* do what tcore does */
+ dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
+ dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
+
@@ -24762,6 +25042,9 @@
+
+ r300_init_reg_flags(dev);
+
++ /* turn off HDP read cache for now */
++ RADEON_WRITE(RADEON_HOST_PATH_CNTL, RADEON_READ(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS);
++
+#if __OS_HAS_AGP
+ if (dev_priv->flags & RADEON_IS_AGP)
+ radeon_modeset_agp_init(dev);
@@ -24869,7 +25152,7 @@
int radeon_driver_load(struct drm_device *dev, unsigned long flags)
{
drm_radeon_private_t *dev_priv;
-@@ -1723,6 +2648,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1723,6 +2649,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = (void *)dev_priv;
dev_priv->flags = flags;
@@ -24878,7 +25161,7 @@
switch (flags & RADEON_FAMILY_MASK) {
case CHIP_R100:
case CHIP_RV200:
-@@ -1743,6 +2670,18 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1743,6 +2671,18 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
break;
}
@@ -24897,7 +25180,7 @@
if (drm_device_is_agp(dev))
dev_priv->flags |= RADEON_IS_AGP;
else if (drm_device_is_pcie(dev))
-@@ -1752,7 +2691,119 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1752,33 +2692,130 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
DRM_DEBUG("%s card detected\n",
((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
@@ -24964,13 +25247,13 @@
+ }
+
+
- return ret;
++ return ret;
+modeset_fail:
+ dev->driver->driver_features &= ~DRIVER_MODESET;
+ drm_put_minor(&dev->control);
-+ return ret;
-+}
-+
+ return ret;
+ }
+
+int radeon_master_create(struct drm_device *dev, struct drm_master *master)
+{
+ struct drm_radeon_master_private *master_priv;
@@ -25014,10 +25297,10 @@
+ drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
+
+ master->driver_priv = NULL;
- }
-
++}
++
/* Create mappings for registers and framebuffer so userland doesn't necessarily
-@@ -1760,25 +2811,10 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+ * have to find them.
*/
int radeon_driver_firstopen(struct drm_device *dev)
{
@@ -25043,7 +25326,7 @@
return 0;
}
-@@ -1786,9 +2822,44 @@ int radeon_driver_unload(struct drm_device *dev)
+@@ -1786,9 +2823,76 @@ int radeon_driver_unload(struct drm_device *dev)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -25088,6 +25371,38 @@
+ }
+
+}
++
++void radeon_commit_ring(drm_radeon_private_t *dev_priv)
++{
++ int i;
++ u32 *ring;
++ int tail_aligned;
++
++ /* check if the ring is padded out to 16-dword alignment */
++
++ tail_aligned = dev_priv->ring.tail & 0xf;
++ if (tail_aligned) {
++ int num_p2 = 16 - tail_aligned;
++
++ ring = dev_priv->ring.start;
++ /* pad with some CP_PACKET2 */
++ for (i = 0; i < num_p2; i++)
++ ring[dev_priv->ring.tail + i] = CP_PACKET2();
++
++ dev_priv->ring.tail += i;
++
++ dev_priv->ring.space -= num_p2 * sizeof(u32);
++ }
++
++ dev_priv->ring.tail &= dev_priv->ring.tail_mask;
++
++ DRM_MEMORYBARRIER();
++ GET_RING_HEAD( dev_priv );
++
++ RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );
++ /* read from PCI bus to ensure correct posting */
++ RADEON_READ( RADEON_CP_RB_RPTR );
++}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
new file mode 100644
index 0000000..302dd93
@@ -25705,10 +26020,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
new file mode 100644
-index 0000000..d352d10
+index 0000000..fbd4143
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
-@@ -0,0 +1,243 @@
+@@ -0,0 +1,247 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -25915,6 +26230,10 @@
+
+ radeon_lock_cursor(crtc, true);
+ if (radeon_is_avivo(dev_priv)) {
++ /* avivo cursor are offset into the total surface */
++ x += crtc->x;
++ y += crtc->y;
++ DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
+ RADEON_WRITE(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
+ ((xorigin ? 0: x) << 16) |
+ (yorigin ? 0 : y));
@@ -26827,7 +27146,7 @@
}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index 4dbb813..57d4aab 100644
+index 4dbb813..705e7ea 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -34,6 +34,8 @@
@@ -26917,7 +27236,15 @@
typedef struct drm_radeon_freelist {
unsigned int age;
-@@ -226,14 +265,87 @@ struct radeon_virt_surface {
+@@ -180,7 +219,6 @@ typedef struct drm_radeon_ring_buffer {
+ int rptr_update; /* Double Words */
+ int rptr_update_l2qw; /* log2 Quad Words */
+
+- int fetch_size; /* Double Words */
+ int fetch_size_l2ow; /* log2 Oct Words */
+
+ u32 tail;
+@@ -226,14 +264,87 @@ struct radeon_virt_surface {
#define RADEON_FLUSH_EMITED (1 < 0)
#define RADEON_PURGE_EMITED (1 < 1)
@@ -27010,7 +27337,7 @@
int gart_size;
u32 gart_vm_start;
unsigned long gart_buffers_offset;
-@@ -249,8 +361,6 @@ typedef struct drm_radeon_private {
+@@ -249,8 +360,6 @@ typedef struct drm_radeon_private {
int usec_timeout;
@@ -27019,7 +27346,7 @@
struct {
u32 boxes;
int freelist_timeouts;
-@@ -286,8 +396,6 @@ typedef struct drm_radeon_private {
+@@ -286,8 +395,6 @@ typedef struct drm_radeon_private {
unsigned long buffers_offset;
unsigned long gart_textures_offset;
@@ -27028,7 +27355,7 @@
drm_local_map_t *cp_ring;
drm_local_map_t *ring_rptr;
drm_local_map_t *gart_textures;
-@@ -296,8 +404,8 @@ typedef struct drm_radeon_private {
+@@ -296,8 +403,8 @@ typedef struct drm_radeon_private {
struct mem_block *fb_heap;
/* SW interrupt */
@@ -27038,7 +27365,7 @@
int vblank_crtc;
uint32_t irq_enable_reg;
int irq_enabled;
-@@ -306,9 +414,6 @@ typedef struct drm_radeon_private {
+@@ -306,9 +413,6 @@ typedef struct drm_radeon_private {
struct radeon_surface surfaces[RADEON_MAX_SURFACES];
struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
@@ -27048,7 +27375,7 @@
u32 scratch_ages[5];
-@@ -318,6 +423,44 @@ typedef struct drm_radeon_private {
+@@ -318,6 +422,44 @@ typedef struct drm_radeon_private {
int num_gb_pipes;
int track_flush;
@@ -27093,7 +27420,7 @@
} drm_radeon_private_t;
typedef struct drm_radeon_buf_priv {
-@@ -332,8 +475,12 @@ typedef struct drm_radeon_kcmd_buffer {
+@@ -332,8 +474,12 @@ typedef struct drm_radeon_kcmd_buffer {
} drm_radeon_kcmd_buffer_t;
extern int radeon_no_wb;
@@ -27106,7 +27433,7 @@
/* Check whether the given hardware address is inside the framebuffer or the
* GART area.
-@@ -367,12 +514,9 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
+@@ -367,12 +513,9 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
@@ -27120,7 +27447,7 @@
extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
-@@ -400,16 +544,19 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
+@@ -400,16 +543,19 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
extern int radeon_driver_unload(struct drm_device *dev);
extern int radeon_driver_firstopen(struct drm_device *dev);
@@ -27144,7 +27471,7 @@
/* r300_cmdbuf.c */
extern void r300_init_reg_flags(struct drm_device *dev);
-@@ -417,6 +564,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -417,6 +563,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
struct drm_file *file_priv,
drm_radeon_kcmd_buffer_t *cmdbuf);
@@ -27156,7 +27483,7 @@
/* Flags for stats.boxes
*/
#define RADEON_BOX_DMA_IDLE 0x1
-@@ -425,10 +577,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -425,10 +576,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_BOX_WAIT_IDLE 0x8
#define RADEON_BOX_TEXTURE_LOAD 0x10
@@ -27171,7 +27498,7 @@
#define RADEON_AGP_COMMAND 0x0f60
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
# define RADEON_AGP_ENABLE (1<<8)
-@@ -447,12 +603,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -447,12 +602,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
* handling, not bus mastering itself.
*/
#define RADEON_BUS_CNTL 0x0030
@@ -27189,7 +27516,7 @@
#define RADEON_BUS_CNTL1 0x0034
# define RADEON_PMI_BM_DIS (1 << 2)
-@@ -554,16 +710,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -554,16 +709,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define R520_MC_IND_WR_EN (1 << 24)
#define R520_MC_IND_DATA 0x74
@@ -27206,7 +27533,7 @@
#define RADEON_MPP_TB_CONFIG 0x01c0
#define RADEON_MEM_CNTL 0x0140
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
-@@ -628,14 +774,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -628,14 +773,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_SCRATCH_REG3 0x15ec
#define RADEON_SCRATCH_REG4 0x15f0
#define RADEON_SCRATCH_REG5 0x15f4
@@ -27233,7 +27560,7 @@
#define RADEON_GEN_INT_CNTL 0x0040
# define RADEON_CRTC_VBLANK_MASK (1 << 0)
-@@ -654,10 +809,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -654,10 +808,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
# define RADEON_SW_INT_FIRE (1 << 26)
# define R500_DISPLAY_INT_STATUS (1 << 0)
@@ -27242,14 +27569,16 @@
-# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
-# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
+#define RADEON_HOST_PATH_CNTL 0x0130
-+# define RADEON_HDP_SOFT_RESET (1 << 26)
+# define RADEON_HDP_APER_CNTL (1 << 23)
++# define RADEON_HP_LIN_RD_CACHE_DIS (1 << 24)
++# define RADEON_HDP_SOFT_RESET (1 << 26)
++# define RADEON_HDP_READ_BUFFER_INVALIDATED (1 << 27)
+
+#define RADEON_NB_TOM 0x15c
#define RADEON_ISYNC_CNTL 0x1724
# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
-@@ -696,12 +852,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -696,12 +853,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_PP_TXFILTER_1 0x1c6c
#define RADEON_PP_TXFILTER_2 0x1c84
@@ -27273,7 +27602,7 @@
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
-@@ -728,11 +889,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -728,11 +890,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
# define R300_ZC_BUSY (1 << 31)
@@ -27285,7 +27614,7 @@
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_RB3D_DC_FLUSH (2 << 0)
# define R300_RB3D_DC_FREE (2 << 2)
-@@ -740,15 +896,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -740,15 +897,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
@@ -27305,7 +27634,7 @@
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
-@@ -937,7 +1093,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -937,7 +1094,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_AIC_CNTL 0x01d0
# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
@@ -27314,7 +27643,7 @@
#define RADEON_AIC_STAT 0x01d4
#define RADEON_AIC_PT_BASE 0x01d8
#define RADEON_AIC_LO_ADDR 0x01dc
-@@ -1009,27 +1165,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1009,27 +1166,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_NUM_VERTICES_SHIFT 16
#define RADEON_COLOR_FORMAT_CI8 2
@@ -27342,7 +27671,7 @@
#define R200_PP_TXCBLEND_0 0x2f00
#define R200_PP_TXCBLEND_1 0x2f10
-@@ -1140,16 +1275,44 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1140,16 +1276,44 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
@@ -27389,7 +27718,7 @@
#define R500_D1CRTC_STATUS 0x609c
#define R500_D2CRTC_STATUS 0x689c
#define R500_CRTC_V_BLANK (1<<0)
-@@ -1190,19 +1353,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1190,19 +1354,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_RING_HIGH_MARK 128
#define RADEON_PCIGART_TABLE_SIZE (32*1024)
@@ -27433,7 +27762,7 @@
#define RADEON_WRITE_PCIE(addr, val) \
do { \
RADEON_WRITE8(RADEON_PCIE_INDEX, \
-@@ -1259,7 +1439,7 @@ do { \
+@@ -1259,7 +1440,7 @@ do { \
#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
@@ -27442,7 +27771,7 @@
} while (0)
#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
-@@ -1336,8 +1516,9 @@ do { \
+@@ -1336,8 +1517,9 @@ do { \
} while (0)
#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
@@ -27454,7 +27783,50 @@
if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
int __ret = radeon_do_cp_idle( dev_priv ); \
if ( __ret ) return __ret; \
-@@ -1443,4 +1624,146 @@ do { \
+@@ -1367,15 +1549,16 @@ do { \
+
+ #define RADEON_VERBOSE 0
+
+-#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
++#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
+
+ #define BEGIN_RING( n ) do { \
+ if ( RADEON_VERBOSE ) { \
+ DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
+ } \
+- if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
++ _align_nr = (n + 0xf) & ~0xf; \
++ if ( dev_priv->ring.space <= _align_nr ) { \
+ COMMIT_RING(); \
+- radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
++ radeon_wait_ring( dev_priv, _align_nr ); \
+ } \
+ _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
+ ring = dev_priv->ring.start; \
+@@ -1392,19 +1575,14 @@ do { \
+ DRM_ERROR( \
+ "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
+ ((dev_priv->ring.tail + _nr) & mask), \
+- write, __LINE__); \
++ write, __LINE__); \
+ } else \
+ dev_priv->ring.tail = write; \
+ } while (0)
+
+ #define COMMIT_RING() do { \
+- /* Flush writes to ring */ \
+- DRM_MEMORYBARRIER(); \
+- GET_RING_HEAD( dev_priv ); \
+- RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
+- /* read from PCI bus to ensure correct posting */ \
+- RADEON_READ( RADEON_CP_RB_RPTR ); \
+-} while (0)
++ radeon_commit_ring(dev_priv); \
++ } while(0)
+
+ #define OUT_RING( x ) do { \
+ if ( RADEON_VERBOSE ) { \
+@@ -1443,4 +1621,148 @@ do { \
write &= mask; \
} while (0)
@@ -27598,6 +27970,8 @@
+#define MARK_CHECK_OFFSET 2
+#define MARK_CHECK_SCISSOR 3
+
++extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
++
+extern int r300_check_range(unsigned reg, int count);
+extern int r300_get_reg_flags(unsigned reg);
#endif /* __RADEON_DRV_H__ */
@@ -28716,10 +29090,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
new file mode 100644
-index 0000000..cbf9a83
+index 0000000..244b066
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
-@@ -0,0 +1,922 @@
+@@ -0,0 +1,927 @@
+/*
+ * Copyright © 2007 David Airlie
+ *
@@ -29189,6 +29563,7 @@
+ uint32_t surface_width, uint32_t surface_height,
+ struct radeon_framebuffer **radeon_fb_p)
+{
++ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct fb_info *info;
+ struct radeonfb_par *par;
+ struct drm_framebuffer *fb;
@@ -29225,6 +29600,8 @@
+ goto out_unref;
+ }
+
++ dev_priv->mm.vram_visible -= aligned_size;
++
+ mutex_lock(&dev->struct_mutex);
+ fb = radeon_framebuffer_create(dev, &mode_cmd, fbo);
+ if (!fb) {
@@ -29618,6 +29995,7 @@
+
+int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
+{
++ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct fb_info *info;
+ struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
+
@@ -29629,6 +30007,7 @@
+ if (info) {
+ unregister_framebuffer(info);
+ drm_bo_kunmap(&radeon_fb->kmap_obj);
++ dev_priv->mm.vram_visible += radeon_fb->obj->size;
+ mutex_lock(&dev->struct_mutex);
+ drm_gem_object_unreference(radeon_fb->obj);
+ radeon_fb->obj = NULL;
@@ -29644,10 +30023,10 @@
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
new file mode 100644
-index 0000000..b662da2
+index 0000000..13af804
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
-@@ -0,0 +1,98 @@
+@@ -0,0 +1,99 @@
+/**************************************************************************
+ *
+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
@@ -29707,14 +30086,15 @@
+{
+ struct drm_radeon_private *dev_priv = (struct drm_radeon_private *) dev->dev_private;
+ uint32_t sequence;
-+ if (waiting_types & DRM_FENCE_TYPE_EXE) {
+
-+ sequence = READ_BREADCRUMB(dev_priv);
++ sequence = RADEON_READ(RADEON_SCRATCH_REG3);
++ /* this used to be READ_BREADCRUMB(dev_priv); but it caused
++ * a race somewhere in the fencing irq
++ */
+
-+ DRM_DEBUG("polling %d\n", sequence);
-+ drm_fence_handler(dev, 0, sequence,
-+ DRM_FENCE_TYPE_EXE, 0);
-+ }
++ DRM_DEBUG("polling %d\n", sequence);
++ drm_fence_handler(dev, 0, sequence,
++ DRM_FENCE_TYPE_EXE, 0);
+}
+
+void radeon_fence_handler(struct drm_device * dev)
@@ -29748,10 +30128,10 @@
+
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
new file mode 100644
-index 0000000..2e20de3
+index 0000000..f338e64
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
-@@ -0,0 +1,1597 @@
+@@ -0,0 +1,1603 @@
+/*
+ * Copyright 2008 Red Hat Inc.
+ *
@@ -30340,6 +30720,9 @@
+ if (ret)
+ return -EINVAL;
+
++ /* subtract from VRAM value reporting to userspace */
++ dev_priv->mm.vram_visible -= RADEON_PCIGART_TABLE_SIZE;
++
+ dev_priv->mm.pcie_table_backup = kzalloc(RADEON_PCIGART_TABLE_SIZE, GFP_KERNEL);
+ if (!dev_priv->mm.pcie_table_backup)
+ return -EINVAL;
@@ -30717,6 +31100,9 @@
+ /* init TTM underneath */
+ drm_bo_driver_init(dev);
+
++ /* use the uncached allocator */
++ dev->bm.allocator_type = _DRM_BM_ALLOCATOR_UNCACHED;
++
+ /* size the mappable VRAM memory for now */
+ radeon_vram_setup(dev);
+
@@ -42120,10 +42506,10 @@
+
diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
new file mode 100644
-index 0000000..c071915
+index 0000000..a0dd667
--- /dev/null
+++ b/include/drm/drm_crtc_helper.h
-@@ -0,0 +1,96 @@
+@@ -0,0 +1,98 @@
+/*
+ * Copyright © 2006 Keith Packard
+ * Copyright © 2007 Intel Corporation
@@ -42219,6 +42605,8 @@
+}
+
+extern int drm_helper_resume_force_mode(struct drm_device *dev);
++extern void drm_helper_set_connector_dpms(struct drm_connector *connector,
++ int dpms_mode);
+#endif
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
new file mode 100644
@@ -42690,10 +43078,10 @@
+#endif
diff --git a/include/drm/drm_objects.h b/include/drm/drm_objects.h
new file mode 100644
-index 0000000..cdd8236
+index 0000000..604c8f8
--- /dev/null
+++ b/include/drm/drm_objects.h
-@@ -0,0 +1,900 @@
+@@ -0,0 +1,913 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
@@ -43357,6 +43745,9 @@
+#define _DRM_FLAG_MEMTYPE_CMA 0x00000010 /* Can't map aperture */
+#define _DRM_FLAG_MEMTYPE_CSELECT 0x00000020 /* Select caching */
+
++#define _DRM_BM_ALLOCATOR_CACHED 0x0
++#define _DRM_BM_ALLOCATOR_UNCACHED 0x1
++
+struct drm_buffer_manager {
+ struct drm_bo_lock bm_lock;
+ struct mutex evict_mutex;
@@ -43371,6 +43762,7 @@
+ unsigned long cur_pages;
+ atomic_t count;
+ struct page *dummy_read_page;
++ int allocator_type;
+};
+
+struct drm_bo_driver {
@@ -43586,6 +43978,15 @@
+ void **virtual);
+extern void drm_mem_reg_iounmap(struct drm_device *dev, struct drm_bo_mem_reg * mem,
+ void *virtual);
++
++/*
++ * drm_uncached.c
++ */
++extern int drm_uncached_init(void);
++extern void drm_uncached_fini(void);
++extern struct page *drm_get_uncached_page(void);
++extern void drm_put_uncached_page(struct page *page);
++
+#ifdef CONFIG_DEBUG_MUTEXES
+#define DRM_ASSERT_LOCKED(_mutex) \
+ BUG_ON(!mutex_is_locked(_mutex) || \
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-10/kernel.spec,v
retrieving revision 1.1123
retrieving revision 1.1124
diff -u -r1.1123 -r1.1124
--- kernel.spec 7 Nov 2008 23:05:01 -0000 1.1123
+++ kernel.spec 8 Nov 2008 04:49:47 -0000 1.1124
@@ -1890,6 +1890,9 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Sat Nov 08 2008 Dave Airlie <airlied at redhat.com> 2.6.27.5-88
+- radeon modesetting - fix mouse on second head and 3 second hangs hopefully
+
* Fri Nov 07 2008 Chuck Ebbert <cebbert at redhat.com> 2.6.27.5-87
- Linux 2.6.27.5
Dropped Patches:
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