rpms/kernel/devel drm-modesetting-radeon.patch, 1.40, 1.41 kernel.spec, 1.1087, 1.1088
Dave Airlie
airlied at fedoraproject.org
Mon Oct 27 06:52:26 UTC 2008
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Author: airlied
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv10617
Modified Files:
drm-modesetting-radeon.patch kernel.spec
Log Message:
- drm-modesetting-radeon.patch - fix some kms issues + add better CS scheme
drm-modesetting-radeon.patch:
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-modesetting-radeon.patch,v
retrieving revision 1.40
retrieving revision 1.41
diff -u -r1.40 -r1.41
--- drm-modesetting-radeon.patch 21 Oct 2008 04:42:59 -0000 1.40
+++ drm-modesetting-radeon.patch 27 Oct 2008 06:52:24 -0000 1.41
@@ -1,3 +1,45 @@
+commit 3d3d149bb684e40fd0f64e6bd24435cca67f3782
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 27 16:41:09 2008 +1000
+
+ radeon: fix some warnings
+
+commit bd62d1ad62cafae3b4e6fe577b422e4995da3813
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 27 16:40:34 2008 +1000
+
+ radeon: fix free after refcount
+
+commit f51358b70d8305688a10dc144d13c18736695971
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 27 16:40:15 2008 +1000
+
+ radeon: CS2 make it all work with new relocs style
+
+commit 410f9425d0a3d44ddd01f63ef0853685c92171f6
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 27 16:39:12 2008 +1000
+
+ radeon: don't copy to user the cs ids
+
+commit 2df731f61efe9456691fcabc11017149806d1151
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 27 14:23:22 2008 +1000
+
+ radeon: make new CS2 command submission interface port older interface to this
+
+commit a0d1c8a1614ce63133fa97527ea7fda11305d609
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 27 10:26:03 2008 +1000
+
+ radeon/drm: fixup ref counting in on fb objs
+
+commit 35f2b23e19b93e6537c07a670ec3a607d22051ec
+Author: Dave Airlie <airlied at redhat.com>
+Date: Thu Oct 23 19:13:50 2008 +1000
+
+ radeon: release agp on module unload
+
commit 0e05709a0476a4572d5bc5ff44a56fc880781a19
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Oct 21 14:15:23 2008 +1000
@@ -7140,10 +7182,10 @@
+}
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
new file mode 100644
-index 0000000..b334f5b
+index 0000000..776a98e
--- /dev/null
+++ b/drivers/gpu/drm/drm_crtc_helper.c
-@@ -0,0 +1,806 @@
+@@ -0,0 +1,804 @@
+/* (c) 2006-2007 Intel Corporation
+ * Copyright (c) 2007 Dave Airlie <airlied at linux.ie>
+ *
@@ -7917,15 +7959,13 @@
+EXPORT_SYMBOL(drm_helper_hotplug_stage_two);
+
+int drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
-+ struct drm_mode_fb_cmd *mode_cmd,
-+ void *mm_private)
++ struct drm_mode_fb_cmd *mode_cmd)
+{
+ fb->width = mode_cmd->width;
+ fb->height = mode_cmd->height;
+ fb->pitch = mode_cmd->pitch;
+ fb->bits_per_pixel = mode_cmd->bpp;
+ fb->depth = mode_cmd->depth;
-+ fb->mm_private = mm_private;
+
+ return 0;
+}
@@ -19139,7 +19179,7 @@
+#endif /* _ATOMBIOS_H */
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
new file mode 100644
-index 0000000..8023716
+index 0000000..a813ba9
--- /dev/null
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -0,0 +1,461 @@
@@ -19420,7 +19460,7 @@
+
+ radeon_fb = to_radeon_framebuffer(crtc->fb);
+
-+ obj = radeon_fb->base.mm_private;
++ obj = radeon_fb->obj;
+ obj_priv = obj->driver_private;
+
+ fb_location = obj_priv->bo->offset + dev_priv->fb_location;
@@ -23118,7 +23158,7 @@
+ return NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index 59a2132..31debc8 100644
+index 59a2132..fa7f9f6 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -31,6 +31,7 @@
@@ -23270,7 +23310,9 @@
+ */
+ if (dev_priv->pll_errata & CHIP_ERRATA_PLL_DELAY)
+ udelay(5000);
-+
+
+- RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
+- return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+ /* This function is required to workaround a hardware bug in some (all?)
+ * revisions of the R300. This workaround should be called after every
+ * CLOCK_CNTL_INDEX register access. If not, register reads afterward
@@ -23296,19 +23338,17 @@
+ data = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+ radeon_pll_errata_after_data(dev_priv);
+ return data;
-+}
+ }
-- RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
-- return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+-static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data)
+{
+ RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, ((addr & 0x3f) | RADEON_PLL_WR_EN));
+ radeon_pll_errata_after_index(dev_priv);
+ RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, data);
+ radeon_pll_errata_after_data(dev_priv);
- }
-
--static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
++}
++
+u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
{
RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
@@ -23483,15 +23523,13 @@
+ dev_priv->scratch = ((__volatile__ u32 *)
+ dev_priv->ring_rptr->handle +
+ (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
-+
+
+- RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
+ if (dev_priv->chip_family >= CHIP_R300)
+ RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7f);
+ else
+ RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x1f);
-- RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
-+ radeon_enable_bm(dev_priv);
-
- /* Turn on bus mastering */
- if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
- ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
@@ -23505,25 +23543,27 @@
- tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
- RADEON_WRITE(RADEON_BUS_CNTL, tmp);
- } /* PCIE cards appears to not need this */
++ radeon_enable_bm(dev_priv);
++
+ dev_priv->scratch[0] = 0;
+ RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
-+
-+ dev_priv->scratch[1] = 0;
-+ RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
- dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
- RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
-+ dev_priv->scratch[2] = 0;
-+ RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
++ dev_priv->scratch[1] = 0;
++ RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
- dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
- RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
- dev_priv->sarea_priv->last_dispatch);
-+ dev_priv->scratch[3] = 0;
-+ RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
++ dev_priv->scratch[2] = 0;
++ RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
- dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
- RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
++ dev_priv->scratch[3] = 0;
++ RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
++
+ dev_priv->scratch[4] = 0;
+ RADEON_WRITE(RADEON_SCRATCH_REG4, 0);
+
@@ -23948,7 +23988,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
return radeon_do_engine_reset(dev);
-@@ -1710,6 +1922,703 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
+@@ -1710,6 +1922,709 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
return ret;
}
@@ -24515,6 +24555,12 @@
+ }
+ return 0;
+}
++
++void radeon_modeset_agp_destroy(struct drm_device *dev)
++{
++ if (dev->agp->acquired)
++ drm_agp_release(dev);
++}
+#endif
+
+int radeon_modeset_cp_init(struct drm_device *dev)
@@ -24652,7 +24698,7 @@
int radeon_driver_load(struct drm_device *dev, unsigned long flags)
{
drm_radeon_private_t *dev_priv;
-@@ -1723,6 +2632,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1723,6 +2638,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = (void *)dev_priv;
dev_priv->flags = flags;
@@ -24661,7 +24707,7 @@
switch (flags & RADEON_FAMILY_MASK) {
case CHIP_R100:
case CHIP_RV200:
-@@ -1743,6 +2654,14 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1743,6 +2660,14 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
break;
}
@@ -24676,7 +24722,7 @@
if (drm_device_is_agp(dev))
dev_priv->flags |= RADEON_IS_AGP;
else if (drm_device_is_pcie(dev))
-@@ -1752,33 +2671,123 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1752,7 +2677,112 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
DRM_DEBUG("%s card detected\n",
((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
@@ -24736,13 +24782,13 @@
+ }
+
+
-+ return ret;
+ return ret;
+modeset_fail:
+ dev->driver->driver_features &= ~DRIVER_MODESET;
+ drm_put_minor(&dev->control);
- return ret;
- }
-
++ return ret;
++}
++
+int radeon_master_create(struct drm_device *dev, struct drm_master *master)
+{
+ struct drm_radeon_master_private *master_priv;
@@ -24786,10 +24832,10 @@
+ drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
+
+ master->driver_priv = NULL;
-+}
-+
+ }
+
/* Create mappings for registers and framebuffer so userland doesn't necessarily
- * have to find them.
+@@ -1760,25 +2790,10 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
*/
int radeon_driver_firstopen(struct drm_device *dev)
{
@@ -24815,7 +24861,7 @@
return 0;
}
-@@ -1786,9 +2795,40 @@ int radeon_driver_unload(struct drm_device *dev)
+@@ -1786,9 +2801,44 @@ int radeon_driver_unload(struct drm_device *dev)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -24823,6 +24869,10 @@
+ drm_irq_uninstall(dev);
+ radeon_modeset_cleanup(dev);
+ radeon_gem_mm_fini(dev);
++#if __OS_HAS_AGP
++ if (dev_priv->flags & RADEON_IS_AGP)
++ radeon_modeset_agp_destroy(dev);
++#endif
+ }
+
+ drm_rmmap(dev, dev_priv->mmio);
@@ -24858,10 +24908,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
new file mode 100644
-index 0000000..d760efe
+index 0000000..6ad499b
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
-@@ -0,0 +1,399 @@
+@@ -0,0 +1,589 @@
+/*
+ * Copyright 2008 Jerome Glisse.
+ * All Rights Reserved.
@@ -24893,21 +24943,176 @@
+#include "radeon_drv.h"
+#include "r300_reg.h"
+
++int radeon_cs2_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
++{
++ struct drm_radeon_cs_parser parser;
++ struct drm_radeon_private *dev_priv = dev->dev_private;
++ struct drm_radeon_cs2 *cs = data;
++ uint32_t cs_id;
++ struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
++ uint64_t *chunk_array;
++ uint64_t *chunk_array_ptr;
++ uint32_t card_offset;
++ long size;
++ int r, i;
++ RING_LOCALS;
++
++ /* set command stream id to 0 which is fake id */
++ cs_id = 0;
++ cs->cs_id = cs_id;
++
++ if (dev_priv == NULL) {
++ DRM_ERROR("called with no initialization\n");
++ return -EINVAL;
++ }
++ if (!cs->num_chunks) {
++ return 0;
++ }
++
++
++ chunk_array = drm_calloc(cs->num_chunks, sizeof(uint64_t), DRM_MEM_DRIVER);
++ if (!chunk_array) {
++ return -ENOMEM;
++ }
++
++ chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
++
++ if (DRM_COPY_FROM_USER(chunk_array, chunk_array_ptr, sizeof(uint64_t)*cs->num_chunks)) {
++ r = -EFAULT;
++ goto out;
++ }
++
++ parser.dev = dev;
++ parser.file_priv = fpriv;
++ parser.reloc_index = -1;
++ parser.ib_index = -1;
++ parser.num_chunks = cs->num_chunks;
++ /* copy out the chunk headers */
++ parser.chunks = drm_calloc(parser.num_chunks, sizeof(struct drm_radeon_kernel_chunk), DRM_MEM_DRIVER);
++ if (!parser.chunks) {
++ return -ENOMEM;
++ }
++
++ for (i = 0; i < parser.num_chunks; i++) {
++ struct drm_radeon_cs_chunk user_chunk;
++
++ chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
++
++ if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, sizeof(struct drm_radeon_cs_chunk))){
++ r = -EFAULT;
++ goto out;
++ }
++ parser.chunks[i].chunk_id = user_chunk.chunk_id;
++
++ if (parser.chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS)
++ parser.reloc_index = i;
++
++ if (parser.chunks[i].chunk_id == RADEON_CHUNK_ID_IB)
++ parser.ib_index = i;
++
++ if (parser.chunks[i].chunk_id == RADEON_CHUNK_ID_OLD) {
++ parser.ib_index = i;
++ parser.reloc_index = -1;
++ }
++
++ parser.chunks[i].length_dw = user_chunk.length_dw;
++ parser.chunks[i].chunk_data = (uint32_t *)(unsigned long)user_chunk.chunk_data;
++
++ parser.chunks[i].kdata = NULL;
++ size = parser.chunks[i].length_dw * sizeof(uint32_t);
++
++ switch(parser.chunks[i].chunk_id) {
++ case RADEON_CHUNK_ID_IB:
++ case RADEON_CHUNK_ID_OLD:
++ if (size == 0) {
++ r = -EINVAL;
++ goto out;
++ }
++ case RADEON_CHUNK_ID_RELOCS:
++ if (size) {
++ parser.chunks[i].kdata = drm_alloc(size, DRM_MEM_DRIVER);
++ if (!parser.chunks[i].kdata) {
++ r = -ENOMEM;
++ goto out;
++ }
++
++ if (DRM_COPY_FROM_USER(parser.chunks[i].kdata, parser.chunks[i].chunk_data, size)) {
++ r = -EFAULT;
++ goto out;
++ }
++ } else
++ parser.chunks[i].kdata = NULL;
++ break;
++ default:
++ break;
++ }
++ DRM_DEBUG("chunk %d %d %d %p\n", i, parser.chunks[i].chunk_id, parser.chunks[i].length_dw,
++ parser.chunks[i].chunk_data);
++ }
++
++
++ if (parser.chunks[parser.ib_index].length_dw > (16 * 1024)) {
++ DRM_ERROR("cs->dwords too big: %d\n", parser.chunks[parser.ib_index].length_dw);
++ r = -EINVAL;
++ goto out;
++ }
++
++ /* get ib */
++ r = dev_priv->cs.ib_get(&parser, &card_offset);
++ if (r) {
++ DRM_ERROR("ib_get failed\n");
++ goto out;
++ }
++
++ /* now parse command stream */
++ r = dev_priv->cs.parse(&parser);
++ if (r) {
++ goto out;
++ }
++
++ BEGIN_RING(4);
++ OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
++ OUT_RING(card_offset);
++ OUT_RING(parser.chunks[parser.ib_index].length_dw);
++ OUT_RING(CP_PACKET2());
++ ADVANCE_RING();
++
++ /* emit cs id sequence */
++ dev_priv->cs.id_emit(dev, &cs_id);
++ COMMIT_RING();
++
++ cs->cs_id = cs_id;
++
++out:
++ dev_priv->cs.ib_free(&parser);
++
++ for (i = 0; i < parser.num_chunks; i++) {
++ if (parser.chunks[i].kdata)
++ drm_free(parser.chunks[i].kdata, parser.chunks[i].length_dw * sizeof(uint32_t), DRM_MEM_DRIVER);
++ }
++
++ drm_free(parser.chunks, sizeof(struct drm_radeon_kernel_chunk)*parser.num_chunks, DRM_MEM_DRIVER);
++ drm_free(chunk_array, sizeof(uint64_t)*parser.num_chunks, DRM_MEM_DRIVER);
++
++ return r;
++}
++
+int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
+{
++ struct drm_radeon_cs_parser parser;
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct drm_radeon_cs *cs = data;
+ uint32_t *packets = NULL;
+ uint32_t cs_id;
+ uint32_t card_offset;
-+ void *ib = NULL;
+ long size;
+ int r;
++ struct drm_radeon_kernel_chunk chunk_fake[1];
+ RING_LOCALS;
+
+ /* set command stream id to 0 which is fake id */
+ cs_id = 0;
-+ DRM_COPY_TO_USER(&cs->cs_id, &cs_id, sizeof(uint32_t));
++ cs->cs_id = cs_id;
+
+ if (dev_priv == NULL) {
+ DRM_ERROR("called with no initialization\n");
@@ -24934,15 +25139,27 @@
+ r = -EFAULT;
+ goto out;
+ }
++
++ chunk_fake[0].chunk_id = RADEON_CHUNK_ID_OLD;
++ chunk_fake[0].length_dw = cs->dwords;
++ chunk_fake[0].kdata = packets;
++
++ parser.dev = dev;
++ parser.file_priv = fpriv;
++ parser.num_chunks = 1;
++ parser.chunks = chunk_fake;
++ parser.ib_index = 0;
++ parser.reloc_index = -1;
++
+ /* get ib */
-+ r = dev_priv->cs.ib_get(dev, &ib, cs->dwords, &card_offset);
++ r = dev_priv->cs.ib_get(&parser, &card_offset);
+ if (r) {
+ DRM_ERROR("ib_get failed\n");
+ goto out;
+ }
-+
++
+ /* now parse command stream */
-+ r = dev_priv->cs.parse(dev, fpriv, ib, packets, cs->dwords);
++ r = dev_priv->cs.parse(&parser);
+ if (r) {
+ goto out;
+ }
@@ -24958,45 +25175,61 @@
+ dev_priv->cs.id_emit(dev, &cs_id);
+ COMMIT_RING();
+
-+ DRM_COPY_TO_USER(&cs->cs_id, &cs_id, sizeof(uint32_t));
++ cs->cs_id = cs_id;
+out:
-+ dev_priv->cs.ib_free(dev, ib, cs->dwords);
++ dev_priv->cs.ib_free(&parser);
+ drm_free(packets, size, DRM_MEM_DRIVER);
+ return r;
+}
+
+/* for non-mm */
-+static int radeon_nomm_relocate(struct drm_device *dev, struct drm_file *file_priv, uint32_t *reloc, uint32_t *offset)
++static int radeon_nomm_relocate(struct drm_radeon_cs_parser *parser, uint32_t *reloc, uint32_t *offset)
+{
+ *offset = reloc[1];
+ return 0;
+}
+#define RELOC_SIZE 2
++#define RELOC_SIZE_NEW 0
+#define RADEON_2D_OFFSET_MASK 0x3fffff
+
-+static __inline__ int radeon_cs_relocate_packet0(struct drm_device *dev, struct drm_file *file_priv,
-+ uint32_t *packets, uint32_t offset_dw)
++static __inline__ int radeon_cs_relocate_packet0(struct drm_radeon_cs_parser *parser, uint32_t offset_dw)
+{
++ struct drm_device *dev = parser->dev;
+ drm_radeon_private_t *dev_priv = dev->dev_private;
-+ uint32_t hdr = packets[offset_dw];
-+ uint32_t reg = (hdr & R300_CP_PACKET0_REG_MASK) << 2;
-+ uint32_t val = packets[offset_dw + 1];
-+ uint32_t packet3_hdr = packets[offset_dw+2];
++ uint32_t hdr, reg, val, packet3_hdr;
+ uint32_t tmp, offset;
++ struct drm_radeon_kernel_chunk *ib_chunk;
+ int ret;
+
++ ib_chunk = &parser->chunks[parser->ib_index];
++// if (parser->reloc_index == -1)
++// is_old = 1;
++
++ hdr = ib_chunk->kdata[offset_dw];
++ reg = (hdr & R300_CP_PACKET0_REG_MASK) << 2;
++ val = ib_chunk->kdata[offset_dw + 1];
++ packet3_hdr = ib_chunk->kdata[offset_dw + 2];
++
+ /* this is too strict we may want to expand the length in the future and have
+ old kernels ignore it. */
-+ if (packet3_hdr != (RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16))) {
-+ DRM_ERROR("Packet 3 was %x should have been %x: reg is %x\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16), reg);
-+ return -EINVAL;
++ if (parser->reloc_index == -1) {
++ if (packet3_hdr != (RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16))) {
++ DRM_ERROR("Packet 3 was %x should have been %x: reg is %x\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16), reg);
++ return -EINVAL;
++ }
++ } else {
++ if (packet3_hdr != (RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE_NEW << 16))) {
++ DRM_ERROR("Packet 3 was %x should have been %x: reg is %x\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE_NEW << 16), reg);
++ return -EINVAL;
++
++ }
+ }
+
+ switch(reg) {
+ case RADEON_DST_PITCH_OFFSET:
+ case RADEON_SRC_PITCH_OFFSET:
+ /* pass in the start of the reloc */
-+ ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + 2, &offset);
++ ret = dev_priv->cs.relocate(parser, ib_chunk->kdata + offset_dw + 2, &offset);
+ if (ret)
+ return ret;
+ tmp = (val & RADEON_2D_OFFSET_MASK) << 10;
@@ -25014,7 +25247,7 @@
+ case RADEON_PP_TXOFFSET_1:
+ case R300_TX_OFFSET_0:
+ case R300_TX_OFFSET_0+4:
-+ ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + 2, &offset);
++ ret = dev_priv->cs.relocate(parser, ib_chunk->kdata + offset_dw + 2, &offset);
+ if (ret)
+ return ret;
+
@@ -25025,25 +25258,32 @@
+ break;
+ }
+
-+ packets[offset_dw + 1] = val;
++ ib_chunk->kdata[offset_dw + 1] = val;
+ return 0;
+}
+
-+static int radeon_cs_relocate_packet3(struct drm_device *dev, struct drm_file *file_priv,
-+ uint32_t *packets, uint32_t offset_dw)
++static int radeon_cs_relocate_packet3(struct drm_radeon_cs_parser *parser,
++ uint32_t offset_dw)
+{
-+ drm_radeon_private_t *dev_priv = dev->dev_private;
-+ uint32_t hdr = packets[offset_dw];
-+ int num_dw = (hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16;
-+ uint32_t reg = hdr & 0xff00;
++ drm_radeon_private_t *dev_priv = parser->dev->dev_private;
++ uint32_t hdr, num_dw, reg;
+ uint32_t offset, val, tmp;
+ int ret;
++ struct drm_radeon_kernel_chunk *ib_chunk;
++
++ ib_chunk = &parser->chunks[parser->ib_index];
++// if (parser->reloc_index == -1)
++// is_old = 1;
++
++ hdr = ib_chunk->kdata[offset_dw];
++ num_dw = (hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16;
++ reg = hdr & 0xff00;
+
+ switch(reg) {
+ case RADEON_CNTL_HOSTDATA_BLT:
+ {
-+ val = packets[offset_dw + 2];
-+ ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + num_dw + 2, &offset);
++ val = ib_chunk->kdata[offset_dw + 2];
++ ret = dev_priv->cs.relocate(parser, ib_chunk->kdata + offset_dw + num_dw + 2, &offset);
+ if (ret)
+ return ret;
+
@@ -25053,7 +25293,7 @@
+ offset >>= 10;
+ val |= offset;
+
-+ packets[offset_dw + 2] = val;
++ ib_chunk->kdata[offset_dw + 2] = val;
+ }
+ default:
+ DRM_ERROR("reg is %x, not RADEON_CNTL_HOSTDATA_BLT\n", reg);
@@ -25062,17 +25302,16 @@
+ return 0;
+}
+
-+int radeon_cs_packet0(struct drm_device *dev, struct drm_file *file_priv,
-+ uint32_t *packets, uint32_t offset_dw)
++int radeon_cs_packet0(struct drm_radeon_cs_parser *parser, uint32_t offset_dw)
+{
-+ drm_radeon_private_t *dev_priv = dev->dev_private;
-+ uint32_t hdr = packets[offset_dw];
-+ int num_dw = ((hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16) + 2;
-+ int need_reloc = 0;
-+ int reg = (hdr & R300_CP_PACKET0_REG_MASK) << 2;
++ uint32_t hdr, num_dw, reg;
+ int count_dw = 1;
+ int ret;
+
++ hdr = parser->chunks[parser->ib_index].kdata[offset_dw];
++ num_dw = ((hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16) + 2;
++ reg = (hdr & R300_CP_PACKET0_REG_MASK) << 2;
++
+ while (count_dw < num_dw) {
+ /* need to have something like the r300 validation here -
+ list of allowed registers */
@@ -25093,7 +25332,7 @@
+ return -EINVAL;
+ }
+
-+ ret = radeon_cs_relocate_packet0(dev, file_priv, packets, offset_dw);
++ ret = radeon_cs_relocate_packet0(parser, offset_dw);
+ if (ret) {
+ DRM_ERROR("failed to relocate packet\n");
+ return ret;
@@ -25114,24 +25353,25 @@
+ return 0;
+}
+
-+int radeon_cs_parse(struct drm_device *dev, struct drm_file *file_priv,
-+ void *ib, uint32_t *packets, uint32_t dwords)
++int radeon_cs_parse(struct drm_radeon_cs_parser *parser)
+{
-+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ volatile int rb;
-+ int size_dw = dwords;
++ struct drm_radeon_kernel_chunk *ib_chunk;
+ /* scan the packet for various things */
-+ int count_dw = 0;
++ int count_dw = 0, size_dw;
+ int ret = 0;
+
++ ib_chunk = &parser->chunks[parser->ib_index];
++ size_dw = ib_chunk->length_dw;
++
+ while (count_dw < size_dw && ret == 0) {
-+ int hdr = packets[count_dw];
++ int hdr = ib_chunk->kdata[count_dw];
+ int num_dw = (hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16;
+ int reg;
+
+ switch (hdr & RADEON_CP_PACKET_MASK) {
+ case RADEON_CP_PACKET0:
-+ ret = radeon_cs_packet0(dev, file_priv, packets, count_dw);
++ ret = radeon_cs_packet0(parser, count_dw);
+ break;
+ case RADEON_CP_PACKET1:
+ case RADEON_CP_PACKET2:
@@ -25144,7 +25384,7 @@
+
+ switch(reg) {
+ case RADEON_CNTL_HOSTDATA_BLT:
-+ radeon_cs_relocate_packet3(dev, file_priv, packets, count_dw);
++ radeon_cs_relocate_packet3(parser, count_dw);
+ break;
+
+ case RADEON_CNTL_BITBLT_MULTI:
@@ -25175,10 +25415,10 @@
+
+
+ /* copy the packet into the IB */
-+ memcpy(ib, packets, dwords * sizeof(uint32_t));
++ memcpy(parser->ib, ib_chunk->kdata, ib_chunk->length_dw * sizeof(uint32_t));
+
+ /* read back last byte to flush WC buffers */
-+ rb = readl((ib + (dwords-1) * sizeof(uint32_t)));
++ rb = readl((parser->ib + (ib_chunk->length_dw-1) * sizeof(uint32_t)));
+
+ return 0;
+}
@@ -25512,10 +25752,10 @@
+
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
new file mode 100644
-index 0000000..9e9435a
+index 0000000..95cccdf
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_display.c
-@@ -0,0 +1,710 @@
+@@ -0,0 +1,717 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -26119,17 +26359,22 @@
+ if (fb->fbdev)
+ radeonfb_remove(dev, fb);
+
++ if (radeon_fb->obj) {
++ mutex_lock(&dev->struct_mutex);
++ drm_gem_object_unreference(radeon_fb->obj);
++ mutex_unlock(&dev->struct_mutex);
++ }
+ drm_framebuffer_cleanup(fb);
+ kfree(radeon_fb);
+}
+
+static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
-+ struct drm_file *file_priv,
-+ unsigned int *handle)
++ struct drm_file *file_priv,
++ unsigned int *handle)
+{
-+ struct drm_gem_object *object = fb->mm_private;
++ struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
+
-+ return drm_gem_handle_create(file_priv, object, handle);
++ return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
+}
+
+static const struct drm_framebuffer_funcs radeon_fb_funcs = {
@@ -26140,7 +26385,7 @@
+struct drm_framebuffer *
+radeon_framebuffer_create(struct drm_device *dev,
+ struct drm_mode_fb_cmd *mode_cmd,
-+ void *mm_private)
++ struct drm_gem_object *obj)
+{
+ struct radeon_framebuffer *radeon_fb;
+
@@ -26149,8 +26394,10 @@
+ return NULL;
+
+ drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
-+ drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd, mm_private);
-+
++ drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
++
++ radeon_fb->obj = obj;
++
+ return &radeon_fb->base;
+}
+
@@ -26161,11 +26408,11 @@
+{
+
+ struct radeon_framebuffer *radeon_fb;
-+ void *mm_private;
++ struct drm_gem_object *obj;
+
-+ mm_private = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
++ obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
+
-+ return radeon_framebuffer_create(dev, mode_cmd, mm_private);
++ return radeon_framebuffer_create(dev, mode_cmd, obj);
+}
+
+static const struct drm_mode_config_funcs radeon_mode_funcs = {
@@ -26365,7 +26612,7 @@
}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index 4dbb813..dff981f 100644
+index 4dbb813..cf7761c 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -34,6 +34,8 @@
@@ -26455,7 +26702,7 @@
typedef struct drm_radeon_freelist {
unsigned int age;
-@@ -226,14 +265,68 @@ struct radeon_virt_surface {
+@@ -226,14 +265,86 @@ struct radeon_virt_surface {
#define RADEON_FLUSH_EMITED (1 < 0)
#define RADEON_PURGE_EMITED (1 < 1)
@@ -26494,6 +26741,23 @@
- u32 fb_location;
- u32 fb_size;
- int new_memmap;
++struct drm_radeon_kernel_chunk {
++ uint32_t chunk_id;
++ uint32_t length_dw;
++ uint32_t __user *chunk_data;
++ uint32_t *kdata;
++};
++
++struct drm_radeon_cs_parser {
++ struct drm_device *dev;
++ struct drm_file *file_priv;
++ uint32_t num_chunks;
++ struct drm_radeon_kernel_chunk *chunks;
++ int ib_index;
++ int reloc_index;
++ void *ib;
++};
++
+/* command submission struct */
+struct drm_radeon_cs_priv {
+ uint32_t id_wcnt;
@@ -26501,35 +26765,36 @@
+ uint32_t id_last_wcnt;
+ uint32_t id_last_scnt;
+
-+ int (*parse)(struct drm_device *dev, struct drm_file *file_priv,
-+ void *ib, uint32_t *packets, uint32_t dwords);
++ int (*parse)(struct drm_radeon_cs_parser *parser);
+ void (*id_emit)(struct drm_device *dev, uint32_t *id);
+ uint32_t (*id_last_get)(struct drm_device *dev);
+ /* this ib handling callback are for hidding memory manager drm
+ * from memory manager less drm, free have to emit ib discard
+ * sequence into the ring */
-+ int (*ib_get)(struct drm_device *dev, void **ib, uint32_t dwords, uint32_t *card_offset);
++ int (*ib_get)(struct drm_radeon_cs_parser *parser, uint32_t *card_offset);
+ uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib);
-+ void (*ib_free)(struct drm_device *dev, void *ib, uint32_t dwords);
++ void (*ib_free)(struct drm_radeon_cs_parser *parser);
+ /* do a relocation either MM or non-MM */
-+ int (*relocate)(struct drm_device *dev, struct drm_file *file_priv,
-+ uint32_t *reloc, uint32_t *offset);
++ int (*relocate)(struct drm_radeon_cs_parser *parser,
++ uint32_t *reloc, uint32_t *offset);
+};
+
++
++
+struct radeon_pm_regs {
+ uint32_t crtc_ext_cntl;
+ uint32_t bios_scratch[8];
+};
-
++
+typedef struct drm_radeon_private {
+ drm_radeon_ring_buffer_t ring;
-+
+
+ bool new_memmap;
+ bool user_mm_enable; /* userspace enabled the memory manager */
int gart_size;
u32 gart_vm_start;
unsigned long gart_buffers_offset;
-@@ -249,8 +342,6 @@ typedef struct drm_radeon_private {
+@@ -249,8 +360,6 @@ typedef struct drm_radeon_private {
int usec_timeout;
@@ -26538,7 +26803,7 @@
struct {
u32 boxes;
int freelist_timeouts;
-@@ -286,8 +377,6 @@ typedef struct drm_radeon_private {
+@@ -286,8 +395,6 @@ typedef struct drm_radeon_private {
unsigned long buffers_offset;
unsigned long gart_textures_offset;
@@ -26547,7 +26812,7 @@
drm_local_map_t *cp_ring;
drm_local_map_t *ring_rptr;
drm_local_map_t *gart_textures;
-@@ -296,8 +385,8 @@ typedef struct drm_radeon_private {
+@@ -296,8 +403,8 @@ typedef struct drm_radeon_private {
struct mem_block *fb_heap;
/* SW interrupt */
@@ -26557,7 +26822,7 @@
int vblank_crtc;
uint32_t irq_enable_reg;
int irq_enabled;
-@@ -306,9 +395,6 @@ typedef struct drm_radeon_private {
+@@ -306,9 +413,6 @@ typedef struct drm_radeon_private {
struct radeon_surface surfaces[RADEON_MAX_SURFACES];
struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
@@ -26567,7 +26832,7 @@
u32 scratch_ages[5];
-@@ -318,6 +404,39 @@ typedef struct drm_radeon_private {
+@@ -318,6 +422,39 @@ typedef struct drm_radeon_private {
int num_gb_pipes;
int track_flush;
@@ -26607,7 +26872,7 @@
} drm_radeon_private_t;
typedef struct drm_radeon_buf_priv {
-@@ -332,8 +451,12 @@ typedef struct drm_radeon_kcmd_buffer {
+@@ -332,8 +469,12 @@ typedef struct drm_radeon_kcmd_buffer {
} drm_radeon_kcmd_buffer_t;
extern int radeon_no_wb;
@@ -26620,7 +26885,7 @@
/* Check whether the given hardware address is inside the framebuffer or the
* GART area.
-@@ -367,12 +490,9 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
+@@ -367,12 +508,9 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
@@ -26634,7 +26899,7 @@
extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
-@@ -400,16 +520,19 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
+@@ -400,16 +538,19 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
extern int radeon_driver_unload(struct drm_device *dev);
extern int radeon_driver_firstopen(struct drm_device *dev);
@@ -26658,7 +26923,7 @@
/* r300_cmdbuf.c */
extern void r300_init_reg_flags(struct drm_device *dev);
-@@ -417,6 +540,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -417,6 +558,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
struct drm_file *file_priv,
drm_radeon_kcmd_buffer_t *cmdbuf);
@@ -26670,7 +26935,7 @@
/* Flags for stats.boxes
*/
#define RADEON_BOX_DMA_IDLE 0x1
-@@ -425,10 +553,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -425,10 +571,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_BOX_WAIT_IDLE 0x8
#define RADEON_BOX_TEXTURE_LOAD 0x10
@@ -26685,7 +26950,7 @@
#define RADEON_AGP_COMMAND 0x0f60
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
# define RADEON_AGP_ENABLE (1<<8)
-@@ -554,16 +686,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -554,16 +704,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define R520_MC_IND_WR_EN (1 << 24)
#define R520_MC_IND_DATA 0x74
@@ -26702,7 +26967,7 @@
#define RADEON_MPP_TB_CONFIG 0x01c0
#define RADEON_MEM_CNTL 0x0140
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
-@@ -628,14 +750,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -628,14 +768,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_SCRATCH_REG3 0x15ec
#define RADEON_SCRATCH_REG4 0x15f0
#define RADEON_SCRATCH_REG5 0x15f4
@@ -26729,7 +26994,7 @@
#define RADEON_GEN_INT_CNTL 0x0040
# define RADEON_CRTC_VBLANK_MASK (1 << 0)
-@@ -654,10 +785,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -654,10 +803,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
# define RADEON_SW_INT_FIRE (1 << 26)
# define R500_DISPLAY_INT_STATUS (1 << 0)
@@ -26745,7 +27010,7 @@
#define RADEON_ISYNC_CNTL 0x1724
# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
-@@ -696,12 +828,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -696,12 +846,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_PP_TXFILTER_1 0x1c6c
#define RADEON_PP_TXFILTER_2 0x1c84
@@ -26769,7 +27034,7 @@
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
-@@ -728,11 +865,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -728,11 +883,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
# define R300_ZC_BUSY (1 << 31)
@@ -26781,7 +27046,7 @@
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_RB3D_DC_FLUSH (2 << 0)
# define R300_RB3D_DC_FREE (2 << 2)
-@@ -740,15 +872,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -740,15 +890,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
@@ -26801,7 +27066,7 @@
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
-@@ -1009,27 +1141,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1009,27 +1159,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_NUM_VERTICES_SHIFT 16
#define RADEON_COLOR_FORMAT_CI8 2
@@ -26829,7 +27094,7 @@
#define R200_PP_TXCBLEND_0 0x2f00
#define R200_PP_TXCBLEND_1 0x2f10
-@@ -1140,16 +1251,44 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1140,16 +1269,44 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
@@ -26876,7 +27141,7 @@
#define R500_D1CRTC_STATUS 0x609c
#define R500_D2CRTC_STATUS 0x689c
#define R500_CRTC_V_BLANK (1<<0)
-@@ -1190,19 +1329,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1190,19 +1347,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_RING_HIGH_MARK 128
#define RADEON_PCIGART_TABLE_SIZE (32*1024)
@@ -26920,7 +27185,7 @@
#define RADEON_WRITE_PCIE(addr, val) \
do { \
RADEON_WRITE8(RADEON_PCIE_INDEX, \
-@@ -1259,7 +1415,7 @@ do { \
+@@ -1259,7 +1433,7 @@ do { \
#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
@@ -26929,7 +27194,7 @@
} while (0)
#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
-@@ -1336,8 +1492,9 @@ do { \
+@@ -1336,8 +1510,9 @@ do { \
} while (0)
#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
@@ -26941,7 +27206,7 @@
if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
int __ret = radeon_do_cp_idle( dev_priv ); \
if ( __ret ) return __ret; \
-@@ -1443,4 +1600,143 @@ do { \
+@@ -1443,4 +1618,144 @@ do { \
write &= mask; \
} while (0)
@@ -27073,6 +27338,7 @@
+extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
+extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *master);
+extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
++extern int radeon_cs2_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
+extern int radeon_cs_init(struct drm_device *dev);
+void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master);
+void radeon_init_memory_map(struct drm_device *dev);
@@ -28200,10 +28466,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
new file mode 100644
-index 0000000..ea2f39d
+index 0000000..cbf9a83
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
-@@ -0,0 +1,921 @@
+@@ -0,0 +1,922 @@
+/*
+ * Copyright © 2007 David Airlie
+ *
@@ -29114,7 +29380,8 @@
+ unregister_framebuffer(info);
+ drm_bo_kunmap(&radeon_fb->kmap_obj);
+ mutex_lock(&dev->struct_mutex);
-+ drm_gem_object_unreference(fb->mm_private);
++ drm_gem_object_unreference(radeon_fb->obj);
++ radeon_fb->obj = NULL;
+ mutex_unlock(&dev->struct_mutex);
+ framebuffer_release(info);
+ }
@@ -29232,10 +29499,10 @@
+
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
new file mode 100644
-index 0000000..4b15fac
+index 0000000..6c62620
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
-@@ -0,0 +1,1616 @@
+@@ -0,0 +1,1646 @@
+/*
+ * Copyright 2008 Red Hat Inc.
+ *
@@ -29364,7 +29631,6 @@
+ struct drm_radeon_gem_object *obj_priv;
+ struct drm_gem_object *obj;
+ int ret = 0;
-+ uint32_t flags;
+ int handle;
+
+ /* create a gem object to contain this object in */
@@ -29395,8 +29661,6 @@
+
+int radeon_gem_set_domain(struct drm_gem_object *obj, uint32_t read_domains, uint32_t write_domain, uint32_t *flags_p, bool unfenced)
+{
-+ struct drm_device *dev = obj->dev;
-+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ struct drm_radeon_gem_object *obj_priv;
+ uint32_t flags = 0;
+ int ret;
@@ -29854,7 +30118,7 @@
+ base = dev->agp->base;
+ if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
+ base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
-+ DRM_INFO("Can't use agp base @0x%08xlx, won't fit\n",
++ DRM_INFO("Can't use agp base @0x%08lx, won't fit\n",
+ dev->agp->base);
+ base = 0;
+ }
@@ -29970,7 +30234,7 @@
+ return -EINVAL;
+ }
+
-+ DRM_DEBUG("Ring ptr %p mapped at %d %p, read ptr %p maped at %d %p\n",
++ DRM_DEBUG("Ring ptr %p mapped at %ld %p, read ptr %p maped at %ld %p\n",
+ dev_priv->mm.ring.bo, dev_priv->mm.ring.bo->offset, dev_priv->mm.ring.kmap.virtual,
+ dev_priv->mm.ring_read.bo, dev_priv->mm.ring_read.bo->offset, dev_priv->mm.ring_read.kmap.virtual);
+
@@ -30067,7 +30331,6 @@
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ uint32_t crtc_gen_cntl;
-+ int ret;
+
+ crtc_gen_cntl = RADEON_READ(RADEON_CRTC_GEN_CNTL);
+ if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
@@ -30086,7 +30349,6 @@
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ uint32_t crtc2_gen_cntl;
-+ struct timeval timeout;
+
+ crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
+ if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
@@ -30155,7 +30417,6 @@
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ u32 mem_size, aper_size;
-+ u32 tmp;
+
+ dev_priv->mc_fb_location = radeon_read_fb_location(dev_priv);
+ radeon_read_agp_location(dev_priv, &dev_priv->mc_agp_loc_lo, &dev_priv->mc_agp_loc_hi);
@@ -30386,11 +30647,11 @@
+
+#define RADEON_NUM_IB (RADEON_IB_MEMORY / RADEON_IB_SIZE)
+
-+int radeon_gem_ib_get(struct drm_device *dev, void **ib, uint32_t dwords, uint32_t *card_offset)
++int radeon_gem_ib_get(struct drm_radeon_cs_parser *parser, uint32_t *card_offset)
+{
+ int i, index = -1;
+ int ret;
-+ drm_radeon_private_t *dev_priv = dev->dev_private;
++ drm_radeon_private_t *dev_priv = parser->dev->dev_private;
+
+ for (i = 0; i < RADEON_NUM_IB; i++) {
+ if (!(dev_priv->ib_alloc_bitmap & (1 << i))){
@@ -30416,12 +30677,12 @@
+ }
+
+ if (index == -1) {
-+ DRM_ERROR("Major case fail to allocate IB from freelist %x\n", dev_priv->ib_alloc_bitmap);
++ DRM_ERROR("Major case fail to allocate IB from freelist %llx\n", dev_priv->ib_alloc_bitmap);
+ return -EINVAL;
+ }
+
+
-+ if (dwords > RADEON_IB_SIZE / sizeof(uint32_t))
++ if (parser->chunks[parser->ib_index].length_dw > RADEON_IB_SIZE / sizeof(uint32_t))
+ return -EINVAL;
+
+ ret = drm_bo_do_validate(dev_priv->ib_objs[index]->bo, 0,
@@ -30433,25 +30694,24 @@
+ }
+
+ *card_offset = dev_priv->gart_vm_start + dev_priv->ib_objs[index]->bo->offset;
-+ *ib = dev_priv->ib_objs[index]->kmap.virtual;
++ parser->ib = dev_priv->ib_objs[index]->kmap.virtual;
+ dev_priv->ib_alloc_bitmap |= (1 << i);
+ return 0;
+}
+
-+static void radeon_gem_ib_free(struct drm_device *dev, void *ib, uint32_t dwords)
++static void radeon_gem_ib_free(struct drm_radeon_cs_parser *parser)
+{
++ struct drm_device *dev = parser->dev;
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ struct drm_fence_object *fence;
+ int ret;
+ int i;
+
+ for (i = 0; i < RADEON_NUM_IB; i++) {
-+
-+ if (dev_priv->ib_objs[i]->kmap.virtual == ib) {
++ if (dev_priv->ib_objs[i]->kmap.virtual == parser->ib) {
+ /* emit a fence object */
+ ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &fence);
+ if (ret) {
-+
+ drm_putback_buffer_objects(dev);
+ }
+ /* dereference the fence object */
@@ -30481,21 +30741,58 @@
+ return 0;
+}
+
-+static int radeon_gem_relocate(struct drm_device *dev, struct drm_file *file_priv,
-+ uint32_t *reloc, uint32_t *offset)
++static int radeon_gem_find_reloc(struct drm_radeon_cs_parser *parser,
++ uint32_t offset, uint32_t *handle,
++ uint32_t *read_domains, uint32_t *write_domain)
+{
++ struct drm_device *dev = parser->dev;
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++ struct drm_radeon_kernel_chunk *reloc_chunk = &parser->chunks[parser->reloc_index];
++
++ if (!reloc_chunk->kdata)
++ return -EINVAL;
++
++ if (offset > reloc_chunk->length_dw){
++ DRM_ERROR("Offset larger than chunk %d %d\n", offset, reloc_chunk->length_dw);
++ return -EINVAL;
++ }
++
++ *handle = reloc_chunk->kdata[offset];
++ *read_domains = reloc_chunk->kdata[offset + 1];
++ *write_domain = reloc_chunk->kdata[offset + 2];
++ return 0;
++}
++
++static int radeon_gem_relocate(struct drm_radeon_cs_parser *parser,
++ uint32_t *reloc, uint32_t *offset)
++{
++ struct drm_device *dev = parser->dev;
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+ /* relocate the handle */
-+ uint32_t read_domains = reloc[2];
-+ uint32_t write_domain = reloc[3];
++ uint32_t read_domains, write_domain;
+ struct drm_gem_object *obj;
+ int flags = 0;
+ int ret;
+ struct drm_radeon_gem_object *obj_priv;
+
-+ obj = drm_gem_object_lookup(dev, file_priv, reloc[1]);
-+ if (!obj)
-+ return -EINVAL;
++ if (parser->reloc_index == -1) {
++ obj = drm_gem_object_lookup(dev, parser->file_priv, reloc[1]);
++ if (!obj)
++ return -EINVAL;
++ read_domains = reloc[2];
++ write_domain = reloc[3];
++ } else {
++ uint32_t handle;
++
++ /* have to lookup handle in other chunk */
++ ret = radeon_gem_find_reloc(parser, reloc[1], &handle, &read_domains, &write_domain);
++ if (ret < 0)
++ return ret;
++
++ obj = drm_gem_object_lookup(dev, parser->file_priv, handle);
++ if (!obj)
++ return -EINVAL;
++ }
+
+ obj_priv = obj->driver_private;
+ radeon_gem_set_domain(obj, read_domains, write_domain, &flags, false);
@@ -30783,7 +31080,7 @@
+ DRM_DEBUG("\n");
+ radeon_gem_addbufs(dev);
+
-+ DRM_DEBUG("%x %d\n", dev_priv->mm.dma_bufs.bo->map_list.hash.key, size);
++ DRM_DEBUG("%lx %d\n", dev_priv->mm.dma_bufs.bo->map_list.hash.key, size);
+ dev->agp_buffer_token = dev_priv->mm.dma_bufs.bo->map_list.hash.key << PAGE_SHIFT;
+ dev_priv->mm.fake_agp_map.handle = dev_priv->mm.dma_bufs.kmap.virtual;
+ dev_priv->mm.fake_agp_map.size = size;
@@ -31113,7 +31410,7 @@
ret = drm_vblank_init(dev, 2);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
new file mode 100644
-index 0000000..820bd54
+index 0000000..c0a3c0f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -0,0 +1,1075 @@
@@ -31350,7 +31647,7 @@
+
+ radeon_fb = to_radeon_framebuffer(crtc->fb);
+
-+ obj = radeon_fb->base.mm_private;
++ obj = radeon_fb->obj;
+ obj_priv = obj->driver_private;
+
+ crtc_offset = obj_priv->bo->offset;
@@ -31773,7 +32070,7 @@
+
+ radeon_fb = to_radeon_framebuffer(crtc->fb);
+
-+ obj = radeon_fb->base.mm_private;
++ obj = radeon_fb->obj;
+ obj_priv = obj->driver_private;
+
+ crtc2_offset = obj_priv->bo->offset;
@@ -33584,10 +33881,10 @@
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
new file mode 100644
-index 0000000..fef2738
+index 0000000..9ba4688
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
-@@ -0,0 +1,350 @@
+@@ -0,0 +1,351 @@
+/*
+ * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
+ * VA Linux Systems Inc., Fremont, California.
@@ -33839,6 +34136,7 @@
+struct radeon_framebuffer {
+ struct drm_framebuffer base;
+ struct drm_bo_kmap_obj kmap_obj;
++ struct drm_gem_object *obj;
+};
+
+extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
@@ -33907,7 +34205,7 @@
+ u16 blue, int regno);
+struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
+ struct drm_mode_fb_cmd *mode_cmd,
-+ void *mm_private);
++ struct drm_gem_object *obj);
+
+int radeonfb_probe(struct drm_device *dev);
+
@@ -33940,7 +34238,7 @@
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
new file mode 100644
-index 0000000..df2739f
+index 0000000..1df4375
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -0,0 +1,248 @@
@@ -34000,10 +34298,10 @@
+ if (!radeon_fb)
+ continue;
+
-+ if (!radeon_fb->base.mm_private)
++ if (!radeon_fb->obj)
+ continue;
+
-+ radeon_gem_object_unpin(radeon_fb->base.mm_private);
++ radeon_gem_object_unpin(radeon_fb->obj);
+ }
+
+ if (!(dev_priv->flags & RADEON_IS_IGP))
@@ -34121,10 +34419,10 @@
+ if (!radeon_fb)
+ continue;
+
-+ if (!radeon_fb->base.mm_private)
++ if (!radeon_fb->obj)
+ continue;
+
-+ radeon_gem_object_pin(radeon_fb->base.mm_private,
++ radeon_gem_object_pin(radeon_fb->obj,
+ PAGE_SIZE, RADEON_GEM_DOMAIN_VRAM);
+ }
+ /* blat the mode back in */
@@ -39542,7 +39840,7 @@
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
-index 5d7153f..399471f 100644
+index 5d7153f..5dbff1c 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -305,8 +305,9 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
@@ -40215,7 +40513,7 @@
radeon_do_release(dev);
}
-@@ -3197,7 +3232,19 @@ struct drm_ioctl_desc radeon_ioctls[] = {
+@@ -3197,7 +3232,20 @@ struct drm_ioctl_desc radeon_ioctls[] = {
DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
@@ -40233,6 +40531,7 @@
+ DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_RADEON_GEM_INDIRECT, radeon_gem_indirect_ioctl, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH),
++ DRM_IOCTL_DEF(DRM_RADEON_CS2, radeon_cs2_ioctl, DRM_AUTH),
};
int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
@@ -40724,10 +41023,10 @@
#endif /* __KERNEL__ */
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
new file mode 100644
-index 0000000..6a73a71
+index 0000000..13fba4f
--- /dev/null
+++ b/include/drm/drm_crtc.h
-@@ -0,0 +1,717 @@
+@@ -0,0 +1,716 @@
+/*
+ * Copyright © 2006 Keith Packard
+ * Copyright © 2007 Intel Corporation
@@ -40970,7 +41269,6 @@
+ void *fbdev;
+ u32 pseudo_palette[17];
+ struct list_head filp_head;
-+ void *mm_private;
+};
+
+struct drm_property_blob {
@@ -41447,10 +41745,10 @@
+
diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
new file mode 100644
-index 0000000..01b1423
+index 0000000..c071915
--- /dev/null
+++ b/include/drm/drm_crtc_helper.h
-@@ -0,0 +1,97 @@
+@@ -0,0 +1,96 @@
+/*
+ * Copyright © 2006 Keith Packard
+ * Copyright © 2007 Intel Corporation
@@ -41528,8 +41826,7 @@
+extern bool drm_helper_crtc_in_use(struct drm_crtc *crtc);
+
+extern int drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
-+ struct drm_mode_fb_cmd *mode_cmd,
-+ void *mm_private);
++ struct drm_mode_fb_cmd *mode_cmd);
+
+static inline void drm_crtc_helper_add(struct drm_crtc *crtc, const struct drm_crtc_helper_funcs *funcs)
+{
@@ -43033,7 +43330,7 @@
int used; /* nr bytes in use */
int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
-index 73ff51f..1347faf 100644
+index 73ff51f..d63d20c 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -453,6 +453,15 @@ typedef struct {
@@ -43052,7 +43349,7 @@
} drm_radeon_sarea_t;
/* WARNING: If you change any of these defines, make sure to change the
-@@ -493,6 +502,18 @@ typedef struct {
+@@ -493,6 +502,19 @@ typedef struct {
#define DRM_RADEON_SURF_ALLOC 0x1a
#define DRM_RADEON_SURF_FREE 0x1b
@@ -43067,11 +43364,12 @@
+#define DRM_RADEON_GEM_INDIRECT 0x24 // temporary for X server
+
+#define DRM_RADEON_CS 0x25
++#define DRM_RADEON_CS2 0x26
+
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
-@@ -521,6 +542,19 @@ typedef struct {
+@@ -521,6 +543,20 @@ typedef struct {
#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
@@ -43086,12 +43384,13 @@
+#define DRM_IOCTL_RADEON_GEM_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INDIRECT, struct drm_radeon_gem_indirect)
+
+#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
++#define DRM_IOCTL_RADEON_CS2 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS2, struct drm_radeon_cs2)
+
+
typedef struct drm_radeon_init {
enum {
RADEON_INIT_CP = 0x01,
-@@ -677,6 +711,7 @@ typedef struct drm_radeon_indirect {
+@@ -677,6 +713,7 @@ typedef struct drm_radeon_indirect {
#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
@@ -43099,7 +43398,7 @@
typedef struct drm_radeon_getparam {
int param;
-@@ -731,6 +766,7 @@ typedef struct drm_radeon_setparam {
+@@ -731,6 +768,7 @@ typedef struct drm_radeon_setparam {
#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
@@ -43107,7 +43406,7 @@
/* 1.14: Clients can allocate/free a surface
*/
typedef struct drm_radeon_surface_alloc {
-@@ -746,4 +782,102 @@ typedef struct drm_radeon_surface_free {
+@@ -746,4 +784,117 @@ typedef struct drm_radeon_surface_free {
#define DRM_RADEON_VBLANK_CRTC1 1
#define DRM_RADEON_VBLANK_CRTC2 2
@@ -43201,11 +43500,26 @@
+
+
+struct drm_radeon_cs {
-+// uint32_t __user *packets;
+ uint32_t dwords;
+ uint32_t cs_id;
+ uint64_t packets;
++};
++
++#define RADEON_CHUNK_ID_RELOCS 0x01
++#define RADEON_CHUNK_ID_IB 0x02
++#define RADEON_CHUNK_ID_OLD 0xff
++
++struct drm_radeon_cs_chunk {
++ uint32_t chunk_id;
++ uint32_t length_dw;
++ uint64_t chunk_data;
++};
+
++struct drm_radeon_cs2 {
++ uint32_t num_chunks;
++ uint32_t cs_id;
++ uint64_t chunks; /* this points to uint64_t * which point to
++ cs chunks */
+};
+
+
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1087
retrieving revision 1.1088
diff -u -r1.1087 -r1.1088
--- kernel.spec 26 Oct 2008 11:45:02 -0000 1.1087
+++ kernel.spec 27 Oct 2008 06:52:25 -0000 1.1088
@@ -1870,6 +1870,9 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Mon Oct 27 2008 Dave Airlie <airlied at redhat.com> 2.6.27.4-52
+- drm-modesetting-radeon.patch - fix some kms issues + add better CS scheme
+
* Sun Oct 26 2008 Chuck Ebbert <cebbert at redhat.com> 2.6.27.4-51
- Linux 2.6.27.4
- Previous message (by thread): rpms/cryptopp/F-9 cryptopp-5.5.2-autotools.patch, NONE, 1.1 cryptopp-5.5.2-gcc4.3.patch, NONE, 1.1 cryptopp-5.5.2-nomars.patch, NONE, 1.1 cryptopp-remove-patented-code.sh, NONE, 1.1 cryptopp.spec, NONE, 1.1 .cvsignore, 1.1, 1.2 sources, 1.1, 1.2
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