rpms/kernel/devel drm-modesetting-radeon.patch, 1.42, 1.43 kernel.spec, 1.1093, 1.1094

Dave Airlie airlied at fedoraproject.org
Mon Oct 27 20:40:04 UTC 2008


Author: airlied

Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv14107

Modified Files:
	drm-modesetting-radeon.patch kernel.spec 
Log Message:
- add support for wait rendering API


drm-modesetting-radeon.patch:

Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-modesetting-radeon.patch,v
retrieving revision 1.42
retrieving revision 1.43
diff -u -r1.42 -r1.43
--- drm-modesetting-radeon.patch	27 Oct 2008 20:13:25 -0000	1.42
+++ drm-modesetting-radeon.patch	27 Oct 2008 20:40:04 -0000	1.43
@@ -1,3 +1,9 @@
+commit 927236acfb2a745d42c2f70c9099bdf664b2e26b
+Author: Dave Airlie <airlied at redhat.com>
+Date:   Tue Oct 28 06:35:10 2008 +1000
+
+    radeon: add wait rendering API
+
 commit c5ac6f0d9dedfaa78987d00ed2dfa7296ba55668
 Author: Dave Airlie <airlied at redhat.com>
 Date:   Tue Oct 28 06:05:58 2008 +1000
@@ -26625,7 +26631,7 @@
  }
  
 diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index 4dbb813..aff4f29 100644
+index 4dbb813..b430917 100644
 --- a/drivers/gpu/drm/radeon/radeon_drv.h
 +++ b/drivers/gpu/drm/radeon/radeon_drv.h
 @@ -34,6 +34,8 @@
@@ -26791,7 +26797,7 @@
 +	int (*relocate)(struct drm_radeon_cs_parser *parser,
 +			uint32_t *reloc, uint32_t *offset);
 +};
- 
++
 +
 +
 +struct radeon_pm_regs {
@@ -26801,7 +26807,7 @@
 +
 +typedef struct drm_radeon_private {
 +	drm_radeon_ring_buffer_t ring;
-+
+ 
 +	bool new_memmap;
 +	bool user_mm_enable; /* userspace enabled the memory manager */
  	int gart_size;
@@ -27246,7 +27252,7 @@
  	if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {		\
  		int __ret = radeon_do_cp_idle( dev_priv );		\
  		if ( __ret ) return __ret;				\
-@@ -1443,4 +1618,142 @@ do {									\
+@@ -1443,4 +1618,144 @@ do {									\
  	write &= mask;						\
  } while (0)
  
@@ -27361,6 +27367,8 @@
 +int radeon_gem_object_unpin(struct drm_gem_object *obj);
 +int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 +				struct drm_file *file_priv);
++int radeon_gem_wait_rendering(struct drm_device *dev, void *data,
++			      struct drm_file *file_priv);
 +struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment,
 +					       int initial_domain, bool discardable);
 +int radeon_modeset_init(struct drm_device *dev);
@@ -29537,10 +29545,10 @@
 +
 diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
 new file mode 100644
-index 0000000..ce33979
+index 0000000..f5d6b94
 --- /dev/null
 +++ b/drivers/gpu/drm/radeon/radeon_gem.c
-@@ -0,0 +1,1571 @@
+@@ -0,0 +1,1590 @@
 +/*
 + * Copyright 2008 Red Hat Inc.
 + *
@@ -29959,14 +29967,33 @@
 +	return 0;
 +}
 +
-+int radeon_gem_execbuffer(struct drm_device *dev, void *data,
-+			  struct drm_file *file_priv)
++int radeon_gem_wait_rendering(struct drm_device *dev, void *data,
++			      struct drm_file *file_priv)
 +{
-+	return -ENOSYS;
++	struct drm_radeon_gem_wait_rendering *args = data;
++	struct drm_gem_object *obj;
++	struct drm_radeon_gem_object *obj_priv;
++	int ret;
 +
 +
++	obj = drm_gem_object_lookup(dev, file_priv, args->handle);
++	if (obj == NULL)
++		return -EINVAL;
++
++	obj_priv = obj->driver_private;
++
++	mutex_lock(&obj_priv->bo->mutex);
++	ret = drm_bo_wait(obj_priv->bo, 0, 1, 1, 0);
++	mutex_unlock(&obj_priv->bo->mutex);
++	
++	mutex_lock(&dev->struct_mutex);
++	drm_gem_object_unreference(obj);
++	mutex_unlock(&dev->struct_mutex);
++	return ret;
 +}
 +
++
++
 +/*
 + * Depending on card genertation, chipset bugs, etc... the amount of vram
 + * accessible to the CPU can vary. This function is our best shot at figuring
@@ -39803,7 +39830,7 @@
 +
 +#endif
 diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
-index 5d7153f..3200f01 100644
+index 5d7153f..14ca916 100644
 --- a/drivers/gpu/drm/radeon/radeon_state.c
 +++ b/drivers/gpu/drm/radeon/radeon_state.c
 @@ -305,8 +305,9 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
@@ -40476,7 +40503,7 @@
  	radeon_do_release(dev);
  }
  
-@@ -3197,7 +3232,19 @@ struct drm_ioctl_desc radeon_ioctls[] = {
+@@ -3197,7 +3232,20 @@ struct drm_ioctl_desc radeon_ioctls[] = {
  	DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
  	DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
  	DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
@@ -40492,6 +40519,7 @@
 +	DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
 +	DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
 +	DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH),
++	DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_RENDERING, radeon_gem_wait_rendering, DRM_AUTH),
 +	DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH),
 +	DRM_IOCTL_DEF(DRM_RADEON_CS2, radeon_cs2_ioctl, DRM_AUTH),
  };
@@ -43292,7 +43320,7 @@
  	int used;		/* nr bytes in use */
  	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
 diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
-index 73ff51f..a2c6b79 100644
+index 73ff51f..770f6f0 100644
 --- a/include/drm/radeon_drm.h
 +++ b/include/drm/radeon_drm.h
 @@ -453,6 +453,15 @@ typedef struct {
@@ -43311,7 +43339,7 @@
  } drm_radeon_sarea_t;
  
  /* WARNING: If you change any of these defines, make sure to change the
-@@ -493,6 +502,18 @@ typedef struct {
+@@ -493,6 +502,19 @@ typedef struct {
  #define DRM_RADEON_SURF_ALLOC 0x1a
  #define DRM_RADEON_SURF_FREE  0x1b
  
@@ -43323,6 +43351,7 @@
 +#define DRM_RADEON_GEM_PREAD  0x21
 +#define DRM_RADEON_GEM_PWRITE 0x22
 +#define DRM_RADEON_GEM_SET_DOMAIN 0x23
++#define DRM_RADEON_GEM_WAIT_RENDERING 0x24
 +
 +#define DRM_RADEON_CS           0x25
 +#define DRM_RADEON_CS2       0x26
@@ -43330,7 +43359,7 @@
  #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
  #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
  #define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
-@@ -521,6 +542,19 @@ typedef struct {
+@@ -521,6 +543,19 @@ typedef struct {
  #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
  #define DRM_IOCTL_RADEON_SURF_FREE  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
  
@@ -43342,7 +43371,7 @@
 +#define DRM_IOCTL_RADEON_GEM_PREAD   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
 +#define DRM_IOCTL_RADEON_GEM_PWRITE   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
 +#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN  DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
-+
++#define DRM_IOCTL_RADEON_GEM_WAIT_RENDERING DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_RENDERING, struct drm_radeon_gem_wait_rendering) 
 +#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
 +#define DRM_IOCTL_RADEON_CS2 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS2, struct drm_radeon_cs2)
 +
@@ -43350,7 +43379,7 @@
  typedef struct drm_radeon_init {
  	enum {
  		RADEON_INIT_CP = 0x01,
-@@ -677,6 +711,7 @@ typedef struct drm_radeon_indirect {
+@@ -677,6 +712,7 @@ typedef struct drm_radeon_indirect {
  #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
  #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
  #define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
@@ -43358,7 +43387,7 @@
  
  typedef struct drm_radeon_getparam {
  	int param;
-@@ -731,6 +766,7 @@ typedef struct drm_radeon_setparam {
+@@ -731,6 +767,7 @@ typedef struct drm_radeon_setparam {
  #define RADEON_SETPARAM_NEW_MEMMAP 4		/* Use new memory map */
  #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
  #define RADEON_SETPARAM_VBLANK_CRTC 6           /* VBLANK CRTC */
@@ -43366,7 +43395,7 @@
  /* 1.14: Clients can allocate/free a surface
   */
  typedef struct drm_radeon_surface_alloc {
-@@ -746,4 +782,113 @@ typedef struct drm_radeon_surface_free {
+@@ -746,4 +783,114 @@ typedef struct drm_radeon_surface_free {
  #define	DRM_RADEON_VBLANK_CRTC1		1
  #define	DRM_RADEON_VBLANK_CRTC2		2
  
@@ -43406,7 +43435,8 @@
 +	uint32_t write_domain;
 +};
 +
-+struct drm_radeon_gem_exec_buffer {
++struct drm_radeon_gem_wait_rendering {
++	uint32_t handle;
 +};
 +
 +struct drm_radeon_gem_pin {


Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1093
retrieving revision 1.1094
diff -u -r1.1093 -r1.1094
--- kernel.spec	27 Oct 2008 20:13:25 -0000	1.1093
+++ kernel.spec	27 Oct 2008 20:40:04 -0000	1.1094
@@ -1876,6 +1876,9 @@
 
 %changelog
 * Tue Oct 28 2008 Dave Airlie <airlied at redhat.com>
+- add support for wait rendering API
+
+* Tue Oct 28 2008 Dave Airlie <airlied at redhat.com>
 - fix rs4xx bus mastering.
 
 * Mon Oct 27 2008 Jeremy Katz <katzj at redhat.com>




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