rpms/xorg-x11-drv-ati/devel radeon-6.12.0-git-fixes.patch, 1.2, 1.3 radeon-modeset.patch, 1.42, 1.43 radeon.xinf, 1.11, 1.12 xorg-x11-drv-ati.spec, 1.166, 1.167 radeon-r6xx-fix.patch, 1.5, NONE
Dave Airlie
airlied at fedoraproject.org
Mon Apr 6 05:38:40 UTC 2009
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Author: airlied
Update of /cvs/pkgs/rpms/xorg-x11-drv-ati/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv20343
Modified Files:
radeon-6.12.0-git-fixes.patch radeon-modeset.patch radeon.xinf
xorg-x11-drv-ati.spec
Removed Files:
radeon-r6xx-fix.patch
Log Message:
* Mon Apr 06 2009 Dave Airlie <airlied at redhat.com> 6.12.1-5
- radeon-modeset.patch: break APIs;
- radeon: move to latest git fixups
radeon-6.12.0-git-fixes.patch:
Index: radeon-6.12.0-git-fixes.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon-6.12.0-git-fixes.patch,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -r1.2 -r1.3
--- radeon-6.12.0-git-fixes.patch 1 Apr 2009 08:54:08 -0000 1.2
+++ radeon-6.12.0-git-fixes.patch 6 Apr 2009 05:38:09 -0000 1.3
@@ -12,10 +12,19 @@
xf86-video-ati)
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
-index d532f16..f31cadb 100644
+index d532f16..3304e84 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
-@@ -429,3 +429,10 @@
+@@ -345,6 +345,8 @@
+ #define PCI_CHIP_RV770_9456 0x9456
+ #define PCI_CHIP_RV770_945A 0x945A
+ #define PCI_CHIP_RV770_945B 0x945B
++#define PCI_CHIP_RV790_9460 0x9460
++#define PCI_CHIP_RV790_9462 0x9462
+ #define PCI_CHIP_RV770_946A 0x946A
+ #define PCI_CHIP_RV770_946B 0x946B
+ #define PCI_CHIP_RV770_947A 0x947A
+@@ -429,3 +431,10 @@
#define PCI_CHIP_RS780_9612 0x9612
#define PCI_CHIP_RS780_9613 0x9613
#define PCI_CHIP_RS780_9614 0x9614
@@ -26,11 +35,484 @@
+#define PCI_CHIP_RS880_9712 0x9712
+#define PCI_CHIP_RS880_9713 0x9713
+#define PCI_CHIP_RS880_9714 0x9714
+diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
+index 50db578..31c032b 100644
+--- a/src/atombios_crtc.c
++++ b/src/atombios_crtc.c
+@@ -517,6 +517,9 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
+
+ if (IS_AVIVO_VARIANT) {
+ uint32_t fb_format;
++#if X_BYTE_ORDER == X_BIG_ENDIAN
++ uint32_t fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
++#endif
+
+ switch (crtc->scrn->bitsPerPixel) {
+ case 15:
+@@ -524,10 +527,16 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ break;
+ case 16:
+ fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
++#if X_BYTE_ORDER == X_BIG_ENDIAN
++ fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
++#endif
+ break;
+ case 24:
+ case 32:
+ fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
++#if X_BYTE_ORDER == X_BIG_ENDIAN
++ fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
++#endif
+ break;
+ default:
+ FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
+@@ -555,6 +564,11 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
+ OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
+
++#if X_BYTE_ORDER == X_BIG_ENDIAN
++ if (info->ChipFamily >= CHIP_FAMILY_R600)
++ OUTREG(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
++#endif
++
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
diff --git a/src/atombios_output.c b/src/atombios_output.c
-index 35d1767..4af04c1 100644
+index 35d1767..60d6c10 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
-@@ -1406,8 +1406,12 @@ atombios_set_output_crtc_source(xf86OutputPtr output)
+@@ -61,7 +61,7 @@ const char *device_name[12] = {
+ };
+
+ static int
+-atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
++atombios_output_dac_setup(xf86OutputPtr output, int action)
+ {
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+@@ -71,6 +71,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
+ AtomBiosArgRec data;
+ unsigned char *space;
+ int index = 0, num = 0;
++ int clock = radeon_output->pixel_clock;
+
+ if (radeon_encoder == NULL)
+ return ATOM_NOT_IMPLEMENTED;
+@@ -90,7 +91,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
+ break;
+ }
+
+- disp_data.ucAction = ATOM_ENABLE;
++ disp_data.ucAction =action;
+
+ if (radeon_output->active_device & (ATOM_DEVICE_CRT_SUPPORT))
+ disp_data.ucDacStandard = ATOM_DAC1_PS2;
+@@ -113,7 +114,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
+ break;
+ }
+ }
+- disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
++ disp_data.usPixelClock = cpu_to_le16(clock / 10);
+
+ data.exec.index = index;
+ data.exec.dataSpace = (void *)&space;
+@@ -130,7 +131,7 @@ atombios_output_dac_setup(xf86OutputPtr output, DisplayModePtr mode)
+ }
+
+ static int
+-atombios_output_tv_setup(xf86OutputPtr output, DisplayModePtr mode)
++atombios_output_tv_setup(xf86OutputPtr output, int action)
+ {
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ radeon_tvout_ptr tvout = &radeon_output->tvout;
+@@ -138,10 +139,11 @@ atombios_output_tv_setup(xf86OutputPtr output, DisplayModePtr mode)
+ TV_ENCODER_CONTROL_PS_ALLOCATION disp_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
++ int clock = radeon_output->pixel_clock;
+
+ memset(&disp_data,0, sizeof(disp_data));
+
+- disp_data.sTVEncoder.ucAction = ATOM_ENABLE;
++ disp_data.sTVEncoder.ucAction = action;
+
+ if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT))
+ disp_data.sTVEncoder.ucTvStandard = ATOM_TV_CV;
+@@ -177,7 +179,7 @@ atombios_output_tv_setup(xf86OutputPtr output, DisplayModePtr mode)
+ }
+ }
+
+- disp_data.sTVEncoder.usPixelClock = cpu_to_le16(mode->Clock / 10);
++ disp_data.sTVEncoder.usPixelClock = cpu_to_le16(clock / 10);
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
+@@ -193,19 +195,21 @@ atombios_output_tv_setup(xf86OutputPtr output, DisplayModePtr mode)
+ }
+
+ int
+-atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
++atombios_external_tmds_setup(xf86OutputPtr output, int action)
+ {
++ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION disp_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
++ int clock = radeon_output->pixel_clock;
+
+ memset(&disp_data,0, sizeof(disp_data));
+
+- disp_data.sXTmdsEncoder.ucEnable = ATOM_ENABLE;
++ disp_data.sXTmdsEncoder.ucEnable = action;
+
+- if (mode->Clock > 165000)
++ if (clock > 165000)
+ disp_data.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
+
+ if (pScrn->rgbBits == 8)
+@@ -225,19 +229,21 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
+ }
+
+ static int
+-atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode)
++atombios_output_ddia_setup(xf86OutputPtr output, int action)
+ {
++ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ DVO_ENCODER_CONTROL_PS_ALLOCATION disp_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
++ int clock = radeon_output->pixel_clock;
+
+ memset(&disp_data,0, sizeof(disp_data));
+
+- disp_data.sDVOEncoder.ucAction = ATOM_ENABLE;
+- disp_data.sDVOEncoder.usPixelClock = cpu_to_le16(mode->Clock / 10);
++ disp_data.sDVOEncoder.ucAction = action;
++ disp_data.sDVOEncoder.usPixelClock = cpu_to_le16(clock / 10);
+
+- if (mode->Clock > 165000)
++ if (clock > 165000)
+ disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
+@@ -254,7 +260,7 @@ atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode)
+ }
+
+ static int
+-atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode)
++atombios_output_digital_setup(xf86OutputPtr output, int action)
+ {
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+@@ -267,6 +273,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode)
+ int index = 0;
+ int major, minor;
+ int lvds_misc = 0;
++ int clock = radeon_output->pixel_clock;
+
+ if (radeon_encoder == NULL)
+ return ATOM_NOT_IMPLEMENTED;
+@@ -308,11 +315,11 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode)
+ switch (minor) {
+ case 1:
+ disp_data.ucMisc = 0;
+- disp_data.ucAction = PANEL_ENCODER_ACTION_ENABLE;
++ disp_data.ucAction = action;
+ if ((radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) ||
+ (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_B))
+ disp_data.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
+- disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
++ disp_data.usPixelClock = cpu_to_le16(clock / 10);
+ if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
+ if (lvds_misc & (1 << 0))
+ disp_data.ucMisc |= PANEL_ENCODER_MISC_DUAL;
+@@ -321,7 +328,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode)
+ } else {
+ if (radeon_output->linkb)
+ disp_data.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
+- if (mode->Clock > 165000)
++ if (clock > 165000)
+ disp_data.ucMisc |= PANEL_ENCODER_MISC_DUAL;
+ if (pScrn->rgbBits == 8)
+ disp_data.ucMisc |= (1 << 1);
+@@ -331,7 +338,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode)
+ case 2:
+ case 3:
+ disp_data2.ucMisc = 0;
+- disp_data2.ucAction = PANEL_ENCODER_ACTION_ENABLE;
++ disp_data2.ucAction = action;
+ if (minor == 3) {
+ if (radeon_output->coherent_mode) {
+ disp_data2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
+@@ -341,7 +348,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode)
+ if ((radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) ||
+ (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_B))
+ disp_data2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
+- disp_data2.usPixelClock = cpu_to_le16(mode->Clock / 10);
++ disp_data2.usPixelClock = cpu_to_le16(clock / 10);
+ disp_data2.ucTruncate = 0;
+ disp_data2.ucSpatial = 0;
+ disp_data2.ucTemporal = 0;
+@@ -364,7 +371,7 @@ atombios_output_digital_setup(xf86OutputPtr output, DisplayModePtr mode)
+ } else {
+ if (radeon_output->linkb)
+ disp_data2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
+- if (mode->Clock > 165000)
++ if (clock > 165000)
+ disp_data2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
+ }
+ data.exec.pspace = &disp_data2;
+@@ -488,16 +495,17 @@ dp_link_clock_for_mode_clock(int mode_clock)
+ }
+
+ static int
+-atombios_output_dig_encoder_setup(xf86OutputPtr output, DisplayModePtr mode)
++atombios_output_dig_encoder_setup(xf86OutputPtr output, int action)
+ {
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+- RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
+ DIG_ENCODER_CONTROL_PS_ALLOCATION disp_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+ int index = 0, major, minor, num = 0;
++ int clock = radeon_output->pixel_clock;
++ int dig_block = radeon_output->dig_block;
+
+ if (radeon_encoder == NULL)
+ return ATOM_NOT_IMPLEMENTED;
+@@ -505,11 +513,11 @@ atombios_output_dig_encoder_setup(xf86OutputPtr output, DisplayModePtr mode)
+ memset(&disp_data,0, sizeof(disp_data));
+
+ if (IS_DCE32_VARIANT) {
+- if (radeon_crtc->crtc_id)
++ if (dig_block)
+ index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
+ else
+ index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
+- num = radeon_crtc->crtc_id + 1;
++ num = dig_block + 1;
+ } else {
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+@@ -529,8 +537,8 @@ atombios_output_dig_encoder_setup(xf86OutputPtr output, DisplayModePtr mode)
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+- disp_data.ucAction = ATOM_ENABLE;
+- disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
++ disp_data.ucAction = action;
++ disp_data.usPixelClock = cpu_to_le16(clock / 10);
+
+ if (IS_DCE32_VARIANT) {
+ switch (radeon_encoder->encoder_id) {
+@@ -569,11 +577,11 @@ atombios_output_dig_encoder_setup(xf86OutputPtr output, DisplayModePtr mode)
+ else
+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
+
+- if (dp_link_clock_for_mode_clock(mode->Clock) == 27000)
++ if (dp_link_clock_for_mode_clock(clock) == 27000)
+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
+
+- disp_data.ucLaneNum = dp_lanes_for_mode_clock(mode->Clock);
+- } else if (mode->Clock > 165000) {
++ disp_data.ucLaneNum = dp_lanes_for_mode_clock(clock);
++ } else if (clock > 165000) {
+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
+ disp_data.ucLaneNum = 8;
+ } else {
+@@ -605,10 +613,9 @@ union dig_transmitter_control {
+ };
+
+ static int
+-atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode)
++atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action)
+ {
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+- RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
+ union dig_transmitter_control disp_data;
+@@ -616,6 +623,8 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode)
+ unsigned char *space;
+ int index = 0, num = 0;
+ int major, minor;
++ int clock = radeon_output->pixel_clock;
++ int dig_block = radeon_output->dig_block;
+
+ if (radeon_encoder == NULL)
+ return ATOM_NOT_IMPLEMENTED;
+@@ -641,20 +650,20 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode)
+
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+- disp_data.v1.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE;
++ disp_data.v1.ucAction = action;
+
+ if (IS_DCE32_VARIANT) {
+ if (radeon_output->MonType == MT_DP) {
+ disp_data.v2.usPixelClock =
+- cpu_to_le16(dp_link_clock_for_mode_clock(mode->Clock));
++ cpu_to_le16(dp_link_clock_for_mode_clock(clock));
+ disp_data.v2.acConfig.fDPConnector = 1;
+- } else if (mode->Clock > 165000) {
+- disp_data.v2.usPixelClock = cpu_to_le16((mode->Clock * 10 * 2) / 100);
++ } else if (clock > 165000) {
++ disp_data.v2.usPixelClock = cpu_to_le16((clock * 10 * 2) / 100);
+ disp_data.v2.acConfig.fDualLinkConnector = 1;
+ } else {
+- disp_data.v2.usPixelClock = cpu_to_le16((mode->Clock * 10 * 4) / 100);
++ disp_data.v2.usPixelClock = cpu_to_le16((clock * 10 * 4) / 100);
+ }
+- if (radeon_crtc->crtc_id)
++ if (dig_block)
+ disp_data.v2.acConfig.ucEncoderSel = 1;
+
+ switch (radeon_encoder->encoder_id) {
+@@ -684,9 +693,9 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode)
+
+ if (radeon_output->MonType == MT_DP)
+ disp_data.v1.usPixelClock =
+- cpu_to_le16(dp_link_clock_for_mode_clock(mode->Clock));
++ cpu_to_le16(dp_link_clock_for_mode_clock(clock));
+ else
+- disp_data.v1.usPixelClock = cpu_to_le16((mode->Clock) / 10);
++ disp_data.v1.usPixelClock = cpu_to_le16((clock) / 10);
+
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+@@ -704,7 +713,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode)
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
+ if (info->IsIGP) {
+- if (mode->Clock > 165000) {
++ if (clock > 165000) {
+ disp_data.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
+ ATOM_TRANSMITTER_CONFIG_LINKA_B);
+ /* guess */
+@@ -724,7 +733,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode)
+ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
+ }
+ } else {
+- if (mode->Clock > 165000)
++ if (clock > 165000)
+ disp_data.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
+ ATOM_TRANSMITTER_CONFIG_LINKA_B |
+ ATOM_TRANSMITTER_CONFIG_LANE_0_7);
+@@ -741,7 +750,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode)
+ case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+ disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
+- if (mode->Clock > 165000)
++ if (clock > 165000)
+ disp_data.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
+ ATOM_TRANSMITTER_CONFIG_LINKA_B |
+ ATOM_TRANSMITTER_CONFIG_LANE_0_7);
+@@ -767,7 +776,6 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode)
+ }
+ }
+ }
+- radeon_output->transmitter_config = disp_data.v1.ucConfig;
+
+ data.exec.index = index;
+ data.exec.dataSpace = (void *)&space;
+@@ -1125,7 +1133,7 @@ atombios_output_overscan_setup(xf86OutputPtr output, DisplayModePtr mode, Displa
+ }
+
+ static int
+-atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode)
++atombios_output_scaler_setup(xf86OutputPtr output)
+ {
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+@@ -1213,63 +1221,6 @@ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode)
+
+ }
+
+-static int
+-atombios_dig_dpms(xf86OutputPtr output, int mode)
+-{
+- RADEONOutputPrivatePtr radeon_output = output->driver_private;
+- RADEONInfoPtr info = RADEONPTR(output->scrn);
+- radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
+- DIG_TRANSMITTER_CONTROL_PS_ALLOCATION disp_data;
+- AtomBiosArgRec data;
+- unsigned char *space;
+-
+- if (radeon_encoder == NULL)
+- return ATOM_NOT_IMPLEMENTED;
+-
+- memset(&disp_data, 0, sizeof(disp_data));
+-
+- switch (mode) {
+- case DPMSModeOn:
+- disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT;
+- break;
+- case DPMSModeStandby:
+- case DPMSModeSuspend:
+- case DPMSModeOff:
+- disp_data.ucAction = ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT;
+- break;
+- }
+-
+- disp_data.ucConfig = radeon_output->transmitter_config;
+-
+- if (IS_DCE32_VARIANT)
+- data.exec.index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
+- else {
+- switch (radeon_encoder->encoder_id) {
+- case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+- data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
+- break;
+- case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+- case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+- data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
+- break;
+- }
+- }
+- data.exec.dataSpace = (void *)&space;
+- data.exec.pspace = &disp_data;
+-
+- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+- ErrorF("Output DIG dpms success\n");
+- return ATOM_SUCCESS;
+- }
+-
+- ErrorF("Output DIG dpms failed\n");
+- return ATOM_NOT_IMPLEMENTED;
+-
+-}
+-
+ void
+ atombios_output_dpms(xf86OutputPtr output, int mode)
+ {
+@@ -1334,7 +1285,7 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
+ case DPMSModeOn:
+ radeon_encoder->devices |= radeon_output->active_device;
+ if (is_dig)
+- (void)atombios_dig_dpms(output, mode);
++ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT);
+ else {
+ disp_data.ucAction = ATOM_ENABLE;
+ data.exec.index = index;
+@@ -1355,7 +1306,7 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
+ radeon_encoder->devices &= ~(radeon_output->active_device);
+ if (!radeon_encoder->devices) {
+ if (is_dig)
+- (void)atombios_dig_dpms(output, mode);
++ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT);
+ else {
+ disp_data.ucAction = ATOM_DISABLE;
+ data.exec.index = index;
+@@ -1406,8 +1357,12 @@ atombios_set_output_crtc_source(xf86OutputPtr output)
default:
if (IS_AVIVO_VARIANT)
crtc_src_param.ucCRTC = radeon_crtc->crtc_id;
@@ -45,11 +527,98 @@
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+@@ -1559,13 +1514,16 @@ atombios_output_mode_set(xf86OutputPtr output,
+ DisplayModePtr adjusted_mode)
+ {
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
++ RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private;
+ radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ if (radeon_encoder == NULL)
+ return;
+
++ radeon_output->pixel_clock = adjusted_mode->Clock;
++ radeon_output->dig_block = radeon_crtc->crtc_id;
+ atombios_output_overscan_setup(output, mode, adjusted_mode);
+- atombios_output_scaler_setup(output, adjusted_mode);
++ atombios_output_scaler_setup(output);
+ atombios_set_output_crtc_source(output);
+
+ if (IS_AVIVO_VARIANT) {
+@@ -1580,29 +1538,31 @@ atombios_output_mode_set(xf86OutputPtr output,
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+ case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+ case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+- atombios_output_digital_setup(output, adjusted_mode);
++ atombios_output_digital_setup(output, PANEL_ENCODER_ACTION_ENABLE);
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+- atombios_output_dig_encoder_setup(output, adjusted_mode);
+- atombios_output_dig_transmitter_setup(output, adjusted_mode);
++ atombios_output_dig_encoder_setup(output, ATOM_ENABLE);
++ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_INIT);
++ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_SETUP);
++ atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_ENABLE);
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DDI:
+- atombios_output_ddia_setup(output, adjusted_mode);
++ atombios_output_ddia_setup(output, ATOM_ENABLE);
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DVO1:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
+- atombios_external_tmds_setup(output, adjusted_mode);
++ atombios_external_tmds_setup(output, ATOM_ENABLE);
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DAC1:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+ case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+- atombios_output_dac_setup(output, adjusted_mode);
++ atombios_output_dac_setup(output, ATOM_ENABLE);
+ if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
+- atombios_output_tv_setup(output, adjusted_mode);
++ atombios_output_tv_setup(output, ATOM_ENABLE);
+ break;
+ }
+ atombios_apply_output_quirks(output, adjusted_mode);
+diff --git a/src/legacy_output.c b/src/legacy_output.c
+index 6223531..423a3e2 100644
+--- a/src/legacy_output.c
++++ b/src/legacy_output.c
+@@ -1589,6 +1589,7 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
+ if (radeon_encoder == NULL)
+ return;
+
++ radeon_output->pixel_clock = adjusted_mode->Clock;
+ if (radeon_crtc->crtc_id == 0) {
+ ErrorF("set RMX\n");
+ is_primary = TRUE;
+@@ -1614,7 +1615,7 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
+ unsigned char *RADEONMMIO = info->MMIO;
+ uint32_t fp2_gen_cntl;
+
+- atombios_external_tmds_setup(output, mode);
++ atombios_external_tmds_setup(output, ATOM_ENABLE);
+ fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL) & ~R200_FP2_SOURCE_SEL_MASK;
+ if (radeon_crtc->crtc_id == 1)
+ fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
-index 4d4e625..bff80ca 100644
+index 4d4e625..b361d9d 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
-@@ -430,3 +430,10 @@
+@@ -346,6 +346,8 @@
+ "0x9456","RV770_9456","RV770",,,,,,"ATI FirePro V8700 (FireGL)"
+ "0x945A","RV770_945A","RV770",1,,,,,"ATI Mobility RADEON HD 4870"
+ "0x945B","RV770_945B","RV770",1,,,,,"ATI Mobility RADEON M98"
++"0x9460","RV790_9460","RV770",,,,,,"ATI Radeon 4800 Series"
++"0x9462","RV790_9462","RV770",,,,,,"ATI Radeon 4800 Series"
+ "0x946A","RV770_946A","RV770",1,,,,,"ATI FirePro M7750"
+ "0x946B","RV770_946B","RV770",1,,,,,"ATI M98"
+ "0x947A","RV770_947A","RV770",1,,,,,"ATI M98"
+@@ -430,3 +432,10 @@
"0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
"0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics"
"0x9614","RS780_9614","RS780",,1,,,1,"ATI Radeon HD 3300 Graphics"
@@ -647,6 +1216,19 @@
(con_obj_id == CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
uint32_t slot_config, ct;
+diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h
+index efebc62..b9a5398 100644
+--- a/src/radeon_atombios.h
++++ b/src/radeon_atombios.h
+@@ -126,7 +126,7 @@ extern Bool
+ RADEONGetATOMTVInfo(xf86OutputPtr output);
+
+ extern int
+-atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode);
++atombios_external_tmds_setup(xf86OutputPtr output, int action);
+
+ extern void
+ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor);
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 6fc0cf4..9b5cb88 100644
--- a/src/radeon_bios.c
@@ -673,10 +1255,19 @@
if (info->sclk == 0) info->sclk = 200;
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
-index eb2df17..e36828c 100644
+index eb2df17..6321246 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
-@@ -349,4 +349,11 @@ RADEONCardInfo RADEONCards[] = {
+@@ -265,6 +265,8 @@ RADEONCardInfo RADEONCards[] = {
+ { 0x9456, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
+ { 0x945A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x945B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
++ { 0x9460, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
++ { 0x9462, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
+ { 0x946A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x946B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x947A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+@@ -349,4 +351,11 @@ RADEONCardInfo RADEONCards[] = {
{ 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
{ 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
{ 0x9614, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
@@ -689,10 +1280,19 @@
+ { 0x9714, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
-index 3c86ae6..caa497a 100644
+index 3c86ae6..631eda8 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
-@@ -349,5 +349,12 @@ static SymTabRec RADEONChipsets[] = {
+@@ -265,6 +265,8 @@ static SymTabRec RADEONChipsets[] = {
+ { PCI_CHIP_RV770_9456, "ATI FirePro V8700 (FireGL)" },
+ { PCI_CHIP_RV770_945A, "ATI Mobility RADEON HD 4870" },
+ { PCI_CHIP_RV770_945B, "ATI Mobility RADEON M98" },
++ { PCI_CHIP_RV790_9460, "ATI Radeon 4800 Series" },
++ { PCI_CHIP_RV790_9462, "ATI Radeon 4800 Series" },
+ { PCI_CHIP_RV770_946A, "ATI FirePro M7750" },
+ { PCI_CHIP_RV770_946B, "ATI M98" },
+ { PCI_CHIP_RV770_947A, "ATI M98" },
+@@ -349,5 +351,12 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" },
{ PCI_CHIP_RS780_9613, "ATI Radeon 3100 Graphics" },
{ PCI_CHIP_RS780_9614, "ATI Radeon HD 3300 Graphics" },
@@ -705,6 +1305,29 @@
+ { PCI_CHIP_RS880_9714, "ATI Radeon Graphics" },
{ -1, NULL }
};
+diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
+index cd0d55e..4b508ce 100644
+--- a/src/radeon_crtc.c
++++ b/src/radeon_crtc.c
+@@ -115,6 +115,9 @@ radeon_crtc_mode_prepare(xf86CrtcPtr crtc)
+ {
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
++ if (radeon_crtc->initialized)
++ radeon_crtc_dpms(crtc, DPMSModeOff);
++
+ if (radeon_crtc->enabled)
+ crtc->funcs->hide_cursor(crtc);
+ }
+@@ -283,6 +286,8 @@ radeon_crtc_mode_commit(xf86CrtcPtr crtc)
+ {
+ if (crtc->scrn->pScreen != NULL)
+ xf86_reload_cursors(crtc->scrn->pScreen);
++
++ radeon_crtc_dpms(crtc, DPMSModeOn);
+ }
+
+ void
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 5a15c70..8673f5e 100644
--- a/src/radeon_driver.c
@@ -834,10 +1457,82 @@
+
#endif
diff --git a/src/radeon_output.c b/src/radeon_output.c
-index 3931db4..719f9e8 100644
+index 3931db4..712ac5f 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
-@@ -1263,10 +1263,21 @@ radeon_create_resources(xf86OutputPtr output)
+@@ -110,7 +110,6 @@ extern void atombios_output_mode_set(xf86OutputPtr output,
+ DisplayModePtr adjusted_mode);
+ extern void atombios_output_dpms(xf86OutputPtr output, int mode);
+ extern RADEONMonitorType atombios_dac_detect(xf86OutputPtr output);
+-extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode);
+ extern AtomBiosResult
+ atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock);
+ static void
+@@ -521,32 +520,8 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
+ static void
+ radeon_mode_prepare(xf86OutputPtr output)
+ {
+- RADEONInfoPtr info = RADEONPTR(output->scrn);
+- xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn);
+- int o;
+-
+- for (o = 0; o < config->num_output; o++) {
+- xf86OutputPtr loop_output = config->output[o];
+- if (loop_output == output)
+- continue;
+- else if (loop_output->crtc) {
+- xf86CrtcPtr other_crtc = loop_output->crtc;
+- RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private;
+- if (other_crtc->enabled) {
+- if (other_radeon_crtc->initialized) {
+- radeon_crtc_dpms(other_crtc, DPMSModeOff);
+- if (IS_AVIVO_VARIANT || info->r4xx_atom)
+- atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 1);
+- radeon_dpms(loop_output, DPMSModeOff);
+- }
+- }
+- }
+- }
+-
+ radeon_bios_output_lock(output, TRUE);
+ radeon_dpms(output, DPMSModeOff);
+- radeon_crtc_dpms(output->crtc, DPMSModeOff);
+-
+ }
+
+ static void
+@@ -566,30 +541,7 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
+ static void
+ radeon_mode_commit(xf86OutputPtr output)
+ {
+- RADEONInfoPtr info = RADEONPTR(output->scrn);
+- xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn);
+- int o;
+-
+- for (o = 0; o < config->num_output; o++) {
+- xf86OutputPtr loop_output = config->output[o];
+- if (loop_output == output)
+- continue;
+- else if (loop_output->crtc) {
+- xf86CrtcPtr other_crtc = loop_output->crtc;
+- RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private;
+- if (other_crtc->enabled) {
+- if (other_radeon_crtc->initialized) {
+- radeon_crtc_dpms(other_crtc, DPMSModeOn);
+- if (IS_AVIVO_VARIANT || info->r4xx_atom)
+- atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 0);
+- radeon_dpms(loop_output, DPMSModeOn);
+- }
+- }
+- }
+- }
+-
+ radeon_dpms(output, DPMSModeOn);
+- radeon_crtc_dpms(output->crtc, DPMSModeOn);
+ radeon_bios_output_lock(output, FALSE);
+ }
+
+@@ -1263,10 +1215,21 @@ radeon_create_resources(xf86OutputPtr output)
"RRConfigureOutputProperty error, %d\n", err);
}
/* Set the current value of the property */
@@ -862,7 +1557,7 @@
err = RRChangeOutputProperty(output->randr_output, rmx_atom,
XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s,
FALSE, FALSE);
-@@ -1884,6 +1895,10 @@ void RADEONInitConnector(xf86OutputPtr output)
+@@ -1884,6 +1847,10 @@ void RADEONInitConnector(xf86OutputPtr output)
else
radeon_output->rmx_type = RMX_OFF;
@@ -873,7 +1568,7 @@
if (!IS_AVIVO_VARIANT) {
if (radeon_output->devices & (ATOM_DEVICE_CRT2_SUPPORT)) {
if (xf86ReturnOptValBool(info->Options, OPTION_TVDAC_LOAD_DETECT, FALSE))
-@@ -2067,12 +2082,12 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
+@@ -2067,12 +2034,12 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].load_detection = FALSE;
info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
info->BiosConnector[0].valid = TRUE;
@@ -890,7 +1585,7 @@
return FALSE;
if (!radeon_add_encoder(pScrn,
radeon_get_encoder_id_from_supported_device(pScrn,
-@@ -2098,12 +2113,12 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
+@@ -2098,12 +2065,12 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].load_detection = FALSE;
info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
info->BiosConnector[0].valid = TRUE;
@@ -907,11 +1602,37 @@
return FALSE;
if (!radeon_add_encoder(pScrn,
radeon_get_encoder_id_from_supported_device(pScrn,
+@@ -2502,11 +2469,16 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn)
+ static int
+ radeon_output_clones (ScrnInfoPtr pScrn, xf86OutputPtr output)
+ {
++ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (pScrn);
+ int o;
+ int index_mask = 0;
+
++ /* DIG routing gets problematic */
++ if (IS_DCE32_VARIANT)
++ return index_mask;
++
+ /* LVDS is too wacky */
+ if (radeon_output->devices & (ATOM_DEVICE_LCD_SUPPORT))
+ return index_mask;
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
-index 31b032a..b9368d7 100644
+index 31b032a..d61c57d 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
-@@ -349,5 +349,12 @@ PciChipsets RADEONPciChipsets[] = {
+@@ -265,6 +265,8 @@ PciChipsets RADEONPciChipsets[] = {
+ { PCI_CHIP_RV770_9456, PCI_CHIP_RV770_9456, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_945A, PCI_CHIP_RV770_945A, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_945B, PCI_CHIP_RV770_945B, RES_SHARED_VGA },
++ { PCI_CHIP_RV790_9460, PCI_CHIP_RV790_9460, RES_SHARED_VGA },
++ { PCI_CHIP_RV790_9462, PCI_CHIP_RV790_9462, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_946A, PCI_CHIP_RV770_946A, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_946B, PCI_CHIP_RV770_946B, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_947A, PCI_CHIP_RV770_947A, RES_SHARED_VGA },
+@@ -349,5 +351,12 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RS780_9612, PCI_CHIP_RS780_9612, RES_SHARED_VGA },
{ PCI_CHIP_RS780_9613, PCI_CHIP_RS780_9613, RES_SHARED_VGA },
{ PCI_CHIP_RS780_9614, PCI_CHIP_RS780_9614, RES_SHARED_VGA },
@@ -925,10 +1646,19 @@
{ -1, -1, RES_UNDEFINED }
};
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
-index b310ce8..3923371 100644
+index b310ce8..a06b4a6 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
-@@ -349,5 +349,12 @@ static const struct pci_id_match radeon_device_match[] = {
+@@ -265,6 +265,8 @@ static const struct pci_id_match radeon_device_match[] = {
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9456, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_945A, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_945B, 0 ),
++ ATI_DEVICE_MATCH( PCI_CHIP_RV790_9460, 0 ),
++ ATI_DEVICE_MATCH( PCI_CHIP_RV790_9462, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_946A, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_946B, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_947A, 0 ),
+@@ -349,5 +351,12 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9612, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9613, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9614, 0 ),
@@ -941,8 +1671,24 @@
+ ATI_DEVICE_MATCH( PCI_CHIP_RS880_9714, 0 ),
{ 0, 0, 0 }
};
+diff --git a/src/radeon_probe.h b/src/radeon_probe.h
+index a0c6b2c..6479972 100644
+--- a/src/radeon_probe.h
++++ b/src/radeon_probe.h
+@@ -271,8 +271,10 @@ typedef struct _RADEONOutputPrivateRec {
+ radeon_tvout_rec tvout;
+
+ /* dce 3.x dig block */
+- int transmitter_config;
+ int igp_lane_info;
++ int dig_block;
++
++ int pixel_clock;
+ } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
+
+ struct avivo_pll_state {
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
-index 0af8859..a130794 100644
+index 0af8859..d74a30a 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -274,6 +274,9 @@
@@ -984,7 +1730,21 @@
#define RADEON_TV_SYNC_CNTL 0x0808
# define RADEON_SYNC_OE (1 << 0)
# define RADEON_SYNC_OUT (1 << 1)
-@@ -4406,6 +4423,7 @@
+@@ -3610,6 +3627,13 @@
+ # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21)
+
+ #define AVIVO_D1GRPH_LUT_SEL 0x6108
++
++#define R600_D1GRPH_SWAP_CONTROL 0x610C
++# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
++# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
++# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
++# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
++
+ #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
+ #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
+ #define AVIVO_D1GRPH_PITCH 0x6120
+@@ -4406,6 +4430,7 @@
#define R300_TX_INVALTAGS 0x4100
#define R300_TX_FILTER0_0 0x4400
#define R300_TX_FILTER0_1 0x4404
@@ -992,7 +1752,7 @@
# define R300_TX_CLAMP_S(x) ((x) << 0)
# define R300_TX_CLAMP_T(x) ((x) << 3)
# define R300_TX_CLAMP_R(x) ((x) << 6)
-@@ -4424,8 +4442,10 @@
+@@ -4424,8 +4449,10 @@
# define R300_TX_ID_SHIFT 28
#define R300_TX_FILTER1_0 0x4440
#define R300_TX_FILTER1_1 0x4444
@@ -1003,7 +1763,7 @@
# define R300_TXWIDTH_SHIFT 0
# define R300_TXHEIGHT_SHIFT 11
# define R300_NUM_LEVELS_SHIFT 26
-@@ -4434,6 +4454,7 @@
+@@ -4434,6 +4461,7 @@
# define R300_TXPITCH_EN (1 << 31)
#define R300_TX_FORMAT1_0 0x44c0
#define R300_TX_FORMAT1_1 0x44c4
@@ -1011,7 +1771,7 @@
# define R300_TX_FORMAT_X8 0x0
# define R300_TX_FORMAT_X16 0x1
# define R300_TX_FORMAT_Y4X4 0x2
-@@ -4506,13 +4527,23 @@
+@@ -4506,13 +4534,23 @@
# define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP (2 << 22)
# define R300_TX_FORMAT_SWAP_YUV (1 << 24)
@@ -1035,7 +1795,7 @@
# define R300_ENDIAN_SWAP_16_BIT (1 << 0)
# define R300_ENDIAN_SWAP_32_BIT (2 << 0)
# define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0)
-@@ -4523,6 +4554,7 @@
+@@ -4523,6 +4561,7 @@
#define R300_TX_ENABLE 0x4104
# define R300_TEX_0_ENABLE (1 << 0)
# define R300_TEX_1_ENABLE (1 << 1)
radeon-modeset.patch:
Index: radeon-modeset.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon-modeset.patch,v
retrieving revision 1.42
retrieving revision 1.43
diff -u -r1.42 -r1.43
--- radeon-modeset.patch 1 Apr 2009 12:03:34 -0000 1.42
+++ radeon-modeset.patch 6 Apr 2009 05:38:09 -0000 1.43
@@ -1,8 +1,16 @@
diff --git a/configure.ac b/configure.ac
-index 660ea1f..4279b60 100644
+index 660ea1f..4ddec1c 100644
--- a/configure.ac
+++ b/configure.ac
-@@ -114,8 +114,19 @@ if test "$DRI" = yes; then
+@@ -31,6 +31,7 @@ AM_CONFIG_HEADER([config.h])
+ AC_CONFIG_AUX_DIR(.)
+
+ AM_INIT_AUTOMAKE([dist-bzip2])
++AC_SYS_LARGEFILE
+
+ AM_MAINTAINER_MODE
+
+@@ -114,8 +115,19 @@ if test "$DRI" = yes; then
if test "$have_damage_h" = yes; then
AC_DEFINE(DAMAGE,1,[Use Damage extension])
fi
@@ -1066,8 +1074,30 @@
+extern Bool drmmode_set_desired_modes(ScrnInfoPtr pScrn, drmmode_ptr drmmode);
+#endif
+#endif
+diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
+index 3dfe151..04b6457 100644
+--- a/src/r600_textured_videofuncs.c
++++ b/src/r600_textured_videofuncs.c
+@@ -215,7 +215,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+ switch(pPriv->id) {
+ case FOURCC_YV12:
+ case FOURCC_I420:
+- accel_state->src_mc_addr[0] = pPriv->src_offset;
++ accel_state->src_mc_addr[0] = pPriv->src_offset + info->fbLocation + pScrn->fbOffset;
+ accel_state->src_size[0] = accel_state->src_pitch[0] * pPriv->h;
+
+ /* flush texture cache */
+@@ -316,7 +316,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+ case FOURCC_UYVY:
+ case FOURCC_YUY2:
+ default:
+- accel_state->src_mc_addr[0] = pPriv->src_offset;
++ accel_state->src_mc_addr[0] = pPriv->src_offset + info->fbLocation + pScrn->fbOffset;
+ accel_state->src_size[0] = accel_state->src_pitch[0] * pPriv->h;
+
+ /* flush texture cache */
diff --git a/src/radeon.h b/src/radeon.h
-index d488429..09e15f4 100644
+index d488429..d1bca2e 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -46,6 +46,8 @@
@@ -1181,7 +1211,7 @@
#ifdef USE_EXA
Bool accelDFS;
#endif
-@@ -892,6 +928,45 @@ typedef struct {
+@@ -892,6 +928,43 @@ typedef struct {
Bool r4xx_atom;
@@ -1191,9 +1221,7 @@
+ Bool cs_used_depth;
+ Bool drm_mm; // the drm memory manager exists and is initialised
+ struct {
-+ uint64_t vram_start;
+ uint64_t vram_size;
-+ uint64_t gart_start;
+ uint64_t gart_size;
+
+ struct radeon_memory *bo_list[2];
@@ -1227,7 +1255,7 @@
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
-@@ -1147,6 +1222,24 @@ extern void
+@@ -1147,6 +1220,24 @@ extern void
radeon_legacy_free_memory(ScrnInfoPtr pScrn,
void *mem_struct);
@@ -1252,7 +1280,7 @@
#ifdef XF86DRI
# ifdef USE_XAA
/* radeon_accelfuncs.c */
-@@ -1165,7 +1258,9 @@ do { \
+@@ -1165,7 +1256,9 @@ do { \
#define RADEONCP_RELEASE(pScrn, info) \
do { \
@@ -1263,7 +1291,7 @@
RADEON_PURGE_CACHE(); \
RADEON_WAIT_UNTIL_IDLE(); \
RADEONCPReleaseIndirect(pScrn); \
-@@ -1200,7 +1295,7 @@ do { \
+@@ -1200,7 +1293,7 @@ do { \
#define RADEONCP_REFRESH(pScrn, info) \
do { \
@@ -1272,7 +1300,7 @@
if (info->cp->needCacheFlush) { \
RADEON_PURGE_CACHE(); \
RADEON_PURGE_ZCACHE(); \
-@@ -1227,6 +1322,13 @@ do { \
+@@ -1227,6 +1320,13 @@ do { \
#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0
#define BEGIN_RING(n) do { \
@@ -1286,7 +1314,7 @@
if (RADEON_VERBOSE) { \
xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
"BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\
-@@ -1239,13 +1341,6 @@ do { \
+@@ -1239,13 +1339,6 @@ do { \
} \
info->cp->dma_debug_func = __FILE__; \
info->cp->dma_debug_lineno = __LINE__; \
@@ -1300,7 +1328,7 @@
__expected = n; \
__head = (pointer)((char *)info->cp->indirectBuffer->address + \
info->cp->indirectBuffer->used); \
-@@ -1288,6 +1383,14 @@ do { \
+@@ -1288,6 +1381,14 @@ do { \
OUT_RING(val); \
} while (0)
@@ -1705,10 +1733,10 @@
+#endif
diff --git a/src/radeon_bufmgr_gem.c b/src/radeon_bufmgr_gem.c
new file mode 100644
-index 0000000..a2fd61a
+index 0000000..6005e51
--- /dev/null
+++ b/src/radeon_bufmgr_gem.c
-@@ -0,0 +1,668 @@
+@@ -0,0 +1,635 @@
+/**************************************************************************
+ *
+ * Copyright © 2007-2008 Red Hat Inc.
@@ -1818,7 +1846,7 @@
+ args.size = size;
+ args.alignment = alignment;
+ args.initial_domain = RADEON_GEM_DOMAIN_CPU;
-+ args.no_backing_store = 0;
++ args.flags = 0;
+
+ ret = drmCommandWriteRead(bufmgr_gem->fd, DRM_RADEON_GEM_CREATE, &args, sizeof(args));
+ gem_bo->gem_handle = args.handle;
@@ -1906,6 +1934,7 @@
+ dri_bo_gem *gem_bo = (dri_bo_gem *)bo;
+ struct drm_radeon_gem_mmap args;
+ int ret;
++ void *ptr;
+
+ if (gem_bo->map_count++ != 0)
+ return 0;
@@ -1915,8 +1944,13 @@
+ args.size = gem_bo->bo.size;
+
+ ret = drmCommandWriteRead(bufmgr_gem->fd, DRM_RADEON_GEM_MMAP, &args, sizeof(args));
-+ if (!ret)
-+ gem_bo->bo.virtual = (void *)(unsigned long)args.addr_ptr;
++ if (ret)
++ return ret;
++
++ ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, bufmgr_gem->fd, args.addr_ptr);
++ if (ptr == MAP_FAILED)
++ return -errno;
++ gem_bo->bo.virtual = ptr;
+
+ return ret;
+}
@@ -1943,7 +1977,7 @@
+void radeon_bufmgr_gem_wait_rendering(dri_bo *buf)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)buf->bufmgr;
-+ struct drm_radeon_gem_wait_rendering args;
++ struct drm_radeon_gem_wait_idle args;
+ struct drm_radeon_gem_set_domain sd_args;
+ dri_bo_gem *gem_bo = (dri_bo_gem *)buf;
+ int ret;
@@ -1964,7 +1998,7 @@
+ args.handle = gem_bo->gem_handle;
+
+ do {
-+ ret = drmCommandWriteRead(bufmgr_gem->fd, DRM_RADEON_GEM_WAIT_RENDERING,
++ ret = drmCommandWriteRead(bufmgr_gem->fd, DRM_RADEON_GEM_WAIT_IDLE,
+ &args, sizeof(args));
+ } while (ret == -EAGAIN);
+ }
@@ -2111,43 +2145,6 @@
+ *count_p = __count;
+}
+
-+static int radeon_gem_bufmgr_pin(dri_bo *bo, int domain)
-+{
-+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
-+ dri_bo_gem *gem_bo = (dri_bo_gem *)bo;
-+ struct drm_radeon_gem_pin pin;
-+ int ret;
-+
-+ if (domain == RADEON_GEM_DOMAIN_VRAM)
-+ gem_bo->in_vram = 1;
-+
-+ pin.pin_domain = domain;
-+ pin.handle = gem_bo->gem_handle;
-+ pin.alignment = 0;
-+
-+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_RADEON_GEM_PIN, &pin);
-+ if (ret != 0)
-+ return -1;
-+
-+ /* pinned buffers are considered touched */
-+ gem_bo->touched = 1;
-+ gem_bo->pinned = 1;
-+ return 0;
-+}
-+
-+static void radeon_gem_bufmgr_unpin(dri_bo *bo)
-+{
-+
-+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
-+ dri_bo_gem *gem_bo = (dri_bo_gem *)bo;
-+ struct drm_radeon_gem_unpin unpin;
-+
-+ unpin.handle = gem_bo->gem_handle;
-+ ioctl(bufmgr_gem->fd, DRM_IOCTL_RADEON_GEM_UNPIN, &unpin);
-+ gem_bo->pinned = 0;
-+}
-+
-+
+static uint32_t radeon_gem_bufmgr_get_handle(dri_bo *buf)
+{
+ dri_bo_gem *gem_bo = (dri_bo_gem *)buf;
@@ -2277,8 +2274,6 @@
+ bufmgr_gem->bufmgr.bo_map = dri_gem_bo_map;
+ bufmgr_gem->bufmgr.bo_unmap = dri_gem_bo_unmap;
+ bufmgr_gem->bufmgr.destroy = dri_bufmgr_gem_destroy;
-+ bufmgr_gem->bufmgr.pin = radeon_gem_bufmgr_pin;
-+ bufmgr_gem->bufmgr.unpin = radeon_gem_bufmgr_unpin;
+ //bufmgr_gem->bufmgr.bo_wait_rendering = radeon_bufmgr_gem_wait_rendering;
+ bufmgr_gem->radeon_bufmgr.emit_reloc = radeon_bufmgr_gem_emit_reloc;
+ bufmgr_gem->bufmgr.get_handle = radeon_gem_bufmgr_get_handle;
@@ -2601,7 +2596,7 @@
CURSOR_SWAPPING_START();
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
-index f6c6261..1699d8a 100644
+index f6c6261..64b5937 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -40,6 +40,8 @@
@@ -2656,7 +2651,7 @@
static void RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num);
#endif
#endif
-@@ -352,6 +371,133 @@ static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext,
+@@ -352,6 +371,111 @@ static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext,
#endif
}
@@ -2683,28 +2678,6 @@
+ return -1;
+}
+
-+static void radeon_update_sarea(ScrnInfoPtr pScrn, drm_radeon_sarea_t * sarea)
-+{
-+ RADEONInfoPtr info = RADEONPTR(pScrn);
-+ int cpp = info->CurrentLayout.pixel_bytes;
-+ sarea->front_handle = -1;
-+ sarea->back_handle = -1;
-+ sarea->depth_handle = -1;
-+
-+ if (info->drm_mm){
-+ /* get handles and use them */
-+ sarea->front_handle = radeon_name_buffer(pScrn, info->mm.front_buffer);
-+
-+ sarea->front_pitch = info->dri->frontPitch * cpp;
-+ sarea->back_pitch = info->dri->backPitch * cpp;
-+ sarea->depth_pitch = info->dri->depthPitch * cpp;
-+ ErrorF("front handle is %x\n", sarea->front_handle);
-+ sarea->back_handle = radeon_name_buffer(pScrn, info->mm.back_buffer);
-+ sarea->depth_handle = radeon_name_buffer(pScrn, info->mm.depth_buffer);
-+
-+ }
-+}
-+
+/* so we need to add a frontbuffer map no matter what */
+#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))
+#define ROUND_TO_PAGE(x) ROUND_TO((x), radeon_drm_page_size)
@@ -2790,7 +2763,7 @@
/* Called when the X server is woken up to allow the last client's
* context to be saved and the X server's context to be loaded. This is
* not necessary for the Radeon since the client detects when it's
-@@ -701,25 +847,35 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info)
+@@ -701,25 +825,35 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info)
info->dri->gartOffset = 0;
@@ -2845,7 +2818,7 @@
}
/* AGP Mode Quirk List - Certain hostbridge/gfx-card combos don't work with
-@@ -992,6 +1148,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -992,6 +1126,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[agp] ring handle = 0x%08x\n",
(unsigned int)info->dri->ringHandle);
@@ -2854,7 +2827,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
&info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n");
-@@ -1000,9 +1158,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1000,9 +1136,10 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring mapped at 0x%08lx\n",
(unsigned long)info->dri->ring);
@@ -2866,7 +2839,7 @@
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[agp] Could not add ring read ptr mapping\n");
return FALSE;
-@@ -1011,6 +1170,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1011,6 +1148,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[agp] ring read ptr handle = 0x%08x\n",
(unsigned int)info->dri->ringReadPtrHandle);
@@ -2875,7 +2848,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle, info->dri->ringReadMapSize,
&info->dri->ringReadPtr) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
-@@ -1020,6 +1181,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1020,6 +1159,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Ring read ptr mapped at 0x%08lx\n",
(unsigned long)info->dri->ringReadPtr);
@@ -2883,7 +2856,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
DRM_AGP, 0, &info->dri->bufHandle) < 0) {
-@@ -1097,6 +1259,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1097,6 +1237,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[pci] ring handle = 0x%08x\n",
(unsigned int)info->dri->ringHandle);
@@ -2891,7 +2864,7 @@
if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
&info->dri->ring) < 0) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n");
-@@ -1108,6 +1271,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1108,6 +1249,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring contents 0x%08lx\n",
*(unsigned long *)(pointer)info->dri->ring);
@@ -2899,7 +2872,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->ringReadOffset, info->dri->ringReadMapSize,
DRM_SCATTER_GATHER, flags, &info->dri->ringReadPtrHandle) < 0) {
-@@ -1119,8 +1283,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1119,8 +1261,10 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
"[pci] ring read ptr handle = 0x%08x\n",
(unsigned int)info->dri->ringReadPtrHandle);
@@ -2910,7 +2883,7 @@
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[pci] Could not map ring read ptr\n");
return FALSE;
-@@ -1131,6 +1297,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1131,6 +1275,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] Ring read ptr contents 0x%08lx\n",
*(unsigned long *)(pointer)info->dri->ringReadPtr);
@@ -2918,7 +2891,7 @@
if (drmAddMap(info->dri->drmFD, info->dri->bufStart, info->dri->bufMapSize,
DRM_SCATTER_GATHER, 0, &info->dri->bufHandle) < 0) {
-@@ -1183,6 +1350,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1183,6 +1328,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen)
*/
static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen)
{
@@ -2928,7 +2901,7 @@
/* Map registers */
info->dri->registerSize = info->MMIOSize;
if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize,
-@@ -1223,20 +1393,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1223,20 +1371,23 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
drmInfo.fb_bpp = info->CurrentLayout.pixel_code;
drmInfo.depth_bpp = (info->dri->depthBits - 8) * 2;
@@ -2966,7 +2939,7 @@
if (drmCommandWrite(info->dri->drmFD, DRM_RADEON_CP_INIT,
&drmInfo, sizeof(drm_radeon_init_t)) < 0)
return FALSE;
-@@ -1245,8 +1418,9 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+@@ -1245,8 +1396,9 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
* registers back to their default values, so we need to restore
* those engine register here.
*/
@@ -2978,7 +2951,7 @@
return TRUE;
}
-@@ -1444,12 +1618,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
+@@ -1444,12 +1596,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
/* Get DRM version & close DRM */
info->dri->pKernelDRMVersion = drmGetVersion(fd);
@@ -2992,7 +2965,7 @@
}
/* Now check if we qualify */
-@@ -1483,10 +1656,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
+@@ -1483,10 +1634,27 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn)
req_patch);
drmFreeVersion(info->dri->pKernelDRMVersion);
info->dri->pKernelDRMVersion = NULL;
@@ -3006,12 +2979,10 @@
+ if (!drmCommandWriteRead(fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
+ {
+ info->drm_mm = TRUE;
-+ info->mm.vram_start = mminfo.vram_start;
+ info->mm.vram_size = mminfo.vram_size;
-+ info->mm.gart_start = mminfo.vram_start;
+ info->mm.gart_size = mminfo.gart_size;
-+ ErrorF("initing %llx %llx %llx %llx\n", mminfo.gart_start,
-+ mminfo.gart_size, mminfo.vram_start, mminfo.vram_size);
++ ErrorF("initing %llx %llx %llx %llx\n",
++ mminfo.gart_size, mminfo.vram_size);
+ }
}
@@ -3023,7 +2994,7 @@
}
Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
-@@ -1495,6 +1687,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
+@@ -1495,6 +1663,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int value = 0;
@@ -3033,7 +3004,7 @@
if (!info->want_vblank_interrupts)
on = FALSE;
-@@ -1514,6 +1709,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
+@@ -1514,6 +1685,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
return TRUE;
}
@@ -3086,7 +3057,7 @@
/* Initialize the screen-specific data structures for the DRI and the
* Radeon. This is the main entry point to the device-specific
-@@ -1577,10 +1818,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1577,10 +1794,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4;
pDRIInfo->ddxDriverMinorVersion = 3;
pDRIInfo->ddxDriverPatchVersion = 0;
@@ -3113,7 +3084,7 @@
pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES;
pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES
< RADEON_MAX_DRAWABLES
-@@ -1633,9 +1886,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1633,9 +1862,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d;
pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d;
pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d;
@@ -3124,7 +3095,7 @@
pDRIInfo->ClipNotify = RADEONDRIClipNotify;
#endif
-@@ -1667,57 +1918,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+@@ -1667,57 +1894,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
pDRIInfo = NULL;
return FALSE;
}
@@ -3138,7 +3109,7 @@
- RADEONDRICloseScreen(pScreen);
- return FALSE;
- }
-
+-
- /* Initialize PCI */
- if ((info->cardType!=CARD_AGP) && !RADEONDRIPciInit(info, pScreen)) {
- xf86DrvMsg(pScreen->myNum, X_ERROR,
@@ -3146,12 +3117,7 @@
- RADEONDRICloseScreen(pScreen);
- return FALSE;
- }
-+ /* Now, nuke dri.c's dummy frontbuffer map setup if we did that. */
-+ if (pDRIInfo->frameBufferSize != 0 && info->drm_mm) {
-+ int tmp;
-+ drm_handle_t fb_handle;
-+ void *ptmp;
-
+-
- /* DRIScreenInit doesn't add all the
- * common mappings. Add additional
- * mappings here.
@@ -3160,13 +3126,18 @@
- RADEONDRICloseScreen(pScreen);
- return FALSE;
- }
--
+
- /* DRIScreenInit adds the frame buffer
- map, but we need it as well */
- {
- void *scratch_ptr;
- int scratch_int;
--
++ /* Now, nuke dri.c's dummy frontbuffer map setup if we did that. */
++ if (pDRIInfo->frameBufferSize != 0 && info->drm_mm) {
++ int tmp;
++ drm_handle_t fb_handle;
++ void *ptmp;
+
- DRIGetDeviceInfo(pScreen, &info->dri->fbHandle,
- &scratch_int, &scratch_int,
- &scratch_int, &scratch_int,
@@ -3229,7 +3200,7 @@
static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
-@@ -1759,17 +2013,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
+@@ -1759,17 +1989,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
return FALSE;
}
@@ -3259,7 +3230,7 @@
/* Initialize and start the CP if required */
RADEONDRICPInit(pScrn);
-@@ -1778,6 +2036,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
+@@ -1778,6 +2012,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen);
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
@@ -3270,7 +3241,7 @@
pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate;
pRADEONDRI->deviceID = info->Chipset;
-@@ -1935,6 +2197,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
+@@ -1935,6 +2173,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
drmUnmap(info->dri->buf, info->dri->bufMapSize);
info->dri->buf = NULL;
}
@@ -3279,7 +3250,7 @@
if (info->dri->ringReadPtr) {
drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize);
info->dri->ringReadPtr = NULL;
-@@ -1943,6 +2207,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
+@@ -1943,6 +2183,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen)
drmUnmap(info->dri->ring, info->dri->ringMapSize);
info->dri->ring = NULL;
}
@@ -3287,7 +3258,7 @@
if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) {
drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle);
drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle);
-@@ -2352,3 +2617,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
+@@ -2352,3 +2593,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value)
&radeonsetparam, sizeof(drm_radeon_setparam_t));
return ret;
}
@@ -4058,7 +4029,7 @@
+
+#endif
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
-index 8673f5e..8d04d92 100644
+index 8673f5e..1c9d5d9 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -67,7 +67,7 @@
@@ -4460,7 +4431,7 @@
if (!RADEONPreInitVisual(pScrn))
goto fail;
-@@ -2907,167 +2979,227 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -2907,167 +2979,225 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions));
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
@@ -4766,12 +4737,10 @@
+
+ if (!drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
+ {
-+ info->mm.vram_start = mminfo.vram_start;
+ info->mm.vram_size = mminfo.vram_visible;
-+ info->mm.gart_start = mminfo.gart_start;
+ info->mm.gart_size = mminfo.gart_size;
-+ ErrorF("initing %llx %llx %llx %llx %llx\n", mminfo.gart_start,
-+ mminfo.gart_size, mminfo.vram_start, mminfo.vram_size, mminfo.vram_visible);
++ ErrorF("initing gart:%llx vram: s:%llx v:%llx\n",
++ mminfo.gart_size, mminfo.vram_size, mminfo.vram_visible);
+ }
+ {
+ struct drm_radeon_getparam gp;
@@ -4817,7 +4786,7 @@
/* Get ScreenInit function */
if (!xf86LoadSubModule(pScrn, "fb")) return FALSE;
-@@ -3082,10 +3214,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
+@@ -3082,10 +3212,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
if (!RADEONPreInitXv(pScrn)) goto fail;
}
@@ -4834,7 +4803,7 @@
}
if (pScrn->modes == NULL) {
-@@ -3238,6 +3372,9 @@ static void RADEONBlockHandler(int i, pointer blockData,
+@@ -3238,6 +3370,9 @@ static void RADEONBlockHandler(int i, pointer blockData,
#ifdef USE_EXA
info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
@@ -4844,7 +4813,7 @@
#endif
}
-@@ -3326,7 +3463,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3326,7 +3461,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
int subPixelOrder = SubPixelUnknown;
char* s;
#endif
@@ -4853,7 +4822,7 @@
info->accelOn = FALSE;
#ifdef USE_XAA
-@@ -3346,58 +3483,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3346,58 +3481,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
"RADEONScreenInit %lx %ld\n",
pScrn->memPhysBase, pScrn->fbOffset);
#endif
@@ -4954,7 +4923,7 @@
/* Visual setup */
miClearVisualTypes();
if (!miSetVisualTypes(pScrn->depth,
-@@ -3431,19 +3571,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3431,19 +3569,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
hasDRI = info->directRenderingEnabled;
#endif /* XF86DRI */
@@ -4988,7 +4957,7 @@
}
}
-@@ -3480,7 +3622,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3480,7 +3620,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#ifdef XF86DRI
if (hasDRI) {
info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS,
@@ -5000,7 +4969,7 @@
/* Reserve approx. half of offscreen memory for local textures by
* default, can be overridden with Option "FBTexPercent".
-@@ -3506,7 +3651,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3506,7 +3649,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#endif
#if defined(XF86DRI) && defined(USE_XAA)
@@ -5009,7 +4978,7 @@
info->dri->textureSize = -1;
if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
&(info->dri->textureSize))) {
-@@ -3524,7 +3669,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3524,7 +3667,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
#endif
#ifdef USE_XAA
@@ -5018,7 +4987,7 @@
return FALSE;
#endif
-@@ -3545,7 +3690,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3545,7 +3688,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->CurrentLayout.pixel_bytes);
int maxy = info->FbMapSize / width_bytes;
@@ -5027,7 +4996,7 @@
xf86DrvMsg(scrnIndex, X_ERROR,
"Static buffer allocation failed. Disabling DRI.\n");
xf86DrvMsg(scrnIndex, X_ERROR,
-@@ -3555,19 +3700,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3555,19 +3698,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024);
info->directRenderingEnabled = FALSE;
} else {
@@ -5086,7 +5055,7 @@
#endif
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Initializing fb layer\n");
-@@ -3591,7 +3771,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3591,7 +3769,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (info->r600_shadow_fb == FALSE) {
/* Init fb layer */
@@ -5095,7 +5064,7 @@
pScrn->virtualX, pScrn->virtualY,
pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
pScrn->bitsPerPixel))
-@@ -3633,8 +3813,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3633,8 +3811,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* restore the memory map here otherwise we may get a hang when
* initializing the drm below
*/
@@ -5108,7 +5077,7 @@
/* Backing store setup */
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-@@ -3644,7 +3826,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3644,7 +3824,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
/* DRI finalisation */
#ifdef XF86DRI
@@ -5117,7 +5086,7 @@
info->dri->pKernelDRMVersion->version_minor >= 19)
{
if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0)
-@@ -3660,14 +3842,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3660,14 +3840,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (info->directRenderingEnabled) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"DRI Finishing init !\n");
@@ -5143,7 +5112,7 @@
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
-@@ -3763,10 +3955,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+@@ -3763,10 +3953,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
return FALSE;
}
}
@@ -5161,7 +5130,7 @@
/* Provide SaveScreen & wrap BlockHandler and CloseScreen */
/* Wrap CloseScreen */
-@@ -5336,7 +5534,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5336,7 +5532,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
#ifdef XF86DRI
Bool CPStarted = info->cp->CPStarted;
@@ -5170,7 +5139,7 @@
DRILock(pScrn->pScreen, 0);
RADEONCP_STOP(pScrn, info);
}
-@@ -5359,8 +5557,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5359,8 +5555,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
#endif
}
@@ -5183,7 +5152,7 @@
ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
-@@ -5372,16 +5572,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+@@ -5372,16 +5570,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
/* xf86SetRootClip would do, but can't access that here */
}
@@ -5211,7 +5180,7 @@
}
#endif
-@@ -5579,6 +5782,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
+@@ -5579,6 +5780,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
xf86OutputPtr output = config->output[config->compat_output];
xf86CrtcPtr crtc = output->crtc;
@@ -5223,7 +5192,7 @@
/* not handled */
if (IS_AVIVO_VARIANT)
return;
-@@ -5618,76 +5826,101 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -5618,76 +5824,100 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONEnterVT\n");
@@ -5301,7 +5270,6 @@
- if (IS_R300_VARIANT || IS_RV100_VARIANT)
- RADEONForceSomeClocks(pScrn);
+ if (info->drm_mm) {
-+ radeon_bind_all_memory(pScrn);
+ info->accel_state->XInited3D = FALSE;
+ info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
+ }
@@ -5375,7 +5343,7 @@
}
#endif
/* this will get XVideo going again, but only if XVideo was initialised
-@@ -5702,7 +5935,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
+@@ -5702,7 +5932,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
info->accel_state->XInited3D = FALSE;
#ifdef XF86DRI
@@ -5384,7 +5352,7 @@
if (info->ChipFamily >= CHIP_FAMILY_R600)
R600LoadShaders(pScrn);
RADEONCP_START(pScrn, info);
-@@ -5726,27 +5959,29 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5726,27 +5956,29 @@ void RADEONLeaveVT(int scrnIndex, int flags)
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONLeaveVT\n");
#ifdef XF86DRI
@@ -5430,7 +5398,7 @@
/* Make sure 3D clients will re-upload textures to video RAM */
if (info->dri->textureSize) {
-@@ -5762,6 +5997,11 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5762,6 +5994,11 @@ void RADEONLeaveVT(int scrnIndex, int flags)
i = list[i].next;
} while (i != 0);
}
@@ -5442,7 +5410,7 @@
}
#endif
-@@ -5788,10 +6028,18 @@ void RADEONLeaveVT(int scrnIndex, int flags)
+@@ -5788,10 +6025,17 @@ void RADEONLeaveVT(int scrnIndex, int flags)
xf86_hide_cursors (pScrn);
@@ -5450,7 +5418,6 @@
+ if (info->drm_mm) {
+ info->accel_state->XInited3D = FALSE;
+ info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
-+ radeon_unbind_all_memory(pScrn);
+ }
- for (i = 0; i < config->num_crtc; i++)
@@ -5464,7 +5431,7 @@
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Ok, leaving now...\n");
-@@ -5845,7 +6093,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
+@@ -5845,7 +6089,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
#endif /* USE_XAA */
if (pScrn->vtSema) {
@@ -5474,13 +5441,12 @@
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-@@ -5880,6 +6129,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
+@@ -5880,6 +6125,11 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
info->DGAModes = NULL;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Unmapping memory\n");
+
+ if (info->drm_mm) {
-+ radeon_unbind_all_memory(pScrn);
+ radeon_free_all_memory(pScrn);
+ }
+
@@ -5488,71 +5454,55 @@
pScrn->vtSema = FALSE;
diff --git a/src/radeon_drm.h b/src/radeon_drm.h
-index 54bc234..06fbad3 100644
+index 54bc234..843cfe8 100644
--- a/src/radeon_drm.h
+++ b/src/radeon_drm.h
-@@ -303,7 +303,6 @@ typedef union {
+@@ -303,7 +303,8 @@ typedef union {
#define RADEON_INDEX_PRIM_OFFSET 20
#define RADEON_SCRATCH_REG_OFFSET 32
-#define R600_SCRATCH_REG_OFFSET 256
++
++#define R600_SCRATCH_REG_OFFSET 256
#define RADEON_NR_SAREA_CLIPRECTS 12
-@@ -454,6 +453,15 @@ typedef struct {
- int pfCurrentPage; /* which buffer is being displayed? */
- int crtc2_base; /* CRTC2 frame offset */
- int tiling_enabled; /* set by drm, read by 2d + 3d clients */
-+
-+ unsigned int last_fence;
-+
-+ uint32_t front_handle;
-+ uint32_t back_handle;
-+ uint32_t depth_handle;
-+ uint32_t front_pitch;
-+ uint32_t back_pitch;
-+ uint32_t depth_pitch;
- } drm_radeon_sarea_t;
-
- /* WARNING: If you change any of these defines, make sure to change the
-@@ -494,6 +502,18 @@ typedef struct {
+@@ -493,6 +494,16 @@ typedef struct {
+ #define DRM_RADEON_SETPARAM 0x19
#define DRM_RADEON_SURF_ALLOC 0x1a
#define DRM_RADEON_SURF_FREE 0x1b
++/* KMS ioctl */
++#define DRM_RADEON_GEM_INFO 0x1c
++#define DRM_RADEON_GEM_CREATE 0x1d
++#define DRM_RADEON_GEM_MMAP 0x1e
++#define DRM_RADEON_GEM_PREAD 0x21
++#define DRM_RADEON_GEM_PWRITE 0x22
++#define DRM_RADEON_GEM_SET_DOMAIN 0x23
++#define DRM_RADEON_GEM_WAIT_IDLE 0x24
++#define DRM_RADEON_CS 0x26
++#define DRM_RADEON_INFO 0x27
-+#define DRM_RADEON_GEM_INFO 0x1c
-+#define DRM_RADEON_GEM_CREATE 0x1d
-+#define DRM_RADEON_GEM_MMAP 0x1e
-+#define DRM_RADEON_GEM_PIN 0x1f
-+#define DRM_RADEON_GEM_UNPIN 0x20
-+#define DRM_RADEON_GEM_PREAD 0x21
-+#define DRM_RADEON_GEM_PWRITE 0x22
-+#define DRM_RADEON_GEM_SET_DOMAIN 0x23
-+#define DRM_RADEON_GEM_WAIT_RENDERING 0x24
-+
-+#define DRM_RADEON_CS 0x26
-+
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
- #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
-@@ -522,16 +542,28 @@ typedef struct {
+@@ -521,6 +532,17 @@ typedef struct {
+ #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
-
-+#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
-+#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
-+#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
-+#define DRM_IOCTL_RADEON_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PIN, struct drm_radeon_gem_pin)
-+#define DRM_IOCTL_RADEON_GEM_UNPIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_UNPIN, struct drm_radeon_gem_unpin)
-+#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
-+#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
-+#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
-+#define DRM_IOCTL_RADEON_GEM_WAIT_RENDERING DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_RENDERING, struct drm_radeon_gem_wait_rendering)
-+#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
-+
++/* KMS */
++#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
++#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
++#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
++#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
++#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
++#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
++#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
++#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
++#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
+
+
typedef struct drm_radeon_init {
enum {
- RADEON_INIT_CP = 0x01,
+@@ -528,10 +550,10 @@ typedef struct drm_radeon_init {
RADEON_CLEANUP_CP = 0x02,
RADEON_INIT_R200_CP = 0x03,
RADEON_INIT_R300_CP = 0x04,
@@ -5565,7 +5515,19 @@
int cp_mode;
int gart_size;
int ring_size;
-@@ -581,7 +613,7 @@ typedef struct drm_radeon_clear {
+@@ -543,9 +565,8 @@ typedef struct drm_radeon_init {
+ unsigned int depth_bpp;
+ unsigned int depth_offset, depth_pitch;
+
+- /* DEPRECATED commented out below to allow for -Werror build */
+- unsigned long fb_offset; /* deprecated, driver asks hardware */
+- unsigned long mmio_offset; /* deprecated, driver asks hardware */
++ unsigned long fb_offset;
++ unsigned long mmio_offset;
+ unsigned long ring_offset;
+ unsigned long ring_rptr_offset;
+ unsigned long buffers_offset;
+@@ -581,7 +602,7 @@ typedef struct drm_radeon_clear {
unsigned int clear_depth;
unsigned int color_mask;
unsigned int depth_mask; /* misnamed field: should be stencil */
@@ -5574,7 +5536,7 @@
} drm_radeon_clear_t;
typedef struct drm_radeon_vertex {
-@@ -607,9 +639,9 @@ typedef struct drm_radeon_vertex2 {
+@@ -607,9 +628,9 @@ typedef struct drm_radeon_vertex2 {
int idx; /* Index of vertex buffer */
int discard; /* Client finished with buffer? */
int nr_states;
@@ -5586,7 +5548,7 @@
} drm_radeon_vertex2_t;
/* v1.3 - obsoletes drm_radeon_vertex2
-@@ -624,15 +656,15 @@ typedef struct drm_radeon_vertex2 {
+@@ -624,15 +645,15 @@ typedef struct drm_radeon_vertex2 {
*/
typedef struct drm_radeon_cmd_buffer {
int bufsz;
@@ -5605,7 +5567,7 @@
} drm_radeon_tex_image_t;
typedef struct drm_radeon_texture {
-@@ -641,11 +673,11 @@ typedef struct drm_radeon_texture {
+@@ -641,11 +662,11 @@ typedef struct drm_radeon_texture {
int format;
int width; /* Texture image coordinates */
int height;
@@ -5619,7 +5581,7 @@
} drm_radeon_stipple_t;
typedef struct drm_radeon_indirect {
-@@ -655,9 +687,6 @@ typedef struct drm_radeon_indirect {
+@@ -655,9 +676,6 @@ typedef struct drm_radeon_indirect {
int discard;
} drm_radeon_indirect_t;
@@ -5629,11 +5591,11 @@
/* enum for card type parameters */
#define RADEON_CARD_PCI 0
#define RADEON_CARD_AGP 1
-@@ -683,10 +712,11 @@ typedef struct drm_radeon_indirect {
+@@ -683,10 +701,11 @@ typedef struct drm_radeon_indirect {
#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
-+#define RADEON_PARAM_KERNEL_MM 16
++#define RADEON_PARAM_DEVICE_ID 16
typedef struct drm_radeon_getparam {
int param;
@@ -5642,7 +5604,7 @@
} drm_radeon_getparam_t;
/* 1.6: Set up a memory manager for regions of shared memory:
-@@ -698,7 +728,7 @@ typedef struct drm_radeon_mem_alloc {
+@@ -698,7 +717,7 @@ typedef struct drm_radeon_mem_alloc {
int region;
int alignment;
int size;
@@ -5651,7 +5613,7 @@
} drm_radeon_mem_alloc_t;
typedef struct drm_radeon_mem_free {
-@@ -715,7 +745,7 @@ typedef struct drm_radeon_mem_init_heap {
+@@ -715,7 +734,7 @@ typedef struct drm_radeon_mem_init_heap {
/* 1.6: Userspace can request & wait on irq's:
*/
typedef struct drm_radeon_irq_emit {
@@ -5660,7 +5622,7 @@
} drm_radeon_irq_emit_t;
typedef struct drm_radeon_irq_wait {
-@@ -734,10 +764,10 @@ typedef struct drm_radeon_setparam {
+@@ -734,7 +753,6 @@ typedef struct drm_radeon_setparam {
#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
@@ -5668,69 +5630,55 @@
#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
-+#define RADEON_SETPARAM_MM_INIT 7 /* DDX wants memory manager but has no modesetting */
- /* 1.14: Clients can allocate/free a surface
- */
- typedef struct drm_radeon_surface_alloc {
-@@ -753,4 +783,107 @@ typedef struct drm_radeon_surface_free {
+@@ -753,4 +771,112 @@ typedef struct drm_radeon_surface_free {
#define DRM_RADEON_VBLANK_CRTC1 1
#define DRM_RADEON_VBLANK_CRTC2 2
-+#define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain
-+#define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed
-+#define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain
++/*
++ * Kernel modesetting world below.
++ */
++#define RADEON_GEM_DOMAIN_CPU 0x1
++#define RADEON_GEM_DOMAIN_GTT 0x2
++#define RADEON_GEM_DOMAIN_VRAM 0x4
+
-+/* return to userspace start/size of gtt and vram apertures */
+struct drm_radeon_gem_info {
-+ uint64_t gart_start;
-+ uint64_t gart_size;
-+ uint64_t vram_start;
-+ uint64_t vram_size;
-+ uint64_t vram_visible;
++ uint64_t gart_size;
++ uint64_t vram_size;
++ uint64_t vram_visible;
+};
+
++#define RADEON_GEM_NO_BACKING_STORE 1
++
+struct drm_radeon_gem_create {
-+ uint64_t size;
-+ uint64_t alignment;
-+ uint32_t handle;
-+ uint32_t initial_domain; // to allow VRAM to be created
-+ uint32_t no_backing_store; // for VRAM objects - select whether they need backing store
-+ // pretty much front/back/depth don't need it - other things do
++ uint64_t size;
++ uint64_t alignment;
++ uint32_t handle;
++ uint32_t initial_domain;
++ uint32_t flags;
+};
+
+struct drm_radeon_gem_mmap {
-+ uint32_t handle;
-+ uint32_t pad;
-+ uint64_t offset;
-+ uint64_t size;
-+ uint64_t addr_ptr;
++ uint32_t handle;
++ uint32_t pad;
++ uint64_t offset;
++ uint64_t size;
++ uint64_t addr_ptr;
+};
+
+struct drm_radeon_gem_set_domain {
-+ uint32_t handle;
-+ uint32_t read_domains;
-+ uint32_t write_domain;
-+};
-+
-+struct drm_radeon_gem_wait_rendering {
-+ uint32_t handle;
-+};
-+
-+struct drm_radeon_gem_pin {
-+ uint32_t handle;
-+ uint32_t pin_domain;
-+ uint64_t alignment;
-+ uint64_t offset;
++ uint32_t handle;
++ uint32_t read_domains;
++ uint32_t write_domain;
+};
+
-+struct drm_radeon_gem_unpin {
-+ uint32_t handle;
-+ uint32_t pad;
++struct drm_radeon_gem_wait_idle {
++ uint32_t handle;
++ uint32_t pad;
+};
+
+struct drm_radeon_gem_busy {
-+ uint32_t handle;
-+ uint32_t busy;
++ uint32_t handle;
++ uint32_t busy;
+};
+
+struct drm_radeon_gem_pread {
@@ -5742,7 +5690,8 @@
+ /** Length of data to read */
+ uint64_t size;
+ /** Pointer to write the data into. */
-+ uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
++ /* void *, but pointers are not 32/64 compatible */
++ uint64_t data_ptr;
+};
+
+struct drm_radeon_gem_pwrite {
@@ -5754,30 +5703,44 @@
+ /** Length of data to write */
+ uint64_t size;
+ /** Pointer to read the data from. */
-+ uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
++ /* void *, but pointers are not 32/64 compatible */
++ uint64_t data_ptr;
+};
+
-+
-+/* New interface which obsolete all previous interface.
-+ */
-+
-+
-+#define RADEON_CHUNK_ID_RELOCS 0x01
-+#define RADEON_CHUNK_ID_IB 0x02
++#define RADEON_CHUNK_ID_RELOCS 0x01
++#define RADEON_CHUNK_ID_IB 0x02
+
+struct drm_radeon_cs_chunk {
-+ uint32_t chunk_id;
-+ uint32_t length_dw;
-+ uint64_t chunk_data;
++ uint32_t chunk_id;
++ uint32_t length_dw;
++ uint64_t chunk_data;
++};
++
++struct drm_radeon_cs_reloc {
++ uint32_t handle;
++ uint32_t read_domains;
++ uint32_t write_domain;
++ uint32_t flags;
+};
+
+struct drm_radeon_cs {
-+ uint32_t num_chunks;
-+ uint32_t cs_id;
-+ uint64_t chunks; /* this points to uint64_t * which point to
-+ cs chunks */
++ uint32_t num_chunks;
++ uint32_t cs_id;
++ /* this points to uint64_t * which point to cs chunks */
++ uint64_t chunks;
++ /* updates to the limits after this CS ioctl */
++ uint64_t gart_limit;
++ uint64_t vram_limit;
+};
+
++#define RADEON_INFO_DEVICE_ID 0x00
++#define RADEON_INFO_NUM_GB_PIPES 0x01
++
++struct drm_radeon_info {
++ uint32_t request;
++ uint32_t pad;
++ uint64_t value;
++};
+
#endif
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
@@ -7579,10 +7542,10 @@
diff --git a/src/radeon_memory.c b/src/radeon_memory.c
new file mode 100644
-index 0000000..67868cc
+index 0000000..f4b6c28
--- /dev/null
+++ b/src/radeon_memory.c
-@@ -0,0 +1,386 @@
+@@ -0,0 +1,241 @@
+
+#include <errno.h>
+#include <sys/ioctl.h>
@@ -7591,75 +7554,6 @@
+#include "radeon_drm.h"
+#include "radeon_bufmgr_gem.h"
+
-+Bool
-+radeon_bind_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem)
-+{
-+ RADEONInfoPtr info = RADEONPTR(pScrn);
-+
-+ if (mem == NULL || mem->bound)
-+ return TRUE;
-+
-+ if (!info->drm_mm)
-+ return FALSE;
-+
-+ if (mem->kernel_bo_handle) {
-+ struct drm_radeon_gem_pin pin;
-+
-+ int ret;
-+
-+ if (mem->pool == RADEON_POOL_VRAM)
-+ pin.pin_domain = RADEON_GEM_DOMAIN_VRAM;
-+ else
-+ pin.pin_domain = RADEON_GEM_DOMAIN_GTT;
-+ pin.handle = mem->kernel_bo_handle;
-+ pin.alignment = mem->alignment;
-+
-+ ret = ioctl(info->dri->drmFD, DRM_IOCTL_RADEON_GEM_PIN, &pin);
-+ if (ret != 0) {
-+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-+ "Failed to pin %s: %s\n", mem->name, strerror(errno));
-+ return FALSE;
-+ }
-+
-+ mem->bound = TRUE;
-+ mem->offset = pin.offset;
-+ // ErrorF("pin returned 0x%llx\n", pin.offset);
-+ mem->end = mem->offset + mem->size;
-+ return TRUE;
-+ }
-+ return FALSE;
-+}
-+
-+static Bool
-+radeon_unbind_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem)
-+{
-+ RADEONInfoPtr info = RADEONPTR(pScrn);
-+ int ret;
-+
-+ if (mem == NULL || !mem->bound)
-+ return TRUE;
-+
-+ if (!info->drm_mm)
-+ return FALSE;
-+
-+ if (mem->kernel_bo_handle) {
-+ struct drm_radeon_gem_unpin unpin;
-+
-+ unpin.handle = mem->kernel_bo_handle;
-+ ret = ioctl(info->dri->drmFD, DRM_IOCTL_RADEON_GEM_UNPIN, &unpin);
-+
-+ if (ret == 0) {
-+ mem->bound = FALSE;
-+ mem->offset = -1;
-+ mem->end = -1;
-+ return TRUE;
-+ } else {
-+ return FALSE;
-+ }
-+ }
-+ return FALSE;
-+}
-+
+void radeon_free_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -7670,8 +7564,6 @@
+ if (mem->map)
+ radeon_unmap_memory(pScrn, mem);
+
-+ radeon_unbind_memory(pScrn, mem);
-+
+ if (mem->kernel_bo_handle) {
+ struct drm_gem_close close;
+
@@ -7715,14 +7607,13 @@
+ mem->size = size;
+ mem->pool = pool;
+ mem->next = mem->prev = NULL;
-+ mem->vt_bind = static_alloc;
+ args.size = size;
+ args.alignment = alignment;
+ if (pool == RADEON_POOL_VRAM)
+ args.initial_domain = RADEON_GEM_DOMAIN_VRAM;
+ else
+ args.initial_domain = RADEON_GEM_DOMAIN_GTT;
-+ args.no_backing_store = no_backing_store;
++ args.flags = no_backing_store ? RADEON_GEM_NO_BACKING_STORE : 0;
+
+ ret = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GEM_CREATE, &args, sizeof(args));
+ if (ret) {
@@ -7745,40 +7636,6 @@
+ return mem;
+}
+
-+Bool radeon_bind_all_memory(ScrnInfoPtr pScrn)
-+{
-+ RADEONInfoPtr info = RADEONPTR(pScrn);
-+ struct radeon_memory *mem;
-+ int i;
-+
-+ for (i = 0; i < 2; i++) {
-+ for (mem = info->mm.bo_list[i]; mem != NULL;
-+ mem = mem->next) {
-+ if (mem->vt_bind)
-+ if (!radeon_bind_memory(pScrn, mem)) {
-+ FatalError("Couldn't bind %s\n", mem->name);
-+ }
-+ }
-+ }
-+ return TRUE;
-+}
-+
-+Bool radeon_unbind_all_memory(ScrnInfoPtr pScrn)
-+{
-+ RADEONInfoPtr info = RADEONPTR(pScrn);
-+ struct radeon_memory *mem;
-+ int i;
-+
-+ for (i = 0; i < 2; i++) {
-+ for (mem = info->mm.bo_list[i]; mem != NULL;
-+ mem = mem->next) {
-+ if (mem->vt_bind)
-+ radeon_unbind_memory(pScrn, mem);
-+ }
-+ }
-+ return TRUE;
-+}
-+
+Bool radeon_free_all_memory(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -7801,16 +7658,22 @@
+ struct drm_radeon_gem_mmap args;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ int ret;
++ void *ptr;
+
+ assert(!mem->map);
+
-+
+ args.handle = mem->kernel_bo_handle;
+ args.size = mem->size;
+ ret = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GEM_MMAP, &args, sizeof(args));
+
-+ if (!ret)
-+ mem->map = (void *)(unsigned long)args.addr_ptr;
++ if (ret)
++ return ret;
++
++ ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, info->dri->drmFD, args.addr_ptr);
++ if (ptr == MAP_FAILED)
++ return -errno;
++
++ mem->map = ptr;
+ // ErrorF("Mapped %s size %ld at %x %p\n", mem->name, mem->size, mem->offset, mem->map);
+ return ret;
+}
@@ -7884,27 +7747,6 @@
+ /* keep area front front buffer - but don't allocate it yet */
+ total_size_bytes += screen_size;
+
-+ if (info->directRenderingEnabled && !info->dri2.enabled) {
-+ info->dri->backPitch = pScrn->displayWidth;
-+ info->mm.back_buffer = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, screen_size, 0, 1, "Back Buffer", 0);
-+ if (!info->mm.back_buffer) {
-+ return FALSE;
-+ }
-+ total_size_bytes += screen_size;
-+
-+ info->dri->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32);
-+ {
-+ int depthCpp = (info->dri->depthBits - 8) / 4;
-+ int depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->dri->depthPitch * depthCpp;
-+ depth_size = RADEON_ALIGN(depth_size, pagesize);
-+ info->mm.depth_buffer = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, depth_size, 0, 1, "Depth Buffer", 0);
-+ if (!info->mm.depth_buffer) {
-+ return FALSE;
-+ }
-+ total_size_bytes += depth_size;
-+ }
-+ }
-+
+ /* work out from the mm size what the exa / tex sizes need to be */
+ remain_size_bytes = info->mm.vram_size - total_size_bytes;
+
@@ -7927,38 +7769,14 @@
+
+ ErrorF("fb size is %dK %dK\n", fb_size_bytes / 1024, total_size_bytes / 1024);
+
-+ info->mm.front_buffer = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, fb_size_bytes, 0, 1, "Front Buffer + EXA", 1);
++ info->mm.front_buffer = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, fb_size_bytes, 0, 1, "Front Buffer", 1);
+ if (!info->mm.front_buffer) {
+ return FALSE;
+ }
+
-+ /* don't need to bind or map memory */
-+ if (!info->dri2.enabled) {
-+ if (radeon_map_memory(pScrn, info->mm.front_buffer)) {
-+ ErrorF("Failed to map front buffer memory\n");
-+ }
-+ info->dri->frontPitch = pScrn->displayWidth;
-+ }
-+
-+ if (info->directRenderingEnabled && info->dri->textureSize) {
-+ info->mm.texture_buffer = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, info->dri->textureSize, 0, 1, "Texture Buffer", 1);
-+ if (!info->mm.texture_buffer) {
-+ return FALSE;
-+ }
-+ radeon_bind_memory(pScrn, info->mm.texture_buffer);
-+ }
-+
-+ if (info->drm_mode_setting) {
-+ drmmode_set_fb(pScrn, &info->drmmode, pScrn->virtualX, RADEON_ALIGN(pScrn->virtualY, 16), stride, info->mm.front_buffer->kernel_bo_handle);
-+ }
++ drmmode_set_fb(pScrn, &info->drmmode, pScrn->virtualX, RADEON_ALIGN(pScrn->virtualY, 16), stride, info->mm.front_buffer->kernel_bo_handle);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK at 0x%08x\n", info->mm.front_buffer->size/1024, info->mm.front_buffer->offset);
-+ if (info->directRenderingEnabled && !info->dri2.enabled) {
-+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Back buffer size: %dK at 0x%08x\n", info->mm.back_buffer->size/1024, info->mm.back_buffer->offset);
-+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Depth buffer size: %dK at 0x%08x\n", info->mm.depth_buffer->size/1024, info->mm.depth_buffer->offset);
-+ }
-+ if (info->mm.texture_buffer)
-+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Texture size: %dK at 0x%08x\n", info->mm.texture_buffer->size/1024, info->mm.texture_buffer->offset);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Remaining VRAM size (used for pixmaps): %dK\n", remain_size_bytes/1024);
+
+ /* set the emit limit at 90% of VRAM */
@@ -7970,10 +7788,10 @@
+
+
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
-index a0c6b2c..30fee18 100644
+index a0c6b2c..b0fd23e 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
-@@ -146,6 +146,27 @@ typedef struct
+@@ -146,6 +146,26 @@ typedef struct
Bool hw_capable;
} RADEONI2CBusRec, *RADEONI2CBusPtr;
@@ -7995,13 +7813,12 @@
+ uint32_t alignment;
+ uint32_t kernel_bo_handle;
+ uint32_t kernel_name;
-+ Bool vt_bind;
+};
+
typedef struct _RADEONCrtcPrivateRec {
void *crtc_rotate_mem;
void *cursor_mem;
-@@ -159,6 +180,8 @@ typedef struct _RADEONCrtcPrivateRec {
+@@ -159,6 +179,8 @@ typedef struct _RADEONCrtcPrivateRec {
int can_tile;
Bool enabled;
Bool initialized;
@@ -8011,7 +7828,7 @@
typedef struct _radeon_encoder {
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
-index 79671c0..1ef8dc3 100644
+index 79671c0..7a70d2f 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -40,6 +40,7 @@
@@ -8094,6 +7911,30 @@
pPriv->src_pitch = dstPitch;
pPriv->planeu_offset = dstPitch * dst_height;
pPriv->planev_offset = pPriv->planeu_offset + dstPitch2 * ((dst_height + 1) >> 1);
+@@ -481,12 +502,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+ if (info->DMAForXv) {
+ if (id == FOURCC_YV12)
+ R600CopyPlanarHW(pScrn, buf, buf + s3offset, buf + s2offset,
+- pPriv->src_offset,
++ pPriv->src_offset + info->fbLocation + pScrn->fbOffset,
+ srcPitch, srcPitch2, pPriv->src_pitch,
+ width, height);
+ else
+ R600CopyPlanarHW(pScrn, buf, buf + s2offset, buf + s3offset,
+- pPriv->src_offset,
++ pPriv->src_offset + info->fbLocation + pScrn->fbOffset,
+ srcPitch, srcPitch2, pPriv->src_pitch,
+ width, height);
+ } else {
+@@ -548,7 +569,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
+ default:
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->DMAForXv)
+- R600CopyPackedHW(pScrn, buf, pPriv->src_offset,
++ R600CopyPackedHW(pScrn, buf, pPriv->src_offset + info->fbLocation + pScrn->fbOffset,
+ 2 * width, pPriv->src_pitch,
+ width, height);
+ else
@@ -566,9 +587,24 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
/* Upload bicubic filter tex */
Index: radeon.xinf
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon.xinf,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -r1.11 -r1.12
--- radeon.xinf 27 Feb 2009 03:57:32 -0000 1.11
+++ radeon.xinf 6 Apr 2009 05:38:10 -0000 1.12
@@ -263,6 +263,8 @@
alias pcivideo:v00001002d00009456sv*sd*bc*sc*i* radeon # ATI FirePro V8700 (FireGL)
alias pcivideo:v00001002d0000945Asv*sd*bc*sc*i* radeon # ATI Mobility RADEON HD 4870
alias pcivideo:v00001002d0000945Bsv*sd*bc*sc*i* radeon # ATI Mobility RADEON M98
+alias pcivideo:v00001002d00009460sv*sd*bc*sc*i* radeon # ATI Radeon 4800 Series
+alias pcivideo:v00001002d00009462sv*sd*bc*sc*i* radeon # ATI Radeon 4800 Series
alias pcivideo:v00001002d0000946Asv*sd*bc*sc*i* radeon # ATI FirePro M7750
alias pcivideo:v00001002d0000946Bsv*sd*bc*sc*i* radeon # ATI M98
alias pcivideo:v00001002d0000947Asv*sd*bc*sc*i* radeon # ATI M98
@@ -347,3 +349,10 @@
alias pcivideo:v00001002d00009612sv*sd*bc*sc*i* radeon # ATI Radeon HD 3200 Graphics
alias pcivideo:v00001002d00009613sv*sd*bc*sc*i* radeon # ATI Radeon 3100 Graphics
alias pcivideo:v00001002d00009614sv*sd*bc*sc*i* radeon # ATI Radeon HD 3300 Graphics
+alias pcivideo:v00001002d00009615sv*sd*bc*sc*i* radeon # ATI Radeon HD 3200 Graphics
+alias pcivideo:v00001002d00009616sv*sd*bc*sc*i* radeon # ATI Radeon 3000 Graphics
+alias pcivideo:v00001002d00009710sv*sd*bc*sc*i* radeon # ATI Radeon HD Graphics
+alias pcivideo:v00001002d00009711sv*sd*bc*sc*i* radeon # ATI Radeon Graphics
+alias pcivideo:v00001002d00009712sv*sd*bc*sc*i* radeon # ATI Mobility Radeon HD Graphics
+alias pcivideo:v00001002d00009713sv*sd*bc*sc*i* radeon # ATI Mobility Radeon Graphics
+alias pcivideo:v00001002d00009714sv*sd*bc*sc*i* radeon # ATI Radeon Graphics
Index: xorg-x11-drv-ati.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/xorg-x11-drv-ati.spec,v
retrieving revision 1.166
retrieving revision 1.167
diff -u -r1.166 -r1.167
--- xorg-x11-drv-ati.spec 3 Apr 2009 10:03:49 -0000 1.166
+++ xorg-x11-drv-ati.spec 6 Apr 2009 05:38:10 -0000 1.167
@@ -19,7 +19,6 @@
#Patch4: radeon-6.9.0-remove-limit-heuristics.patch
Patch5: radeon-6.9.0-panel-size-sanity.patch
Patch6: radeon-6.9.0-bgnr-enable.patch
-Patch7: radeon-r6xx-fix.patch
ExcludeArch: s390 s390x
@@ -34,7 +33,7 @@
Requires: xorg-x11-server-Xorg >= 1.4.99.1
Requires: libdrm >= 2.4.0-0.21
# new CS method needs newer kernel
-Requires: kernel >= 2.6.27.4-58
+Requires: kernel >= 2.6.29.1-51
%description
X.Org X11 ati video driver.
@@ -46,7 +45,6 @@
#patch4 -p1 -b .remove-limit-heuristics
#%patch5 -p1 -b .panel-size
%patch6 -p1 -b .bgnr
-%patch7 -p1 -b .r6xv
%build
autoreconf -iv
@@ -78,6 +76,10 @@
%{_mandir}/man4/radeon.4*
%changelog
+* Mon Apr 06 2009 Dave Airlie <airlied at redhat.com> 6.12.1-5
+- radeon-modeset.patch: break APIs;
+- radeon: move to latest git fixups
+
* Fri Apr 03 2009 Dave Airlie <airlied at redhat.com> 6.12.1-4
- fix up r600 xv harder
--- radeon-r6xx-fix.patch DELETED ---
- Previous message (by thread): rpms/kernel/F-11 drm-modesetting-radeon.patch, 1.68, 1.69 drm-next.patch, 1.12, 1.13 drm-nouveau.patch, 1.33, 1.34 kernel.spec, 1.1513, 1.1514 drm-radeon-reorder-bm.patch, 1.1, NONE
- Next message (by thread): rpms/xorg-x11-drv-ati/devel xorg-x11-drv-ati.spec,1.167,1.168
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