rpms/gcc/F-11 gcc44-power7-2.patch, 1.2, 1.3 gcc44-power7-3.patch, NONE, 1.1 gcc44-pr39856.patch, NONE, 1.1 gcc44-pr39903.patch, NONE, 1.1 .cvsignore, 1.272, 1.273 gcc.spec, 1.46, 1.47 sources, 1.275, 1.276 gcc44-cswtch.patch, 1.1, NONE gcc44-pr39543.patch, 1.3, NONE gcc44-pr39794.patch, 1.2, NONE gcc44-pr39867.patch, 1.1, NONE gcc44-rh459374-1.patch, 1.1, NONE gcc44-rh459374-2.patch, 1.1, NONE gcc44-rh459374-3.patch, 1.1, NONE
Jakub Jelinek
jakub at fedoraproject.org
Mon Apr 27 12:44:02 UTC 2009
Author: jakub
Update of /cvs/pkgs/rpms/gcc/F-11
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv1758
Modified Files:
.cvsignore gcc.spec sources
Added Files:
gcc44-power7-2.patch gcc44-power7-3.patch gcc44-pr39856.patch
gcc44-pr39903.patch
Removed Files:
gcc44-cswtch.patch gcc44-pr39543.patch gcc44-pr39794.patch
gcc44-pr39867.patch gcc44-rh459374-1.patch
gcc44-rh459374-2.patch gcc44-rh459374-3.patch
Log Message:
4.4.0-3
gcc44-power7-2.patch:
Index: gcc44-power7-2.patch
===================================================================
RCS file: gcc44-power7-2.patch
diff -N gcc44-power7-2.patch
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gcc44-power7-2.patch 27 Apr 2009 12:43:31 -0000 1.3
@@ -0,0 +1,328 @@
+2009-04-14 Michael Meissner <meissner at linux.vnet.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000_secondary_reload_inner): Handle
+ more possible combinations of addresses.
+
+ * config/rs6000/vector.md (vec_reload_and_plus_<mptrsize>): Allow
+ register+small constant in addition to register+register, and
+ restrict the insn to only match during reload and afterwards.
+ (vec_reload_and_reg_<mptrsize>): Allow for and of register
+ indirect to not generate insn not found message.
+
+ PR testsuite/39769
+ * gcc.dg/vmx/3a-04.c (test): Don't rely on floating point equality
+ for testing the results of estimate instructions.
+ * gcc.dg/vmx/3a-04m.c (test): Ditto.
+ * gcc.dg/vmx/3a-05.c (test): Ditto.
+
+--- gcc/testsuite/gcc.dg/vmx/3a-05.c (revision 146069)
++++ gcc/testsuite/gcc.dg/vmx/3a-05.c (revision 146118)
+@@ -14,9 +14,13 @@ f(vector float a, vector float b, vector
+
+ static void test()
+ {
+- check(vec_all_eq(f(((vector float){2,3,5,7}),
++ check(vec_all_gt(f(((vector float){2,3,5,7}),
+ ((vector float){11,13,17,19}),
+ ((vector float){23,29,31,37})),
+- ((vector float){16.9092026, 18.7693329, -2.8233242, -92.9472198})),
+- "f");
++ ((vector float){16.90, 18.76, -2.83, -92.95}))
++ && vec_all_lt(f(((vector float){2,3,5,7}),
++ ((vector float){11,13,17,19}),
++ ((vector float){23,29,31,37})),
++ ((vector float){16.91, 18.77, -2.82, -92.94})),
++ "f");
+ }
+--- gcc/testsuite/gcc.dg/vmx/3a-04m.c (revision 146069)
++++ gcc/testsuite/gcc.dg/vmx/3a-04m.c (revision 146118)
+@@ -10,9 +10,13 @@ f(vector float a, vector float b, vector
+
+ static void test()
+ {
+- check(vec_all_eq(f(((vector float){2,3,5,7}),
++ check(vec_all_gt(f(((vector float){2,3,5,7}),
+ ((vector float){11,13,17,19}),
+ ((vector float){23,29,31,37})),
+- ((vector float){23.1818085, 29.2307587, 32.2940826, 128.368393})),
++ ((vector float){23.18, 29.23, 32.29, 128.36}))
++ && vec_all_lt(f(((vector float){2,3,5,7}),
++ ((vector float){11,13,17,19}),
++ ((vector float){23,29,31,37})),
++ ((vector float){23.19, 29.24, 32.30, 128.37})),
+ "f");
+ }
+--- gcc/testsuite/gcc.dg/vmx/3a-04.c (revision 146069)
++++ gcc/testsuite/gcc.dg/vmx/3a-04.c (revision 146118)
+@@ -10,9 +10,13 @@ f(vector float a, vector float b, vector
+
+ static void test()
+ {
+- check(vec_all_eq(f(((vector float){2,3,5,7}),
++ check(vec_all_gt(f(((vector float){2,3,5,7}),
+ ((vector float){11,13,17,19}),
+ ((vector float){23,29,31,37})),
+- ((vector float){23.1818085, 29.2307587, 32.2940826, 128.368393})),
++ ((vector float){23.18, 29.23, 32.29, 128.36}))
++ && vec_all_lt(f(((vector float){2,3,5,7}),
++ ((vector float){11,13,17,19}),
++ ((vector float){23,29,31,37})),
++ ((vector float){23.19, 29.24, 32.30, 128.37})),
+ "f");
+ }
+--- gcc/config/rs6000/vector.md (revision 146069)
++++ gcc/config/rs6000/vector.md (revision 146118)
+@@ -129,14 +129,15 @@ (define_expand "reload_<VEC_R:mode>_<P:m
+ })
+
+ ;; Reload sometimes tries to move the address to a GPR, and can generate
+-;; invalid RTL for addresses involving AND -16.
++;; invalid RTL for addresses involving AND -16. Allow addresses involving
++;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
+
+ (define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
+ [(set (match_operand:P 0 "gpc_reg_operand" "=b")
+ (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
+- (match_operand:P 2 "gpc_reg_operand" "r"))
++ (match_operand:P 2 "reg_or_cint_operand" "rI"))
+ (const_int -16)))]
+- "TARGET_ALTIVEC || TARGET_VSX"
++ "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+@@ -146,6 +147,21 @@ (define_insn_and_split "*vec_reload_and_
+ (and:P (match_dup 0)
+ (const_int -16)))
+ (clobber:CC (scratch:CC))])])
++
++;; The normal ANDSI3/ANDDI3 won't match if reload decides to move an AND -16
++;; address to a register because there is no clobber of a (scratch), so we add
++;; it here.
++(define_insn_and_split "*vec_reload_and_reg_<mptrsize>"
++ [(set (match_operand:P 0 "gpc_reg_operand" "=b")
++ (and:P (match_operand:P 1 "gpc_reg_operand" "r")
++ (const_int -16)))]
++ "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)"
++ "#"
++ "&& reload_completed"
++ [(parallel [(set (match_dup 0)
++ (and:P (match_dup 1)
++ (const_int -16)))
++ (clobber:CC (scratch:CC))])])
+
+ ;; Generic floating point vector arithmetic support
+ (define_expand "add<mode>3"
+--- gcc/config/rs6000/rs6000.c (revision 146069)
++++ gcc/config/rs6000/rs6000.c (revision 146118)
+@@ -12574,6 +12574,11 @@ rs6000_secondary_reload_inner (rtx reg,
+ enum reg_class rclass;
+ rtx addr;
+ rtx and_op2 = NULL_RTX;
++ rtx addr_op1;
++ rtx addr_op2;
++ rtx scratch_or_premodify = scratch;
++ rtx and_rtx;
++ rtx cc_clobber;
+
+ if (TARGET_DEBUG_ADDR)
+ {
+@@ -12595,7 +12600,8 @@ rs6000_secondary_reload_inner (rtx reg,
+
+ switch (rclass)
+ {
+- /* Move reg+reg addresses into a scratch register for GPRs. */
++ /* GPRs can handle reg + small constant, all other addresses need to use
++ the scratch register. */
+ case GENERAL_REGS:
+ case BASE_REGS:
+ if (GET_CODE (addr) == AND)
+@@ -12603,70 +12609,152 @@ rs6000_secondary_reload_inner (rtx reg,
+ and_op2 = XEXP (addr, 1);
+ addr = XEXP (addr, 0);
+ }
++
++ if (GET_CODE (addr) == PRE_MODIFY)
++ {
++ scratch_or_premodify = XEXP (addr, 0);
++ gcc_assert (REG_P (scratch_or_premodify));
++ gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
++ addr = XEXP (addr, 1);
++ }
++
+ if (GET_CODE (addr) == PLUS
+ && (!rs6000_legitimate_offset_address_p (TImode, addr, true)
+ || and_op2 != NULL_RTX))
+ {
+- if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
+- || GET_CODE (addr) == CONST_INT)
+- rs6000_emit_move (scratch, addr, GET_MODE (addr));
+- else
+- emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
+- addr = scratch;
++ addr_op1 = XEXP (addr, 0);
++ addr_op2 = XEXP (addr, 1);
++ gcc_assert (legitimate_indirect_address_p (addr_op1, true));
++
++ if (!REG_P (addr_op2)
++ && (GET_CODE (addr_op2) != CONST_INT
++ || !satisfies_constraint_I (addr_op2)))
++ {
++ rs6000_emit_move (scratch, addr_op2, Pmode);
++ addr_op2 = scratch;
++ }
++
++ emit_insn (gen_rtx_SET (VOIDmode,
++ scratch_or_premodify,
++ gen_rtx_PLUS (Pmode,
++ addr_op1,
++ addr_op2)));
++
++ addr = scratch_or_premodify;
++ scratch_or_premodify = scratch;
+ }
+- else if (GET_CODE (addr) == PRE_MODIFY
+- && REG_P (XEXP (addr, 0))
+- && GET_CODE (XEXP (addr, 1)) == PLUS)
++ else if (!legitimate_indirect_address_p (addr, true)
++ && !rs6000_legitimate_offset_address_p (TImode, addr, true))
+ {
+- emit_insn (gen_rtx_SET (VOIDmode, XEXP (addr, 0), XEXP (addr, 1)));
+- addr = XEXP (addr, 0);
++ rs6000_emit_move (scratch_or_premodify, addr, Pmode);
++ addr = scratch_or_premodify;
++ scratch_or_premodify = scratch;
+ }
+ break;
+
++ /* Float/Altivec registers can only handle reg+reg addressing. Move
++ other addresses into a scratch register. */
++ case FLOAT_REGS:
++ case VSX_REGS:
++ case ALTIVEC_REGS:
++
+ /* With float regs, we need to handle the AND ourselves, since we can't
+ use the Altivec instruction with an implicit AND -16. Allow scalar
+ loads to float registers to use reg+offset even if VSX. */
+- case FLOAT_REGS:
+- case VSX_REGS:
+- if (GET_CODE (addr) == AND)
++ if (GET_CODE (addr) == AND
++ && (rclass != ALTIVEC_REGS || GET_MODE_SIZE (mode) != 16))
+ {
+ and_op2 = XEXP (addr, 1);
+ addr = XEXP (addr, 0);
+ }
+- /* fall through */
+
+- /* Move reg+offset addresses into a scratch register. */
+- case ALTIVEC_REGS:
+- if (!legitimate_indirect_address_p (addr, true)
+- && !legitimate_indexed_address_p (addr, true)
+- && (GET_CODE (addr) != PRE_MODIFY
+- || !legitimate_indexed_address_p (XEXP (addr, 1), true))
+- && (rclass != FLOAT_REGS
+- || GET_MODE_SIZE (mode) != 8
++ /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
++ as the address later. */
++ if (GET_CODE (addr) == PRE_MODIFY
++ && (!VECTOR_MEM_VSX_P (mode)
+ || and_op2 != NULL_RTX
+- || !rs6000_legitimate_offset_address_p (mode, addr, true)))
++ || !legitimate_indexed_address_p (XEXP (addr, 1), true)))
+ {
+- if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
+- || GET_CODE (addr) == CONST_INT)
+- rs6000_emit_move (scratch, addr, GET_MODE (addr));
+- else
+- emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
+- addr = scratch;
++ scratch_or_premodify = XEXP (addr, 0);
++ gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,
++ true));
++ gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
++ addr = XEXP (addr, 1);
++ }
++
++ if (legitimate_indirect_address_p (addr, true) /* reg */
++ || legitimate_indexed_address_p (addr, true) /* reg+reg */
++ || GET_CODE (addr) == PRE_MODIFY /* VSX pre-modify */
++ || GET_CODE (addr) == AND /* Altivec memory */
++ || (rclass == FLOAT_REGS /* legacy float mem */
++ && GET_MODE_SIZE (mode) == 8
++ && and_op2 == NULL_RTX
++ && scratch_or_premodify == scratch
++ && rs6000_legitimate_offset_address_p (mode, addr, true)))
++ ;
++
++ else if (GET_CODE (addr) == PLUS)
++ {
++ addr_op1 = XEXP (addr, 0);
++ addr_op2 = XEXP (addr, 1);
++ gcc_assert (REG_P (addr_op1));
++
++ rs6000_emit_move (scratch, addr_op2, Pmode);
++ emit_insn (gen_rtx_SET (VOIDmode,
++ scratch_or_premodify,
++ gen_rtx_PLUS (Pmode,
++ addr_op1,
++ scratch)));
++ addr = scratch_or_premodify;
++ scratch_or_premodify = scratch;
+ }
++
++ else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
++ || GET_CODE (addr) == CONST_INT)
++ {
++ rs6000_emit_move (scratch_or_premodify, addr, Pmode);
++ addr = scratch_or_premodify;
++ scratch_or_premodify = scratch;
++ }
++
++ else
++ gcc_unreachable ();
++
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+- /* If the original address involved an AND -16 that is part of the Altivec
+- addresses, recreate the and now. */
++ /* If the original address involved a pre-modify that we couldn't use the VSX
++ memory instruction with update, and we haven't taken care of already,
++ store the address in the pre-modify register and use that as the
++ address. */
++ if (scratch_or_premodify != scratch && scratch_or_premodify != addr)
++ {
++ emit_insn (gen_rtx_SET (VOIDmode, scratch_or_premodify, addr));
++ addr = scratch_or_premodify;
++ }
++
++ /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
++ memory instruction, recreate the AND now, including the clobber which is
++ generated by the general ANDSI3/ANDDI3 patterns for the
++ andi. instruction. */
+ if (and_op2 != NULL_RTX)
+ {
+- rtx and_rtx = gen_rtx_SET (VOIDmode,
+- scratch,
+- gen_rtx_AND (Pmode, addr, and_op2));
+- rtx cc_clobber = gen_rtx_CLOBBER (CCmode, gen_rtx_SCRATCH (CCmode));
++ if (! legitimate_indirect_address_p (addr, true))
++ {
++ emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
++ addr = scratch;
++ }
++
++ and_rtx = gen_rtx_SET (VOIDmode,
++ scratch,
++ gen_rtx_AND (Pmode,
++ addr,
++ and_op2));
++
++ cc_clobber = gen_rtx_CLOBBER (CCmode, gen_rtx_SCRATCH (CCmode));
+ emit_insn (gen_rtx_PARALLEL (VOIDmode,
+ gen_rtvec (2, and_rtx, cc_clobber)));
+ addr = scratch;
gcc44-power7-3.patch:
--- NEW FILE gcc44-power7-3.patch ---
--- gcc/doc/extend.texi (revision 146119)
+++ gcc/doc/extend.texi (revision 146798)
@@ -7094,7 +7094,7 @@ instructions, but allow the compiler to
* MIPS Loongson Built-in Functions::
* Other MIPS Built-in Functions::
* picoChip Built-in Functions::
-* PowerPC AltiVec Built-in Functions::
+* PowerPC AltiVec/VSX Built-in Functions::
* SPARC VIS Built-in Functions::
* SPU Built-in Functions::
@end menu
@@ -9571,7 +9571,7 @@ GCC defines the preprocessor macro @code
when this function is available.
@end table
- at node PowerPC AltiVec Built-in Functions
+ at node PowerPC AltiVec/VSX Built-in Functions
@subsection PowerPC AltiVec Built-in Functions
GCC provides an interface for the PowerPC family of processors to access
@@ -9597,6 +9597,19 @@ vector bool int
vector float
@end smallexample
+If @option{-mvsx} is used the following additional vector types are
+implemented.
+
+ at smallexample
+vector unsigned long
+vector signed long
+vector double
+ at end smallexample
+
+The long types are only implemented for 64-bit code generation, and
+the long type is only used in the floating point/integer conversion
+instructions.
+
GCC's implementation of the high-level language interface available from
C and C++ code differs from Motorola's documentation in several ways.
--- gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c (revision 146798)
@@ -0,0 +1,212 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xxsel" } } */
+/* { dg-final { scan-assembler "vperm" } } */
+/* { dg-final { scan-assembler "xvrdpi" } } */
+/* { dg-final { scan-assembler "xvrdpic" } } */
+/* { dg-final { scan-assembler "xvrdpim" } } */
+/* { dg-final { scan-assembler "xvrdpip" } } */
+/* { dg-final { scan-assembler "xvrdpiz" } } */
+/* { dg-final { scan-assembler "xvrspi" } } */
+/* { dg-final { scan-assembler "xvrspic" } } */
+/* { dg-final { scan-assembler "xvrspim" } } */
+/* { dg-final { scan-assembler "xvrspip" } } */
+/* { dg-final { scan-assembler "xvrspiz" } } */
+/* { dg-final { scan-assembler "xsrdpi" } } */
+/* { dg-final { scan-assembler "xsrdpic" } } */
+/* { dg-final { scan-assembler "xsrdpim" } } */
+/* { dg-final { scan-assembler "xsrdpip" } } */
+/* { dg-final { scan-assembler "xsrdpiz" } } */
+/* { dg-final { scan-assembler "xsmaxdp" } } */
+/* { dg-final { scan-assembler "xsmindp" } } */
+/* { dg-final { scan-assembler "xxland" } } */
+/* { dg-final { scan-assembler "xxlandc" } } */
+/* { dg-final { scan-assembler "xxlnor" } } */
+/* { dg-final { scan-assembler "xxlor" } } */
+/* { dg-final { scan-assembler "xxlxor" } } */
+/* { dg-final { scan-assembler "xvcmpeqdp" } } */
+/* { dg-final { scan-assembler "xvcmpgtdp" } } */
+/* { dg-final { scan-assembler "xvcmpgedp" } } */
+/* { dg-final { scan-assembler "xvcmpeqsp" } } */
+/* { dg-final { scan-assembler "xvcmpgtsp" } } */
+/* { dg-final { scan-assembler "xvcmpgesp" } } */
+/* { dg-final { scan-assembler "xxsldwi" } } */
+/* { dg-final { scan-assembler-not "call" } } */
+
+extern __vector int si[][4];
+extern __vector short ss[][4];
+extern __vector signed char sc[][4];
+extern __vector float f[][4];
+extern __vector unsigned int ui[][4];
+extern __vector unsigned short us[][4];
+extern __vector unsigned char uc[][4];
+extern __vector __bool int bi[][4];
+extern __vector __bool short bs[][4];
+extern __vector __bool char bc[][4];
+extern __vector __pixel p[][4];
+#ifdef __VSX__
+extern __vector double d[][4];
+extern __vector long sl[][4];
+extern __vector unsigned long ul[][4];
+extern __vector __bool long bl[][4];
+#endif
+
+int do_sel(void)
+{
+ int i = 0;
+
+ si[i][0] = __builtin_vsx_xxsel_4si (si[i][1], si[i][2], si[i][3]); i++;
+ ss[i][0] = __builtin_vsx_xxsel_8hi (ss[i][1], ss[i][2], ss[i][3]); i++;
+ sc[i][0] = __builtin_vsx_xxsel_16qi (sc[i][1], sc[i][2], sc[i][3]); i++;
+ f[i][0] = __builtin_vsx_xxsel_4sf (f[i][1], f[i][2], f[i][3]); i++;
+ d[i][0] = __builtin_vsx_xxsel_2df (d[i][1], d[i][2], d[i][3]); i++;
+
+ si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], bi[i][3]); i++;
+ ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], bs[i][3]); i++;
+ sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], bc[i][3]); i++;
+ f[i][0] = __builtin_vsx_xxsel (f[i][1], f[i][2], bi[i][3]); i++;
+ d[i][0] = __builtin_vsx_xxsel (d[i][1], d[i][2], bl[i][3]); i++;
+
+ si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], ui[i][3]); i++;
+ ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], us[i][3]); i++;
+ sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], uc[i][3]); i++;
+ f[i][0] = __builtin_vsx_xxsel (f[i][1], f[i][2], ui[i][3]); i++;
+ d[i][0] = __builtin_vsx_xxsel (d[i][1], d[i][2], ul[i][3]); i++;
+
+ return i;
+}
+
+int do_perm(void)
+{
+ int i = 0;
+
+ si[i][0] = __builtin_vsx_vperm_4si (si[i][1], si[i][2], sc[i][3]); i++;
+ ss[i][0] = __builtin_vsx_vperm_8hi (ss[i][1], ss[i][2], sc[i][3]); i++;
+ sc[i][0] = __builtin_vsx_vperm_16qi (sc[i][1], sc[i][2], sc[i][3]); i++;
+ f[i][0] = __builtin_vsx_vperm_4sf (f[i][1], f[i][2], sc[i][3]); i++;
+ d[i][0] = __builtin_vsx_vperm_2df (d[i][1], d[i][2], sc[i][3]); i++;
+
+ si[i][0] = __builtin_vsx_vperm (si[i][1], si[i][2], uc[i][3]); i++;
+ ss[i][0] = __builtin_vsx_vperm (ss[i][1], ss[i][2], uc[i][3]); i++;
+ sc[i][0] = __builtin_vsx_vperm (sc[i][1], sc[i][2], uc[i][3]); i++;
+ f[i][0] = __builtin_vsx_vperm (f[i][1], f[i][2], uc[i][3]); i++;
+ d[i][0] = __builtin_vsx_vperm (d[i][1], d[i][2], uc[i][3]); i++;
+
+ return i;
+}
+
+int do_xxperm (void)
+{
+ int i = 0;
+
+ d[i][0] = __builtin_vsx_xxpermdi_2df (d[i][1], d[i][2], 0); i++;
+ d[i][0] = __builtin_vsx_xxpermdi (d[i][1], d[i][2], 1); i++;
+ return i;
+}
+
+double x, y;
+void do_concat (void)
+{
+ d[0][0] = __builtin_vsx_concat_2df (x, y);
+}
+
+void do_set (void)
+{
+ d[0][0] = __builtin_vsx_set_2df (d[0][1], x, 0);
+ d[1][0] = __builtin_vsx_set_2df (d[1][1], y, 1);
+}
+
+extern double z[][4];
+
+int do_math (void)
+{
+ int i = 0;
+
+ d[i][0] = __builtin_vsx_xvrdpi (d[i][1]); i++;
+ d[i][0] = __builtin_vsx_xvrdpic (d[i][1]); i++;
+ d[i][0] = __builtin_vsx_xvrdpim (d[i][1]); i++;
+ d[i][0] = __builtin_vsx_xvrdpip (d[i][1]); i++;
+ d[i][0] = __builtin_vsx_xvrdpiz (d[i][1]); i++;
+
+ f[i][0] = __builtin_vsx_xvrspi (f[i][1]); i++;
+ f[i][0] = __builtin_vsx_xvrspic (f[i][1]); i++;
+ f[i][0] = __builtin_vsx_xvrspim (f[i][1]); i++;
+ f[i][0] = __builtin_vsx_xvrspip (f[i][1]); i++;
+ f[i][0] = __builtin_vsx_xvrspiz (f[i][1]); i++;
+
+ z[i][0] = __builtin_vsx_xsrdpi (z[i][1]); i++;
+ z[i][0] = __builtin_vsx_xsrdpic (z[i][1]); i++;
+ z[i][0] = __builtin_vsx_xsrdpim (z[i][1]); i++;
+ z[i][0] = __builtin_vsx_xsrdpip (z[i][1]); i++;
+ z[i][0] = __builtin_vsx_xsrdpiz (z[i][1]); i++;
+ z[i][0] = __builtin_vsx_xsmaxdp (z[i][1], z[i][0]); i++;
+ z[i][0] = __builtin_vsx_xsmindp (z[i][1], z[i][0]); i++;
+ return i;
+}
+
+int do_cmp (void)
+{
+ int i = 0;
+
+ d[i][0] = __builtin_vsx_xvcmpeqdp (d[i][1], d[i][2]); i++;
+ d[i][0] = __builtin_vsx_xvcmpgtdp (d[i][1], d[i][2]); i++;
+ d[i][0] = __builtin_vsx_xvcmpgedp (d[i][1], d[i][2]); i++;
+
[...3124 lines suppressed...]
/* VSX overloaded builtins, add the overloaded functions not present in
Altivec. */
@@ -3395,7 +3411,13 @@ enum rs6000_builtins
VSX_BUILTIN_VEC_NMADD,
VSX_BUITLIN_VEC_NMSUB,
VSX_BUILTIN_VEC_DIV,
- VSX_BUILTIN_OVERLOADED_LAST = VSX_BUILTIN_VEC_DIV,
+ VSX_BUILTIN_VEC_XXMRGHW,
+ VSX_BUILTIN_VEC_XXMRGLW,
+ VSX_BUILTIN_VEC_XXPERMDI,
+ VSX_BUILTIN_VEC_XXSLDWI,
+ VSX_BUILTIN_VEC_XXSPLTD,
+ VSX_BUILTIN_VEC_XXSPLTW,
+ VSX_BUILTIN_OVERLOADED_LAST = VSX_BUILTIN_VEC_XXSPLTW,
/* Combined VSX/Altivec builtins. */
VECTOR_BUILTIN_FLOAT_V4SI_V4SF,
@@ -3425,13 +3447,16 @@ enum rs6000_builtin_type_index
RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V4SI,
+ RS6000_BTI_unsigned_V2DI,
RS6000_BTI_bool_char, /* __bool char */
RS6000_BTI_bool_short, /* __bool short */
RS6000_BTI_bool_int, /* __bool int */
+ RS6000_BTI_bool_long, /* __bool long */
RS6000_BTI_pixel, /* __pixel */
RS6000_BTI_bool_V16QI, /* __vector __bool char */
RS6000_BTI_bool_V8HI, /* __vector __bool short */
RS6000_BTI_bool_V4SI, /* __vector __bool int */
+ RS6000_BTI_bool_V2DI, /* __vector __bool long */
RS6000_BTI_pixel_V8HI, /* __vector __pixel */
RS6000_BTI_long, /* long_integer_type_node */
RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
@@ -3466,13 +3491,16 @@ enum rs6000_builtin_type_index
#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
+#define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
#define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
#define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
#define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
+#define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
#define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
#define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
#define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
#define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
+#define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
#define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
--- gcc/config/rs6000/altivec.md (revision 146119)
+++ gcc/config/rs6000/altivec.md (revision 146798)
@@ -166,12 +166,15 @@ (define_mode_iterator V [V4SI V8HI V16QI
;; otherwise handled by altivec (v2df, v2di, ti)
(define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI TI])
+;; Like VM, except don't do TImode
+(define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI])
+
(define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
;; Vector move instructions.
(define_insn "*altivec_mov<mode>"
- [(set (match_operand:V 0 "nonimmediate_operand" "=Z,v,v,*o,*r,*r,v,v")
- (match_operand:V 1 "input_operand" "v,Z,v,r,o,r,j,W"))]
+ [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*o,*r,*r,v,v")
+ (match_operand:VM2 1 "input_operand" "v,Z,v,r,o,r,j,W"))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
@@ -191,6 +194,31 @@ (define_insn "*altivec_mov<mode>"
}
[(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")])
+;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode
+;; is for unions. However for plain data movement, slightly favor the vector
+;; loads
+(define_insn "*altivec_movti"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,v,v,?o,?r,?r,v,v")
+ (match_operand:TI 1 "input_operand" "v,Z,v,r,o,r,j,W"))]
+ "VECTOR_MEM_ALTIVEC_P (TImode)
+ && (register_operand (operands[0], TImode)
+ || register_operand (operands[1], TImode))"
+{
+ switch (which_alternative)
+ {
+ case 0: return "stvx %1,%y0";
+ case 1: return "lvx %0,%y1";
+ case 2: return "vor %0,%1,%1";
+ case 3: return "#";
+ case 4: return "#";
+ case 5: return "#";
+ case 6: return "vxor %0,%0,%0";
+ case 7: return output_vec_const_move (operands);
+ default: gcc_unreachable ();
+ }
+}
+ [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")])
+
(define_split
[(set (match_operand:VM 0 "altivec_register_operand" "")
(match_operand:VM 1 "easy_vector_constant_add_self" ""))]
@@ -434,13 +462,13 @@ (define_insn "*altivec_gev4sf"
"vcmpgefp %0,%1,%2"
[(set_attr "type" "veccmp")])
-(define_insn "altivec_vsel<mode>"
+(define_insn "*altivec_vsel<mode>"
[(set (match_operand:VM 0 "altivec_register_operand" "=v")
(if_then_else:VM (ne (match_operand:VM 1 "altivec_register_operand" "v")
(const_int 0))
(match_operand:VM 2 "altivec_register_operand" "v")
(match_operand:VM 3 "altivec_register_operand" "v")))]
- "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
+ "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
"vsel %0,%3,%2,%1"
[(set_attr "type" "vecperm")])
@@ -780,7 +808,7 @@ (define_insn "altivec_vmrghw"
(const_int 3)
(const_int 1)]))
(const_int 5)))]
- "TARGET_ALTIVEC"
+ "VECTOR_MEM_ALTIVEC_P (V4SImode)"
"vmrghw %0,%1,%2"
[(set_attr "type" "vecperm")])
@@ -797,7 +825,7 @@ (define_insn "*altivec_vmrghsf"
(const_int 3)
(const_int 1)]))
(const_int 5)))]
- "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
+ "VECTOR_MEM_ALTIVEC_P (V4SFmode)"
"vmrghw %0,%1,%2"
[(set_attr "type" "vecperm")])
@@ -881,7 +909,7 @@ (define_insn "altivec_vmrglw"
(const_int 1)
(const_int 3)]))
(const_int 5)))]
- "TARGET_ALTIVEC"
+ "VECTOR_MEM_ALTIVEC_P (V4SImode)"
"vmrglw %0,%1,%2"
[(set_attr "type" "vecperm")])
@@ -899,7 +927,7 @@ (define_insn "*altivec_vmrglsf"
(const_int 1)
(const_int 3)]))
(const_int 5)))]
- "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
+ "VECTOR_MEM_ALTIVEC_P (V4SFmode)"
"vmrglw %0,%1,%2"
[(set_attr "type" "vecperm")])
--- gcc/config/rs6000/rs6000.md (revision 146119)
+++ gcc/config/rs6000/rs6000.md (revision 146798)
@@ -14667,7 +14667,11 @@ (define_insn "return"
[(set_attr "type" "jmpreg")])
(define_expand "indirect_jump"
- [(set (pc) (match_operand 0 "register_operand" ""))])
+ [(set (pc) (match_operand 0 "register_operand" ""))]
+ ""
+{
+ rs6000_set_indirect_jump ();
+})
(define_insn "*indirect_jump<mode>"
[(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
@@ -14682,14 +14686,14 @@ (define_expand "tablejump"
[(use (match_operand 0 "" ""))
(use (label_ref (match_operand 1 "" "")))]
""
- "
{
+ rs6000_set_indirect_jump ();
if (TARGET_32BIT)
emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
else
emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
DONE;
-}")
+})
(define_expand "tablejumpsi"
[(set (match_dup 3)
@@ -14749,6 +14753,11 @@ (define_expand "doloop_end"
/* Only use this on innermost loops. */
if (INTVAL (operands[3]) > 1)
FAIL;
+ /* Do not try to use decrement and count on code that has an indirect
+ jump or a table jump, because the ctr register is preferred over the
+ lr register. */
+ if (rs6000_has_indirect_jump_p ())
+ FAIL;
if (TARGET_64BIT)
{
if (GET_MODE (operands[0]) != DImode)
gcc44-pr39856.patch:
--- NEW FILE gcc44-pr39856.patch ---
2009-04-24 Vladimir Makarov <vmakarov at redhat.com>
PR target/39856
* reg-stack.c (subst_stack_regs_pat): Remove gcc_assert for note
for clobber.
--- gcc/reg-stack.c (revision 146648)
+++ gcc/reg-stack.c (working copy)
@@ -1371,21 +1371,23 @@ subst_stack_regs_pat (rtx insn, stack re
if (pat != PATTERN (insn))
{
- /* The fix_truncdi_1 pattern wants to be able to allocate
- its own scratch register. It does this by clobbering
- an fp reg so that it is assured of an empty reg-stack
- register. If the register is live, kill it now.
- Remove the DEAD/UNUSED note so we don't try to kill it
- later too. */
+ /* The fix_truncdi_1 pattern wants to be able to
+ allocate its own scratch register. It does this by
+ clobbering an fp reg so that it is assured of an
+ empty reg-stack register. If the register is live,
+ kill it now. Remove the DEAD/UNUSED note so we
+ don't try to kill it later too.
+
+ In reality the UNUSED note can be absent in some
+ complicated cases when the register is reused for
+ partially set variable. */
if (note)
emit_pop_insn (insn, regstack, *dest, EMIT_BEFORE);
else
- {
- note = find_reg_note (insn, REG_UNUSED, *dest);
- gcc_assert (note);
- }
- remove_note (insn, note);
+ note = find_reg_note (insn, REG_UNUSED, *dest);
+ if (note)
+ remove_note (insn, note);
replace_reg (dest, FIRST_STACK_REG + 1);
}
else
gcc44-pr39903.patch:
--- NEW FILE gcc44-pr39903.patch ---
2009-04-26 H.J. Lu <hongjiu.lu at intel.com>
PR target/39903
* config/i386/i386.c (construct_container): Don't call
gen_reg_or_parallel with BLKmode for X86_64_SSE_CLASS,
X86_64_SSESF_CLASS and X86_64_SSEDF_CLASS.
PR target/39903
* gcc.dg/torture/pr39903-1.c: New.
* gcc.dg/torture/pr39903-2.c: Likewise.
--- gcc/config/i386/i386.c (revision 146817)
+++ gcc/config/i386/i386.c (working copy)
@@ -5466,7 +5466,10 @@ construct_container (enum machine_mode m
case X86_64_SSE_CLASS:
case X86_64_SSESF_CLASS:
case X86_64_SSEDF_CLASS:
- return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
+ if (mode != BLKmode)
+ return gen_reg_or_parallel (mode, orig_mode,
+ SSE_REGNO (sse_regno));
+ break;
case X86_64_X87_CLASS:
case X86_64_COMPLEX_X87_CLASS:
return gen_rtx_REG (mode, FIRST_STACK_REG);
--- gcc/testsuite/gcc.dg/torture/pr39903-1.c (revision 0)
+++ gcc/testsuite/gcc.dg/torture/pr39903-1.c (revision 0)
@@ -0,0 +1,24 @@
+/* PR target/39903 */
+/* { dg-do run } */
+/* { dg-options "-Wno-psabi" } */
+
+struct X {
+ double d;
+ double b[];
+};
+
+struct X __attribute__((noinline))
+foo (double d)
+{
+ struct X x;
+ x.d = d;
+ return x;
+}
+extern void abort (void);
+int main()
+{
+ struct X x = foo(3.0);
+ if (x.d != 3.0)
+ abort ();
+ return 0;
+}
--- gcc/testsuite/gcc.dg/torture/pr39903-2.c (revision 0)
+++ gcc/testsuite/gcc.dg/torture/pr39903-2.c (revision 0)
@@ -0,0 +1,24 @@
+/* PR target/39903 */
+/* { dg-do run } */
+/* { dg-options "-Wno-psabi" } */
+
+struct X {
+ float d;
+ float b[];
+};
+
+struct X __attribute__((noinline))
+foo (float d)
+{
+ struct X x;
+ x.d = d;
+ return x;
+}
+extern void abort (void);
+int main()
+{
+ struct X x = foo(3.0);
+ if (x.d != 3.0)
+ abort ();
+ return 0;
+}
Index: .cvsignore
===================================================================
RCS file: /cvs/pkgs/rpms/gcc/F-11/.cvsignore,v
retrieving revision 1.272
retrieving revision 1.273
diff -u -r1.272 -r1.273
--- .cvsignore 24 Apr 2009 08:04:27 -0000 1.272
+++ .cvsignore 27 Apr 2009 12:43:31 -0000 1.273
@@ -1,2 +1,2 @@
fastjar-0.97.tar.gz
-gcc-4.4.0-20090424.tar.bz2
+gcc-4.4.0-20090427.tar.bz2
Index: gcc.spec
===================================================================
RCS file: /cvs/pkgs/rpms/gcc/F-11/gcc.spec,v
retrieving revision 1.46
retrieving revision 1.47
diff -u -r1.46 -r1.47
--- gcc.spec 24 Apr 2009 08:04:27 -0000 1.46
+++ gcc.spec 27 Apr 2009 12:43:31 -0000 1.47
@@ -1,9 +1,9 @@
-%define DATE 20090424
-%define SVNREV 146674
+%define DATE 20090427
+%define SVNREV 146836
%define gcc_version 4.4.0
# Note, gcc_release must be integer, if you want to add suffixes to
# %{release}, append them after %{gcc_release} on Release: line.
-%define gcc_release 2
+%define gcc_release 3
%define _unpackaged_files_terminate_build 0
%define multilib_64_archs sparc64 ppc64 s390x x86_64
%define include_gappletviewer 1
@@ -147,15 +147,12 @@
Patch21: gcc44-cloog-dl.patch
Patch22: gcc44-raw-string.patch
Patch24: gcc44-atom.patch
-Patch26: gcc44-power7.patch
+Patch25: gcc44-power7.patch
+Patch26: gcc44-power7-2.patch
+Patch27: gcc44-power7-3.patch
Patch28: gcc44-pr38757.patch
-Patch30: gcc44-pr39543.patch
-Patch31: gcc44-pr39794.patch
-Patch32: gcc44-rh459374-1.patch
-Patch33: gcc44-rh459374-2.patch
-Patch34: gcc44-rh459374-3.patch
-Patch35: gcc44-cswtch.patch
-Patch36: gcc44-pr39867.patch
+Patch29: gcc44-pr39856.patch
+Patch30: gcc44-pr39903.patch
Patch1000: fastjar-0.97-segfault.patch
@@ -441,15 +438,12 @@
%endif
%patch22 -p0 -b .raw-string~
%patch24 -p0 -b .atom~
-%patch26 -p0 -b .power7~
+%patch25 -p0 -b .power7~
+%patch26 -p0 -b .power7-2~
+%patch27 -p0 -b .power7-3~
%patch28 -p0 -b .pr38757~
-%patch30 -p0 -b .pr39543~
-%patch31 -p0 -b .pr39794~
-%patch32 -p0 -b .rh459374-1~
-%patch33 -p0 -b .rh459374-2~
-%patch34 -p0 -b .rh459374-3~
-%patch35 -p0 -b .cswtch~
-%patch36 -p0 -b .pr39867~
+%patch29 -p0 -b .pr39856~
+%patch30 -p0 -b .pr39903~
# This testcase doesn't compile.
rm libjava/testsuite/libjava.lang/PR35020*
@@ -1760,6 +1754,16 @@
%doc rpm.doc/changelogs/libmudflap/ChangeLog*
%changelog
+* Mon Apr 27 2009 Jakub Jelinek <jakub at redhat.com> 4.4.0-3
+- update from gcc-4_4-branch
+ - PR bootstrap/39739
+ - fix -Wunused-value (#497545, PR c/39889)
+- backport further power7-meissner branch changes (#497816)
+- fix reg-stack ICE on SPEC2k6 453.povray with -m32 -O3 -msse3
+ (PR target/39856)
+- fix x86_64 ICE on passing structure with flexible array member
+ (PR target/39903)
+
* Fri Apr 24 2009 Jakub Jelinek <jakub at redhat.com> 4.4.0-2
- update from gcc-4_4-branch
- PR c++/38228
@@ -1818,7 +1822,7 @@
tree-optimization/39557
- emit debuginfo for block local externs in C (PR debug/39563)
- fix -maltivec conditional vector macro (PR target/39558)
-- teach fwprop to handle asm (PR rtl-optimization/39543)
+- teach fwprop to handle asm (PR inline-asm/39543)
* Tue Mar 24 2009 Jakub Jelinek <jakub at redhat.com> 4.4.0-0.29
- update from trunk
Index: sources
===================================================================
RCS file: /cvs/pkgs/rpms/gcc/F-11/sources,v
retrieving revision 1.275
retrieving revision 1.276
diff -u -r1.275 -r1.276
--- sources 24 Apr 2009 08:04:27 -0000 1.275
+++ sources 27 Apr 2009 12:43:32 -0000 1.276
@@ -1,2 +1,2 @@
2659f09c2e43ef8b7d4406321753f1b2 fastjar-0.97.tar.gz
-441af0d1283e61c52f241a06710f56a3 gcc-4.4.0-20090424.tar.bz2
+373986714230ac85e2d6d6e4abb107e0 gcc-4.4.0-20090427.tar.bz2
--- gcc44-cswtch.patch DELETED ---
--- gcc44-pr39543.patch DELETED ---
--- gcc44-pr39794.patch DELETED ---
--- gcc44-pr39867.patch DELETED ---
--- gcc44-rh459374-1.patch DELETED ---
--- gcc44-rh459374-2.patch DELETED ---
--- gcc44-rh459374-3.patch DELETED ---
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