rpms/kernel/F-12 drm-nouveau.patch, 1.69, 1.70 kernel.spec, 1.1948, 1.1949
Ben Skeggs
bskeggs at fedoraproject.org
Fri Dec 4 04:48:59 UTC 2009
Author: bskeggs
Update of /cvs/pkgs/rpms/kernel/F-12
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv1914
Modified Files:
drm-nouveau.patch kernel.spec
Log Message:
* Fri Dec 04 2009 Ben Skeggs <bskeggs at redhat.com> 2.6.31.6-163
- nouveau: reduce debug level of some warning messages (rh#543883)
- nouveau: modesetting fixes on nva5/nva8
- nouveau: suspend/resume fixes on nva5/nva8 (bios opcode 0x8d)
- nouveau: cleanup chipset/arch handling, fail init on unknown chipsets
- nouveau: fix failure to detect some outputs when dcb table is odd
- nouveau: eliminate unnecessary cursor state changes on nv50
drm-nouveau.patch:
drivers/gpu/drm/Kconfig | 56
drivers/gpu/drm/Makefile | 2
drivers/gpu/drm/i2c/Makefile | 4
drivers/gpu/drm/i2c/ch7006_drv.c | 531
drivers/gpu/drm/i2c/ch7006_mode.c | 473
drivers/gpu/drm/i2c/ch7006_priv.h | 344
drivers/gpu/drm/nouveau/Makefile | 30
drivers/gpu/drm/nouveau/nouveau_acpi.c | 125
drivers/gpu/drm/nouveau/nouveau_backlight.c | 155
drivers/gpu/drm/nouveau/nouveau_bios.c | 6046 ++++++
drivers/gpu/drm/nouveau/nouveau_bios.h | 289
drivers/gpu/drm/nouveau/nouveau_bo.c | 663
drivers/gpu/drm/nouveau/nouveau_calc.c | 478
drivers/gpu/drm/nouveau/nouveau_channel.c | 468
drivers/gpu/drm/nouveau/nouveau_connector.c | 812
drivers/gpu/drm/nouveau/nouveau_connector.h | 54
drivers/gpu/drm/nouveau/nouveau_crtc.h | 95
drivers/gpu/drm/nouveau/nouveau_debugfs.c | 155
drivers/gpu/drm/nouveau/nouveau_display.c | 115
drivers/gpu/drm/nouveau/nouveau_dma.c | 206
drivers/gpu/drm/nouveau/nouveau_dma.h | 157
drivers/gpu/drm/nouveau/nouveau_drv.c | 413
drivers/gpu/drm/nouveau/nouveau_drv.h | 1270 +
drivers/gpu/drm/nouveau/nouveau_encoder.h | 66
drivers/gpu/drm/nouveau/nouveau_fb.h | 47
drivers/gpu/drm/nouveau/nouveau_fbcon.c | 380
drivers/gpu/drm/nouveau/nouveau_fbcon.h | 47
drivers/gpu/drm/nouveau/nouveau_fence.c | 262
drivers/gpu/drm/nouveau/nouveau_gem.c | 976 +
drivers/gpu/drm/nouveau/nouveau_hw.c | 1080 +
drivers/gpu/drm/nouveau/nouveau_hw.h | 455
drivers/gpu/drm/nouveau/nouveau_i2c.c | 257
drivers/gpu/drm/nouveau/nouveau_i2c.h | 45
drivers/gpu/drm/nouveau/nouveau_ioc32.c | 72
drivers/gpu/drm/nouveau/nouveau_irq.c | 693
drivers/gpu/drm/nouveau/nouveau_mem.c | 583
drivers/gpu/drm/nouveau/nouveau_notifier.c | 196
drivers/gpu/drm/nouveau/nouveau_object.c | 1294 +
drivers/gpu/drm/nouveau/nouveau_reg.h | 788
drivers/gpu/drm/nouveau/nouveau_sgdma.c | 321
drivers/gpu/drm/nouveau/nouveau_state.c | 865
drivers/gpu/drm/nouveau/nouveau_ttm.c | 131
drivers/gpu/drm/nouveau/nv04_crtc.c | 1002 +
drivers/gpu/drm/nouveau/nv04_cursor.c | 70
drivers/gpu/drm/nouveau/nv04_dac.c | 528
drivers/gpu/drm/nouveau/nv04_dfp.c | 621
drivers/gpu/drm/nouveau/nv04_display.c | 293
drivers/gpu/drm/nouveau/nv04_fb.c | 21
drivers/gpu/drm/nouveau/nv04_fbcon.c | 316
drivers/gpu/drm/nouveau/nv04_fifo.c | 271
drivers/gpu/drm/nouveau/nv04_graph.c | 579
drivers/gpu/drm/nouveau/nv04_instmem.c | 208
drivers/gpu/drm/nouveau/nv04_mc.c | 20
drivers/gpu/drm/nouveau/nv04_timer.c | 51
drivers/gpu/drm/nouveau/nv04_tv.c | 305
drivers/gpu/drm/nouveau/nv10_fb.c | 24
drivers/gpu/drm/nouveau/nv10_fifo.c | 260
drivers/gpu/drm/nouveau/nv10_graph.c | 892
drivers/gpu/drm/nouveau/nv17_gpio.c | 92
drivers/gpu/drm/nouveau/nv17_tv.c | 681
drivers/gpu/drm/nouveau/nv17_tv.h | 156
drivers/gpu/drm/nouveau/nv17_tv_modes.c | 583
drivers/gpu/drm/nouveau/nv20_graph.c | 780
drivers/gpu/drm/nouveau/nv40_fb.c | 62
drivers/gpu/drm/nouveau/nv40_fifo.c | 314
drivers/gpu/drm/nouveau/nv40_graph.c | 2239 ++
drivers/gpu/drm/nouveau/nv40_mc.c | 38
drivers/gpu/drm/nouveau/nv50_crtc.c | 769
drivers/gpu/drm/nouveau/nv50_cursor.c | 156
drivers/gpu/drm/nouveau/nv50_dac.c | 304
drivers/gpu/drm/nouveau/nv50_display.c | 998 +
drivers/gpu/drm/nouveau/nv50_display.h | 46
drivers/gpu/drm/nouveau/nv50_evo.h | 113
drivers/gpu/drm/nouveau/nv50_fbcon.c | 273
drivers/gpu/drm/nouveau/nv50_fifo.c | 494
drivers/gpu/drm/nouveau/nv50_graph.c | 470
drivers/gpu/drm/nouveau/nv50_grctx.h |26832 ++++++++++++++++++++++++++++
drivers/gpu/drm/nouveau/nv50_instmem.c | 509
drivers/gpu/drm/nouveau/nv50_mc.c | 40
drivers/gpu/drm/nouveau/nv50_sor.c | 269
drivers/gpu/drm/nouveau/nvreg.h | 535
drivers/gpu/drm/ttm/ttm_bo.c | 4
include/drm/Kbuild | 1
include/drm/i2c/ch7006.h | 86
include/drm/nouveau_drm.h | 220
85 files changed, 64024 insertions(+)
Index: drm-nouveau.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-12/drm-nouveau.patch,v
retrieving revision 1.69
retrieving revision 1.70
diff -u -p -r1.69 -r1.70
--- drm-nouveau.patch 1 Dec 2009 23:24:14 -0000 1.69
+++ drm-nouveau.patch 4 Dec 2009 04:48:58 -0000 1.70
@@ -1486,7 +1486,7 @@ index 0000000..fd75226
+obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
new file mode 100644
-index 0000000..ec0f2f3
+index 0000000..1cf4882
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -0,0 +1,125 @@
@@ -1554,7 +1554,7 @@ index 0000000..ec0f2f3
+
+ err = acpi_evaluate_object(handle, "_DSM", &input, &output);
+ if (err) {
-+ NV_ERROR(dev, "failed to evaluate _DSM: %d\n", err);
++ NV_INFO(dev, "failed to evaluate _DSM: %d\n", err);
+ return err;
+ }
+
@@ -1778,10 +1778,10 @@ index 0000000..20564f8
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
new file mode 100644
-index 0000000..6ddeca2
+index 0000000..3595be1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
-@@ -0,0 +1,5988 @@
+@@ -0,0 +1,6046 @@
+/*
+ * Copyright 2005-2006 Erik Waling
+ * Copyright 2006 Stephane Marchesin
@@ -1870,11 +1870,12 @@ index 0000000..6ddeca2
+
+static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ uint32_t pci_nv_20, save_pci_nv_20;
+ int pcir_ptr;
+ int i;
+
-+ if (nv_arch(dev) >= NV_50)
++ if (dev_priv->card_type >= NV_50)
+ pci_nv_20 = 0x88050;
+ else
+ pci_nv_20 = NV_PBUS_PCI_NV_20;
@@ -1913,10 +1914,11 @@ index 0000000..6ddeca2
+
+static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ uint32_t old_bar0_pramin = 0;
+ int i;
+
-+ if (nv_arch(dev) >= NV_50) {
++ if (dev_priv->card_type >= NV_50) {
+ uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
+
+ if (!vbios_vram)
@@ -1935,7 +1937,7 @@ index 0000000..6ddeca2
+ data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
+
+out:
-+ if (nv_arch(dev) >= NV_50)
++ if (dev_priv->card_type >= NV_50)
+ nv_wr32(dev, 0x1700, old_bar0_pramin);
+}
+
@@ -2075,18 +2077,21 @@ index 0000000..6ddeca2
+static uint32_t
+munge_reg(struct nvbios *bios, uint32_t reg)
+{
-+ if (nv_arch(bios->dev) < NV_50)
-+ return reg;
++ struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
++ struct dcb_entry *dcbent = bios->display.output;
+
-+ if (!(reg & 0x40000000))
++ if (dev_priv->card_type < NV_50)
+ return reg;
+
-+ BUG_ON(!bios->display.output);
++ if (reg & 0x40000000) {
++ BUG_ON(!dcbent);
+
-+ if (reg & 0x40000000)
-+ reg += (ffs(bios->display.output->or) - 1) * 0x800;
++ reg += (ffs(dcbent->or) - 1) * 0x800;
++ if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
++ reg += 0x00000080;
++ }
+
-+ reg &= ~0x40000000;
++ reg &= ~0x60000000;
+ return reg;
+}
+
@@ -4313,7 +4318,20 @@ index 0000000..6ddeca2
+init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
+{
+ /*
-+ * INIT_85 opcode: 0x8C ('')
++ * INIT_8C opcode: 0x8C ('')
++ *
++ * NOP so far....
++ *
++ */
++
++ return true;
++}
++
++static bool
++init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
++{
++ /*
++ * INIT_8D opcode: 0x8D ('')
+ *
+ * NOP so far....
+ *
@@ -4768,6 +4786,7 @@ index 0000000..6ddeca2
+ /* INIT_RAM_RESTRICT_PLL's length is adjusted by the BIT M table */
+ { "INIT_RAM_RESTRICT_PLL" , 0x87, 2 , 0 , 0 , init_ram_restrict_pll },
+ { "INIT_8C" , 0x8C, 1 , 0 , 0 , init_8c },
++ { "INIT_8D" , 0x8D, 1 , 0 , 0 , init_8d },
+ { "INIT_GPIO" , 0x8E, 1 , 0 , 0 , init_gpio },
+ /* INIT_RAM_RESTRICT_ZM_REG_GROUP's mult is loaded by M table in BIT */
+ { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, 7 , 6 , 0 , init_ram_restrict_zm_reg_group },
@@ -5139,8 +5158,11 @@ index 0000000..6ddeca2
+ return 0;
+}
+
-+static int get_fp_strap(struct drm_device *dev, struct nvbios *bios)
++static int
++get_fp_strap(struct drm_device *dev, struct nvbios *bios)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++
+ /*
+ * The fp strap is normally dictated by the "User Strap" in
+ * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
@@ -5153,7 +5175,7 @@ index 0000000..6ddeca2
+ if (bios->major_version < 5 && bios->data[0x48] & 0x4)
+ return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
+
-+ if (nv_arch(dev) >= NV_50)
++ if (dev_priv->card_type >= NV_50)
+ return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
+ else
+ return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
@@ -5774,6 +5796,7 @@ index 0000000..6ddeca2
+ case 0x20:
+ case 0x21:
+ case 0x30:
++ case 0x40:
+ headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
+ recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
+ entries = bios->data[bios->pll_limit_tbl_ptr + 3];
@@ -5922,7 +5945,7 @@ index 0000000..6ddeca2
+ pll_lim->refclk = 25000;
+ }
+ }
-+ } else if (pll_lim_ver) { /* ver 0x30 */
++ } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
+ uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
+ uint8_t *record = NULL;
+ int i;
@@ -5962,6 +5985,42 @@ index 0000000..6ddeca2
+ pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
+ pll_lim->log2p_bias = record[27];
+ pll_lim->refclk = ROM32(record[28]);
++ } else if (pll_lim_ver) { /* ver 0x40 */
++ uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
++ uint8_t *record = NULL;
++ int i;
++
++ BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
++ limit_match);
++
++ for (i = 0; i < entries; i++, entry += recordlen) {
++ if (ROM32(entry[3]) == limit_match) {
++ record = &bios->data[ROM16(entry[1])];
++ break;
++ }
++ }
++
++ if (!record) {
++ NV_ERROR(dev, "Register 0x%08x not found in PLL "
++ "limits table", limit_match);
++ return -ENOENT;
++ }
++
++ pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
++ pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
++ pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
++ pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
++ pll_lim->vco1.min_m = record[8];
++ pll_lim->vco1.max_m = record[9];
++ pll_lim->vco1.min_n = record[10];
++ pll_lim->vco1.max_n = record[11];
++ pll_lim->min_p = record[12];
++ pll_lim->max_p = record[13];
++ /* where did this go to?? */
++ if (limit_match == 0x00614100 || limit_match == 0x00614900)
++ pll_lim->refclk = 27000;
++ else
++ pll_lim->refclk = 100000;
+ }
+
+ /*
@@ -6420,8 +6479,11 @@ index 0000000..6ddeca2
+
+#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
+
-+static int parse_bit_table(struct drm_device *dev, struct nvbios *bios, const uint16_t bitoffset, struct bit_table *table)
++static int
++parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
++ struct bit_table *table)
+{
++ struct drm_device *dev = bios->dev;
+ uint8_t maxentries = bios->data[bitoffset + 4];
+ int i, offset;
+ struct bit_entry bitentry;
@@ -6439,13 +6501,12 @@ index 0000000..6ddeca2
+ return table->parse_fn(dev, bios, &bitentry);
+ }
+
-+ NV_ERROR(dev, "BIT table '%c' not found\n", table->id);
-+
++ NV_INFO(dev, "BIT table '%c' not found\n", table->id);
+ return -ENOSYS;
+}
+
-+static int parse_bit_structure(struct drm_device *dev, struct nvbios *bios,
-+ const uint16_t bitoffset)
++static int
++parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
+{
+ int ret;
+
@@ -6455,23 +6516,23 @@ index 0000000..6ddeca2
+ * functions shouldn't be actually *doing* anything apart from pulling
+ * data from the image into the bios struct, thus no interdependencies
+ */
-+ ret = parse_bit_table(dev, bios, bitoffset, &BIT_TABLE('i', i));
++ ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
+ if (ret) /* info? */
+ return ret;
+ if (bios->major_version >= 0x60) /* g80+ */
-+ parse_bit_table(dev, bios, bitoffset, &BIT_TABLE('A', A));
-+ ret = parse_bit_table(dev, bios, bitoffset, &BIT_TABLE('C', C));
++ parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
++ ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
+ if (ret)
+ return ret;
-+ parse_bit_table(dev, bios, bitoffset, &BIT_TABLE('D', display));
-+ ret = parse_bit_table(dev, bios, bitoffset, &BIT_TABLE('I', init));
++ parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
++ ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
+ if (ret)
+ return ret;
-+ parse_bit_table(dev, bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
-+ parse_bit_table(dev, bios, bitoffset, &BIT_TABLE('L', lvds));
-+ parse_bit_table(dev, bios, bitoffset, &BIT_TABLE('T', tmds));
-+ parse_bit_table(dev, bios, bitoffset, &BIT_TABLE('U', U));
-+ parse_bit_table(dev, bios, bitoffset, &BIT_TABLE('d', displayport));
++ parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
++ parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
++ parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
++ parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
++ parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
+
+ return 0;
+}
@@ -7095,6 +7156,7 @@ index 0000000..6ddeca2
+ break;
+ }
+ case OUTPUT_DP:
++ entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
+ entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
+ switch ((conf & 0x0f000000) >> 24) {
+ case 0xf:
@@ -7109,7 +7171,7 @@ index 0000000..6ddeca2
+ }
+ break;
+ case OUTPUT_TMDS:
-+ entry->tmdsconf.sor_link = (conf & 0x00000030) >> 4;
++ entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
+ break;
+ case 0xe:
+ /* weird g80 mobile type that "nv" treats as a terminator */
@@ -7383,13 +7445,9 @@ index 0000000..6ddeca2
+ if (configblock)
+ config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
+
-+ /*
-+ * Should we allow discontinuous DCBs? Certainly DCB I2C
-+ * tables can be discontinuous.
-+ */
+ if ((connection & 0x0000000f) == 0x0000000f)
-+ /* end of records */
-+ break;
++ continue;
++
+ if (connection == 0x00000000)
+ /* seen on an NV11 with DCB v1.5 */
+ break;
@@ -7618,7 +7676,7 @@ index 0000000..6ddeca2
+ bit_signature, sizeof(bit_signature));
+ if (offset) {
+ NV_TRACE(dev, "BIT BIOS found\n");
-+ return parse_bit_structure(dev, bios, offset + 6);
++ return parse_bit_structure(bios, offset + 6);
+ }
+
+ offset = findstr(bios->data, bios->length,
@@ -7772,10 +7830,10 @@ index 0000000..6ddeca2
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
new file mode 100644
-index 0000000..7cd7288
+index 0000000..1d5f10b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
-@@ -0,0 +1,280 @@
+@@ -0,0 +1,289 @@
+/*
+ * Copyright 2007-2008 Nouveau Project
+ *
@@ -7823,10 +7881,14 @@ index 0000000..7cd7288
+ uint8_t or;
+ bool duallink_possible;
+ union {
++ struct sor_conf {
++ int link;
++ } sorconf;
+ struct {
+ int maxfreq;
+ } crtconf;
+ struct {
++ struct sor_conf sor;
+ bool use_straps_for_mode;
+ bool use_power_scripts;
+ } lvdsconf;
@@ -7834,11 +7896,12 @@ index 0000000..7cd7288
+ bool has_component_output;
+ } tvconf;
+ struct {
++ struct sor_conf sor;
+ int link_nr;
+ int link_bw;
+ } dpconf;
+ struct {
-+ int sor_link;
++ struct sor_conf sor;
+ } tmdsconf;
+ };
+ bool i2c_upper_default;
@@ -7956,6 +8019,10 @@ index 0000000..7cd7288
+ */
+ uint8_t max_usable_log2p;
+ uint8_t log2p_bias;
++
++ uint8_t min_p;
++ uint8_t max_p;
++
+ int refclk;
+};
+
@@ -8727,10 +8794,10 @@ index 0000000..8d1383a
+
diff --git a/drivers/gpu/drm/nouveau/nouveau_calc.c b/drivers/gpu/drm/nouveau/nouveau_calc.c
new file mode 100644
-index 0000000..81271d6
+index 0000000..ee2b845
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_calc.c
-@@ -0,0 +1,469 @@
+@@ -0,0 +1,478 @@
+/*
+ * Copyright 1993-2003 NVIDIA, Corporation
+ * Copyright 2007-2009 Stuart Bennett
@@ -8928,6 +8995,7 @@ index 0000000..81271d6
+nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
+ int *burst, int *lwm)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nv_fifo_info fifo_data;
+ struct nv_sim_state sim_data;
+ int MClk = nouveau_hw_get_clock(dev, MPLL);
@@ -8956,7 +9024,7 @@ index 0000000..81271d6
+ sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
+ }
+
-+ if (nv_arch(dev) == NV_04)
++ if (dev_priv->card_type == NV_04)
+ nv04_calc_arb(&fifo_data, &sim_data);
+ else
+ nv10_calc_arb(&fifo_data, &sim_data);
@@ -8981,7 +9049,9 @@ index 0000000..81271d6
+void
+nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)
+{
-+ if (nv_arch(dev) < NV_30)
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++
++ if (dev_priv->card_type < NV_30)
+ nv04_update_arb(dev, vclk, bpp, burst, lwm);
+ else if ((dev->pci_device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
+ (dev->pci_device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
@@ -9008,40 +9078,46 @@ index 0000000..81271d6
+ int minvco = pll_lim->vco1.minfreq, maxvco = pll_lim->vco1.maxfreq;
+ int minM = pll_lim->vco1.min_m, maxM = pll_lim->vco1.max_m;
+ int minN = pll_lim->vco1.min_n, maxN = pll_lim->vco1.max_n;
-+ int minU = pll_lim->vco1.min_inputfreq, maxU = pll_lim->vco1.max_inputfreq;
-+ int maxlog2P = pll_lim->max_usable_log2p;
++ int minU = pll_lim->vco1.min_inputfreq;
++ int maxU = pll_lim->vco1.max_inputfreq;
++ int minP = pll_lim->max_p ? pll_lim->min_p : 0;
++ int maxP = pll_lim->max_p ? pll_lim->max_p : pll_lim->max_usable_log2p;
+ int crystal = pll_lim->refclk;
-+ int M, N, log2P, P;
++ int M, N, thisP, P;
+ int clkP, calcclk;
+ int delta, bestdelta = INT_MAX;
+ int bestclk = 0;
+
+ /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */
+ /* possibly correlated with introduction of 27MHz crystal */
-+ if (cv < 0x17 || cv == 0x1a || cv == 0x20) {
-+ if (clk > 250000)
-+ maxM = 6;
-+ if (clk > 340000)
-+ maxM = 2;
-+ } else if (cv < 0x40) {
-+ if (clk > 150000)
-+ maxM = 6;
-+ if (clk > 200000)
-+ maxM = 4;
-+ if (clk > 340000)
-+ maxM = 2;
++ if (dev_priv->card_type < NV_50) {
++ if (cv < 0x17 || cv == 0x1a || cv == 0x20) {
++ if (clk > 250000)
++ maxM = 6;
++ if (clk > 340000)
++ maxM = 2;
++ } else if (cv < 0x40) {
++ if (clk > 150000)
++ maxM = 6;
++ if (clk > 200000)
++ maxM = 4;
++ if (clk > 340000)
++ maxM = 2;
++ }
+ }
+
-+ if ((clk << maxlog2P) < minvco) {
-+ minvco = clk << maxlog2P;
++ P = pll_lim->max_p ? maxP : (1 << maxP);
++ if ((clk * P) < minvco) {
++ minvco = clk * maxP;
+ maxvco = minvco * 2;
+ }
++
+ if (clk + clk/200 > maxvco) /* +0.5% */
+ maxvco = clk + clk/200;
+
+ /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
-+ for (log2P = 0; log2P <= maxlog2P; log2P++) {
-+ P = 1 << log2P;
++ for (thisP = minP; thisP <= maxP; thisP++) {
++ P = pll_lim->max_p ? thisP : (1 << thisP);
+ clkP = clk * P;
+
+ if (clkP < minvco)
@@ -9074,7 +9150,7 @@ index 0000000..81271d6
+ bestclk = calcclk;
+ bestpv->N1 = N;
+ bestpv->M1 = M;
-+ bestpv->log2P = log2P;
++ bestpv->log2P = thisP;
+ if (delta == 0) /* except this one */
+ return bestclk;
+ }
@@ -11731,10 +11807,10 @@ index 0000000..d8de3f6
+MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
new file mode 100644
-index 0000000..a4ab9d1
+index 0000000..106dfe6
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
-@@ -0,0 +1,1299 @@
+@@ -0,0 +1,1270 @@
+/*
+ * Copyright 2005 Stephane Marchesin.
+ * All Rights Reserved.
@@ -12193,16 +12269,12 @@ index 0000000..a4ab9d1
+};
+
+enum nouveau_card_type {
-+ NV_UNKNOWN = 0,
-+ NV_04 = 4,
-+ NV_05 = 5,
-+ NV_10 = 10,
-+ NV_11 = 11,
-+ NV_17 = 17,
-+ NV_20 = 20,
-+ NV_30 = 30,
-+ NV_40 = 40,
-+ NV_50 = 50,
++ NV_04 = 0x00,
++ NV_10 = 0x10,
++ NV_20 = 0x20,
++ NV_30 = 0x30,
++ NV_40 = 0x40,
++ NV_50 = 0x50,
+};
+
+struct drm_nouveau_private {
@@ -12968,39 +13040,13 @@ index 0000000..a4ab9d1
+ NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
+} while (0)
+
-+static inline enum nouveau_card_type
-+nv_arch(struct drm_device *dev)
-+{
-+ struct drm_nouveau_private *dev_priv = dev->dev_private;
-+
-+ switch (dev_priv->chipset & 0xf0) {
-+ case 0x00:
-+ return NV_04;
-+ case 0x10:
-+ return NV_10;
-+ case 0x20:
-+ return NV_20;
-+ case 0x30:
-+ return NV_30;
-+ case 0x40:
-+ case 0x60:
-+ return NV_40;
-+ case 0x50:
-+ case 0x80:
-+ case 0x90:
-+ case 0xa0:
-+ return NV_50;
-+ default:
-+ return NV_UNKNOWN;
-+ }
-+}
-+
+static inline bool
+nv_two_heads(struct drm_device *dev)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ const int impl = dev->pci_device & 0x0ff0;
+
-+ if (nv_arch(dev) >= NV_10 && impl != 0x0100 &&
++ if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
+ impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
+ return true;
+
@@ -13016,9 +13062,10 @@ index 0000000..a4ab9d1
+static inline bool
+nv_two_reg_pll(struct drm_device *dev)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ const int impl = dev->pci_device & 0x0ff0;
+
-+ if (impl == 0x0310 || impl == 0x0340 || nv_arch(dev) >= NV_40)
++ if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
+ return true;
+ return false;
+}
@@ -14850,10 +14897,10 @@ index 0000000..f10b53b
+
diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c b/drivers/gpu/drm/nouveau/nouveau_hw.c
new file mode 100644
-index 0000000..e78ee53
+index 0000000..fa137b9
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.c
-@@ -0,0 +1,1078 @@
+@@ -0,0 +1,1080 @@
+/*
+ * Copyright 2006 Dave Airlie
+ * Copyright 2007 Maarten Maathuis
@@ -15282,6 +15329,7 @@ index 0000000..e78ee53
+nouveau_hw_get_pllvals(struct drm_device *dev, enum pll_types plltype,
+ struct nouveau_pll_vals *pllvals)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ const uint32_t nv04_regs[MAX_PLL_TYPES] = { NV_PRAMDAC_NVPLL_COEFF,
+ NV_PRAMDAC_MPLL_COEFF,
+ NV_PRAMDAC_VPLL_COEFF,
@@ -15294,7 +15342,7 @@ index 0000000..e78ee53
+ struct pll_lims pll_lim;
+ int ret;
+
-+ if (nv_arch(dev) < NV_40)
++ if (dev_priv->card_type < NV_40)
+ reg1 = nv04_regs[plltype];
+ else
+ reg1 = nv40_regs[plltype];
@@ -15309,7 +15357,7 @@ index 0000000..e78ee53
+ pll2 = nvReadMC(dev, reg2);
+ }
+
-+ if (nv_arch(dev) == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
++ if (dev_priv->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
+ uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
+
+ /* check whether vpll has been forced into single stage mode */
@@ -15513,7 +15561,7 @@ index 0000000..e78ee53
+ struct nv04_crtc_reg *regp = &state->crtc_reg[head];
+ int i;
+
-+ if (nv_arch(dev) >= NV_10)
++ if (dev_priv->card_type >= NV_10)
+ regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
+
+ nouveau_hw_get_pllvals(dev, head ? VPLL2 : VPLL1, ®p->pllvals);
@@ -15566,10 +15614,10 @@ index 0000000..e78ee53
+
+ regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
+
-+ if (nv_arch(dev) >= NV_30)
++ if (dev_priv->card_type >= NV_30)
+ regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
+
-+ if (nv_arch(dev) == NV_40) {
++ if (dev_priv->card_type == NV_40) {
+ regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
+ regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
+ regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
@@ -15589,7 +15637,7 @@ index 0000000..e78ee53
+ uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
+ int i;
+
-+ if (nv_arch(dev) >= NV_10)
++ if (dev_priv->card_type >= NV_10)
+ NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
+
+ nouveau_hw_setpll(dev, pllreg, ®p->pllvals);
@@ -15637,10 +15685,10 @@ index 0000000..e78ee53
+
+ NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
+
-+ if (nv_arch(dev) >= NV_30)
++ if (dev_priv->card_type >= NV_30)
+ NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
+
-+ if (nv_arch(dev) == NV_40) {
++ if (dev_priv->card_type == NV_40) {
+ NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
+ NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
+ NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
@@ -15705,6 +15753,7 @@ index 0000000..e78ee53
+nv_save_state_ext(struct drm_device *dev, int head,
+ struct nv04_mode_state *state)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nv04_crtc_reg *regp = &state->crtc_reg[head];
+ int i;
+
@@ -15719,7 +15768,7 @@ index 0000000..e78ee53
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
-+ if (nv_arch(dev) >= NV_30)
++ if (dev_priv->card_type >= NV_30)
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
@@ -15727,14 +15776,14 @@ index 0000000..e78ee53
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
+
-+ if (nv_arch(dev) >= NV_10) {
++ if (dev_priv->card_type >= NV_10) {
+ regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
+ regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
+
-+ if (nv_arch(dev) >= NV_30)
++ if (dev_priv->card_type >= NV_30)
+ regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
+
-+ if (nv_arch(dev) == NV_40)
++ if (dev_priv->card_type == NV_40)
+ regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
+
+ if (nv_two_heads(dev))
@@ -15746,7 +15795,7 @@ index 0000000..e78ee53
+
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
-+ if (nv_arch(dev) >= NV_10) {
++ if (dev_priv->card_type >= NV_10) {
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
+ rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
@@ -15778,7 +15827,7 @@ index 0000000..e78ee53
+ uint32_t reg900;
+ int i;
+
-+ if (nv_arch(dev) >= NV_10) {
++ if (dev_priv->card_type >= NV_10) {
+ if (nv_two_heads(dev))
+ /* setting ENGINE_CTRL (EC) *must* come before
+ * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
@@ -15800,10 +15849,10 @@ index 0000000..e78ee53
+ NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
+ NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
+
-+ if (nv_arch(dev) >= NV_30)
++ if (dev_priv->card_type >= NV_30)
+ NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
+
-+ if (nv_arch(dev) == NV_40) {
++ if (dev_priv->card_type == NV_40) {
+ NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
+
+ reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
@@ -15825,20 +15874,20 @@ index 0000000..e78ee53
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
-+ if (nv_arch(dev) >= NV_30)
++ if (dev_priv->card_type >= NV_30)
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
+
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
-+ if (nv_arch(dev) == NV_40)
++ if (dev_priv->card_type == NV_40)
+ nv_fix_nv40_hw_cursor(dev, head);
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
+
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
-+ if (nv_arch(dev) >= NV_10) {
++ if (dev_priv->card_type >= NV_10) {
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
+ wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
@@ -15846,7 +15895,7 @@ index 0000000..e78ee53
+ }
+ /* NV11 and NV20 stop at 0x52. */
+ if (nv_gf4_disp_arch(dev)) {
-+ if (nv_arch(dev) == NV_10) {
++ if (dev_priv->card_type == NV_10) {
+ /* Not waiting for vertical retrace before modifying
+ CRE_53/CRE_54 causes lockups. */
+ nouveau_wait_until(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
@@ -15934,10 +15983,10 @@ index 0000000..e78ee53
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.h b/drivers/gpu/drm/nouveau/nouveau_hw.h
new file mode 100644
-index 0000000..ff4993a
+index 0000000..869130f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.h
-@@ -0,0 +1,448 @@
+@@ -0,0 +1,455 @@
+/*
+ * Copyright 2008 Stuart Bennett
+ *
@@ -16170,10 +16219,12 @@ index 0000000..ff4993a
+static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
+ int head, uint32_t reg)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ uint8_t val;
++
+ /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
+ * NVSetOwner for the relevant head to be programmed */
-+ if (head && nv_arch(dev) == NV_40)
++ if (head && dev_priv->card_type == NV_40)
+ reg += NV_PRMVIO_SIZE;
+
+ val = nv_rd08(dev, reg);
@@ -16184,9 +16235,11 @@ index 0000000..ff4993a
+static inline void NVWritePRMVIO(struct drm_device *dev,
+ int head, uint32_t reg, uint8_t value)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++
+ /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
+ * NVSetOwner for the relevant head to be programmed */
-+ if (head && nv_arch(dev) == NV_40)
++ if (head && dev_priv->card_type == NV_40)
+ reg += NV_PRMVIO_SIZE;
+
+ NV_REG_DEBUG(RMVIO, dev, "head %d reg %08x val %02x\n",
@@ -16334,7 +16387,9 @@ index 0000000..ff4993a
+
+static inline int nv_cursor_width(struct drm_device *dev)
+{
-+ return nv_arch(dev) >= NV_10 ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++
++ return dev_priv->card_type >= NV_10 ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
+}
+
+static inline void
@@ -16362,13 +16417,14 @@ index 0000000..ff4993a
+ *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
+ NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
+
-+ if (nv_arch(dev) == NV_40)
++ if (dev_priv->card_type == NV_40)
+ nv_fix_nv40_hw_cursor(dev, head);
+}
+
+static inline uint32_t
+nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp)
+{
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ int mask;
+
+ if (bpp == 15)
@@ -16377,7 +16433,7 @@ index 0000000..ff4993a
+ bpp = 8;
+
+ /* Alignment requirements taken from the Haiku driver */
-+ if (nv_arch(dev) == NV_04)
++ if (dev_priv->card_type == NV_04)
+ mask = 128 / bpp - 1;
+ else
+ mask = 512 / bpp - 1;
@@ -16780,10 +16836,10 @@ index 0000000..a2c30f4
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
new file mode 100644
-index 0000000..597007a
+index 0000000..39b9f51
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
-@@ -0,0 +1,696 @@
+@@ -0,0 +1,693 @@
+/*
+ * Copyright (C) 2006 Ben Skeggs.
+ *
@@ -17280,12 +17336,9 @@ index 0000000..597007a
+
+ switch (dev_priv->card_type) {
+ case NV_04:
-+ case NV_05:
+ nv04_graph_context_switch(dev);
+ break;
+ case NV_10:
-+ case NV_11:
-+ case NV_17:
+ nv10_graph_context_switch(dev);
+ break;
+ default:
@@ -17482,10 +17535,10 @@ index 0000000..597007a
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
new file mode 100644
-index 0000000..4a6fde6
+index 0000000..7d35bd5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
-@@ -0,0 +1,585 @@
+@@ -0,0 +1,583 @@
+/*
+ * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
+ * Copyright 2005 Stephane Marchesin
@@ -17852,10 +17905,11 @@ index 0000000..4a6fde6
+uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
++ uint32_t boot0;
++
+ switch (dev_priv->card_type) {
+ case NV_04:
-+ case NV_05: {
-+ uint32_t boot0 = nv_rd32(dev, NV03_BOOT_0);
++ boot0 = nv_rd32(dev, NV03_BOOT_0);
+ if (boot0 & 0x00000100)
+ return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
+
@@ -17870,10 +17924,7 @@ index 0000000..4a6fde6
+ return 4 * 1024 * 1024;
+ }
+ break;
-+ }
+ case NV_10:
-+ case NV_11:
-+ case NV_17:
+ case NV_20:
+ case NV_30:
+ case NV_40:
@@ -20696,10 +20747,10 @@ index 0000000..4c7f1e4
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
new file mode 100644
-index 0000000..205b6d9
+index 0000000..0de87b8
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
-@@ -0,0 +1,876 @@
+@@ -0,0 +1,865 @@
+/*
+ * Copyright 2005 Stephane Marchesin
+ * Copyright 2008 Stuart Bennett
@@ -21047,13 +21098,6 @@ index 0000000..205b6d9
+ if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
+ return 0;
+
-+ /* Determine exact chipset we're running on */
-+ if (dev_priv->card_type < NV_10)
-+ dev_priv->chipset = dev_priv->card_type;
-+ else
-+ dev_priv->chipset =
-+ (nv_rd32(dev, NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;
-+
+ /* Initialise internal driver API hooks */
+ ret = nouveau_init_engine_ptrs(dev);
+ if (ret)
@@ -21267,7 +21311,6 @@ index 0000000..205b6d9
+{
+ struct drm_nouveau_private *dev_priv;
+ uint32_t reg0;
-+ uint8_t architecture = 0;
+ resource_size_t mmio_start_offs;
+
+ dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
@@ -21321,41 +21364,38 @@ index 0000000..205b6d9
+ /* We're dealing with >=NV10 */
+ if ((reg0 & 0x0f000000) > 0) {
+ /* Bit 27-20 contain the architecture in hex */
-+ architecture = (reg0 & 0xff00000) >> 20;
++ dev_priv->chipset = (reg0 & 0xff00000) >> 20;
+ /* NV04 or NV05 */
+ } else if ((reg0 & 0xff00fff0) == 0x20004000) {
-+ architecture = 0x04;
-+ }
++ dev_priv->chipset = 0x04;
++ } else
++ dev_priv->chipset = 0xff;
+
-+ if (architecture >= 0x80)
-+ dev_priv->card_type = NV_50;
-+ else if (architecture >= 0x60)
++ switch (dev_priv->chipset & 0xf0) {
++ case 0x00:
++ case 0x10:
++ case 0x20:
++ case 0x30:
++ dev_priv->card_type = dev_priv->chipset & 0xf0;
++ break;
++ case 0x40:
++ case 0x60:
+ dev_priv->card_type = NV_40;
-+ else if (architecture >= 0x50)
++ break;
++ case 0x50:
++ case 0x80:
++ case 0x90:
++ case 0xa0:
+ dev_priv->card_type = NV_50;
-+ else if (architecture >= 0x40)
-+ dev_priv->card_type = NV_40;
-+ else if (architecture >= 0x30)
-+ dev_priv->card_type = NV_30;
-+ else if (architecture >= 0x20)
-+ dev_priv->card_type = NV_20;
-+ else if (architecture >= 0x17)
-+ dev_priv->card_type = NV_17;
-+ else if (architecture >= 0x11)
-+ dev_priv->card_type = NV_11;
-+ else if (architecture >= 0x10)
-+ dev_priv->card_type = NV_10;
-+ else if (architecture >= 0x04)
-+ dev_priv->card_type = NV_04;
-+ else
-+ dev_priv->card_type = NV_UNKNOWN;
++ break;
++ default:
++ NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
++ return -EINVAL;
++ }
+
-+ NV_INFO(dev, "Detected an NV%d generation card (0x%08x)\n",
++ NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
+ dev_priv->card_type, reg0);
+
-+ if (dev_priv->card_type == NV_UNKNOWN)
-+ return -EINVAL;
-+
+ /* map larger RAMIN aperture on NV40 cards */
+ dev_priv->ramin = NULL;
+ if (dev_priv->card_type >= NV_40) {
@@ -21715,10 +21755,10 @@ index 0000000..7818981
+
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
new file mode 100644
-index 0000000..0a5cfc1
+index 0000000..b913636
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
-@@ -0,0 +1,1001 @@
+@@ -0,0 +1,1002 @@
+/*
+ * Copyright 1993-2003 NVIDIA, Corporation
+ * Copyright 2006 Dave Airlie
@@ -21855,7 +21895,7 @@ index 0000000..0a5cfc1
+ state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
+
+ /* The blob uses this always, so let's do the same */
-+ if (nv_arch(dev) == NV_40)
++ if (dev_priv->card_type == NV_40)
+ state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
+ /* again nv40 and some nv43 act more like nv3x as described above */
+ if (dev_priv->chipset < 0x41)
@@ -21984,7 +22024,7 @@ index 0000000..0a5cfc1
+ horizEnd = horizTotal - 2;
+ horizBlankEnd = horizTotal + 4;
+#if 0
-+ if (dev->overlayAdaptor && nv_arch(dev) >= NV_10)
++ if (dev->overlayAdaptor && dev_priv->card_type >= NV_10)
+ /* This reportedly works around some video overlay bandwidth problems */
+ horizTotal += 2;
+#endif
@@ -22261,17 +22301,17 @@ index 0000000..0a5cfc1
+ regp->crtc_830 = mode->crtc_vdisplay - 3;
+ regp->crtc_834 = mode->crtc_vdisplay - 1;
+
-+ if (nv_arch(dev) == NV_40)
++ if (dev_priv->card_type == NV_40)
+ /* This is what the blob does */
+ regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
+
-+ if (nv_arch(dev) >= NV_30)
++ if (dev_priv->card_type >= NV_30)
+ regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
+
+ regp->crtc_cfg = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
+
+ /* Some misc regs */
-+ if (nv_arch(dev) == NV_40) {
++ if (dev_priv->card_type == NV_40) {
+ regp->CRTC[NV_CIO_CRE_85] = 0xFF;
+ regp->CRTC[NV_CIO_CRE_86] = 0x1;
+ }
@@ -22283,7 +22323,7 @@ index 0000000..0a5cfc1
+
+ /* Generic PRAMDAC regs */
+
-+ if (nv_arch(dev) >= NV_10)
++ if (dev_priv->card_type >= NV_10)
+ /* Only bit that bios and blob set. */
+ regp->nv10_cursync = (1 << 25);
+
@@ -22332,7 +22372,7 @@ index 0000000..0a5cfc1
+
+ nv_crtc_mode_set_vga(crtc, adjusted_mode);
+ /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
-+ if (nv_arch(dev) == NV_40)
++ if (dev_priv->card_type == NV_40)
+ NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
+ nv_crtc_mode_set_regs(crtc, adjusted_mode);
+ nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
@@ -22379,6 +22419,7 @@ index 0000000..0a5cfc1
+static void nv_crtc_prepare(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
+ struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
+
@@ -22391,7 +22432,7 @@ index 0000000..0a5cfc1
+
+ /* Some more preperation. */
+ NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
-+ if (nv_arch(dev) == NV_40) {
++ if (dev_priv->card_type == NV_40) {
+ uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
+ NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
+ }
@@ -22540,7 +22581,7 @@ index 0000000..0a5cfc1
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
+
-+ if (nv_arch(dev) >= NV_30) {
++ if (dev_priv->card_type >= NV_30) {
+ regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
+ }
@@ -22722,7 +22763,7 @@ index 0000000..0a5cfc1
+
diff --git a/drivers/gpu/drm/nouveau/nv04_cursor.c b/drivers/gpu/drm/nouveau/nv04_cursor.c
new file mode 100644
-index 0000000..fc9156e
+index 0000000..89a91b9
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv04_cursor.c
@@ -0,0 +1,70 @@
@@ -22782,7 +22823,7 @@ index 0000000..fc9156e
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
+ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
-+ if (nv_arch(dev) == NV_40)
++ if (dev_priv->card_type == NV_40)
+ nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
+}
+
@@ -22798,7 +22839,7 @@ index 0000000..fc9156e
+
diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
new file mode 100644
-index 0000000..f781761
+index 0000000..a5fa517
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv04_dac.c
@@ -0,0 +1,528 @@
@@ -23071,7 +23112,7 @@ index 0000000..f781761
+ /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
+ routput = (saved_routput & 0xfffffece) | head << 8;
+
-+ if (nv_arch(dev) >= NV_40) {
++ if (dev_priv->card_type >= NV_40) {
+ if (dcb->type == OUTPUT_TV)
+ routput |= 0x1a << 16;
+ else
@@ -25469,10 +25510,10 @@ index 0000000..396ee92
+
diff --git a/drivers/gpu/drm/nouveau/nv04_instmem.c b/drivers/gpu/drm/nouveau/nv04_instmem.c
new file mode 100644
-index 0000000..d87a426
+index 0000000..a20c206
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv04_instmem.c
-@@ -0,0 +1,210 @@
+@@ -0,0 +1,208 @@
+#include "drmP.h"
+#include "drm.h"
+#include "nouveau_drv.h"
@@ -25483,10 +25524,10 @@ index 0000000..d87a426
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
-+ if (dev_priv->card_type >= NV_40)
++ if (dev_priv->chipset >= 0x40)
+ return 128;
+ else
-+ if (dev_priv->card_type >= NV_17)
++ if (dev_priv->chipset >= 0x17)
+ return 64;
+
+ return 32;
@@ -25567,8 +25608,6 @@ index 0000000..d87a426
+ break;
+ case NV_30:
+ case NV_20:
-+ case NV_17:
-+ case NV_11:
+ case NV_10:
+ case NV_04:
+ default:
@@ -26109,7 +26148,7 @@ index 0000000..79e2d10
+}
diff --git a/drivers/gpu/drm/nouveau/nv10_fifo.c b/drivers/gpu/drm/nouveau/nv10_fifo.c
new file mode 100644
-index 0000000..877f00e
+index 0000000..7aeabf2
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv10_fifo.c
@@ -0,0 +1,260 @@
@@ -26331,12 +26370,12 @@ index 0000000..877f00e
+ (dev_priv->ramht_offset >> 8));
+ nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
+
-+ if (dev_priv->card_type > NV_11) {
++ if (dev_priv->chipset < 0x17) {
++ nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc_offset >> 8);
++ } else {
+ nv_wr32(dev, NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset >> 8) |
+ (1 << 16) /* 64 Bytes entry*/);
+ /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
-+ } else {
-+ nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc_offset >> 8);
+ }
+}
+
@@ -27371,7 +27410,7 @@ index 0000000..2e58c33
+}
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
new file mode 100644
-index 0000000..009fa48
+index 0000000..46cfd9c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -0,0 +1,681 @@
@@ -27668,7 +27707,7 @@ index 0000000..009fa48
+ /* Set the DACCLK register */
+ dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
+
-+ if (nv_arch(dev) == NV_40)
++ if (dev_priv->card_type == NV_40)
+ dacclk |= 0x1a << 16;
+
+ if (tv_norm->kind == CTV_ENC_MODE) {
@@ -27725,7 +27764,7 @@ index 0000000..009fa48
+ tv_regs->ptv_614 = 0x13;
+ }
+
-+ if (nv_arch(dev) >= NV_30) {
++ if (dev_priv->card_type >= NV_30) {
+ tv_regs->ptv_500 = 0xe8e0;
+ tv_regs->ptv_504 = 0x1710;
+ tv_regs->ptv_604 = 0x0;
@@ -32272,10 +32311,10 @@ index 0000000..2a3495e
+}
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
new file mode 100644
-index 0000000..768fb4f
+index 0000000..f8e28a1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
-@@ -0,0 +1,788 @@
+@@ -0,0 +1,769 @@
+/*
+ * Copyright (C) 2008 Maarten Maathuis.
+ * All Rights Reserved.
@@ -32368,7 +32407,6 @@ index 0000000..768fb4f
+ BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
+ OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
+ } else {
-+ nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
+ if (nv_crtc->cursor.visible)
+ nv_crtc->cursor.show(nv_crtc, false);
+ else
@@ -32553,23 +32591,6 @@ index 0000000..768fb4f
+ if (ret)
+ return ret;
+
-+ /*XXX: need a vbios image from one of these cards to look at
-+ * rather than just guessing. P isn't log2P on these
-+ * cards, it's uncertain at this stage what the PLL
-+ * limits tables have to say about these chips.
-+ *
-+ * getPLL_single will need some modifications to calculate
-+ * this properly too.
-+ *
-+ * for the moment, hacking up the PLL limits table with
-+ * a log2 value matching nv's maximum.
-+ */
-+ if (!limits.vco2.maxfreq) {
-+ NV_ERROR(dev, "single-stage PLL, please report: %d!!\n",
-+ limits.max_usable_log2p);
-+ limits.max_usable_log2p = 6;
-+ }
-+
+ ret = nouveau_calc_pll_mnp(dev, &limits, pclk, &pll);
+ if (ret <= 0)
+ return ret;
@@ -32585,7 +32606,7 @@ index 0000000..768fb4f
+ reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000;
+ nv_wr32(dev, pll_reg, 0x50000610);
+ nv_wr32(dev, pll_reg + 4, reg1 |
-+ (((1<<pll.log2P)-1) << 16) | (pll.M1 << 8) | pll.N1);
++ (pll.log2P << 16) | (pll.M1 << 8) | pll.N1);
+ }
+
+ return 0;
@@ -32646,9 +32667,8 @@ index 0000000..768fb4f
+
+ nouveau_bo_unmap(cursor);
+
-+ nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
-+ nv_crtc->cursor.offset -= dev_priv->vm_vram_base;
-+ nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
++ nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset -
++ dev_priv->vm_vram_base);
+ nv_crtc->cursor.show(nv_crtc, true);
+
+out:
@@ -33066,10 +33086,10 @@ index 0000000..768fb4f
+}
diff --git a/drivers/gpu/drm/nouveau/nv50_cursor.c b/drivers/gpu/drm/nouveau/nv50_cursor.c
new file mode 100644
-index 0000000..aa7baad
+index 0000000..e2e79a8
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_cursor.c
-@@ -0,0 +1,153 @@
+@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2008 Maarten Maathuis.
+ * All Rights Reserved.
@@ -33106,55 +33126,63 @@ index 0000000..aa7baad
+#include "nv50_display.h"
+
+static void
-+nv50_cursor_show(struct nouveau_crtc *crtc, bool update)
++nv50_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
+{
-+ struct drm_nouveau_private *dev_priv = crtc->base.dev->dev_private;
++ struct drm_nouveau_private *dev_priv = nv_crtc->base.dev->dev_private;
+ struct nouveau_channel *evo = dev_priv->evo;
-+ struct drm_device *dev = crtc->base.dev;
++ struct drm_device *dev = nv_crtc->base.dev;
+ int ret;
+
+ NV_DEBUG(dev, "\n");
+
-+ ret = RING_SPACE(evo, (dev_priv->chipset != 0x50 ? 4 : 2) + update * 2);
++ if (update && nv_crtc->cursor.visible)
++ return;
++
++ ret = RING_SPACE(evo, (dev_priv->chipset != 0x50 ? 5 : 3) + update * 2);
+ if (ret) {
+ NV_ERROR(dev, "no space while unhiding cursor\n");
+ return;
+ }
+
+ if (dev_priv->chipset != 0x50) {
-+ BEGIN_RING(evo, 0, NV84_EVO_CRTC(crtc->index, CURSOR_DMA), 1);
++ BEGIN_RING(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1);
+ OUT_RING(evo, NvEvoVRAM);
+ }
-+ BEGIN_RING(evo, 0, NV50_EVO_CRTC(crtc->index, CURSOR_CTRL), 1);
++ BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2);
+ OUT_RING(evo, NV50_EVO_CRTC_CURSOR_CTRL_SHOW);
++ OUT_RING(evo, nv_crtc->cursor.offset >> 8);
+
+ if (update) {
+ BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
+ OUT_RING(evo, 0);
+ FIRE_RING(evo);
-+ crtc->cursor.visible = true;
++ nv_crtc->cursor.visible = true;
+ }
+}
+
+static void
-+nv50_cursor_hide(struct nouveau_crtc *crtc, bool update)
++nv50_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
+{
-+ struct drm_nouveau_private *dev_priv = crtc->base.dev->dev_private;
++ struct drm_nouveau_private *dev_priv = nv_crtc->base.dev->dev_private;
+ struct nouveau_channel *evo = dev_priv->evo;
-+ struct drm_device *dev = crtc->base.dev;
++ struct drm_device *dev = nv_crtc->base.dev;
+ int ret;
+
+ NV_DEBUG(dev, "\n");
+
-+ ret = RING_SPACE(evo, (dev_priv->chipset != 0x50 ? 4 : 2) + update * 2);
++ if (update && !nv_crtc->cursor.visible)
++ return;
++
++ ret = RING_SPACE(evo, (dev_priv->chipset != 0x50 ? 5 : 3) + update * 2);
+ if (ret) {
+ NV_ERROR(dev, "no space while hiding cursor\n");
+ return;
+ }
-+ BEGIN_RING(evo, 0, NV50_EVO_CRTC(crtc->index, CURSOR_CTRL), 1);
++ BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2);
+ OUT_RING(evo, NV50_EVO_CRTC_CURSOR_CTRL_HIDE);
++ OUT_RING(evo, 0);
+ if (dev_priv->chipset != 0x50) {
-+ BEGIN_RING(evo, 0, NV84_EVO_CRTC(crtc->index, CURSOR_DMA), 1);
++ BEGIN_RING(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1);
+ OUT_RING(evo, NV84_EVO_CRTC_CURSOR_DMA_HANDLE_NONE);
+ }
+
@@ -33162,55 +33190,50 @@ index 0000000..aa7baad
+ BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
+ OUT_RING(evo, 0);
+ FIRE_RING(evo);
-+ crtc->cursor.visible = false;
++ nv_crtc->cursor.visible = false;
+ }
+}
+
+static void
-+nv50_cursor_set_pos(struct nouveau_crtc *crtc, int x, int y)
++nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
+{
-+ struct drm_device *dev = crtc->base.dev;
++ struct drm_device *dev = nv_crtc->base.dev;
+
-+ nv_wr32(dev, NV50_PDISPLAY_CURSOR_USER_POS(crtc->index),
++ nv_wr32(dev, NV50_PDISPLAY_CURSOR_USER_POS(nv_crtc->index),
+ ((y & 0xFFFF) << 16) | (x & 0xFFFF));
+ /* Needed to make the cursor move. */
-+ nv_wr32(dev, NV50_PDISPLAY_CURSOR_USER_POS_CTRL(crtc->index), 0);
++ nv_wr32(dev, NV50_PDISPLAY_CURSOR_USER_POS_CTRL(nv_crtc->index), 0);
+}
+
+static void
-+nv50_cursor_set_offset(struct nouveau_crtc *crtc, uint32_t offset)
++nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
+{
-+ struct drm_nouveau_private *dev_priv = crtc->base.dev->dev_private;
-+ struct nouveau_channel *evo = dev_priv->evo;
-+ struct drm_device *dev = crtc->base.dev;
-+ int ret;
-+
-+ NV_DEBUG(dev, "\n");
-+
-+ ret = RING_SPACE(evo, 2);
-+ if (ret) {
-+ NV_ERROR(dev, "no space while setting cursor image\n");
++ NV_DEBUG(nv_crtc->base.dev, "\n");
++ if (offset == nv_crtc->cursor.offset)
+ return;
++
++ nv_crtc->cursor.offset = offset;
++ if (nv_crtc->cursor.visible) {
++ nv_crtc->cursor.visible = false;
++ nv_crtc->cursor.show(nv_crtc, true);
+ }
-+ BEGIN_RING(evo, 0, NV50_EVO_CRTC(crtc->index, CURSOR_OFFSET), 1);
-+ OUT_RING(evo, offset >> 8);
+}
+
+int
-+nv50_cursor_init(struct nouveau_crtc *crtc)
++nv50_cursor_init(struct nouveau_crtc *nv_crtc)
+{
-+ crtc->cursor.set_offset = nv50_cursor_set_offset;
-+ crtc->cursor.set_pos = nv50_cursor_set_pos;
-+ crtc->cursor.hide = nv50_cursor_hide;
-+ crtc->cursor.show = nv50_cursor_show;
++ nv_crtc->cursor.set_offset = nv50_cursor_set_offset;
++ nv_crtc->cursor.set_pos = nv50_cursor_set_pos;
++ nv_crtc->cursor.hide = nv50_cursor_hide;
++ nv_crtc->cursor.show = nv50_cursor_show;
+ return 0;
+}
+
+void
-+nv50_cursor_fini(struct nouveau_crtc *crtc)
++nv50_cursor_fini(struct nouveau_crtc *nv_crtc)
+{
-+ struct drm_device *dev = crtc->base.dev;
-+ int idx = crtc->index;
++ struct drm_device *dev = nv_crtc->base.dev;
++ int idx = nv_crtc->index;
+
+ NV_DEBUG(dev, "\n");
+
@@ -33535,10 +33558,10 @@ index 0000000..fb5838e
+
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
new file mode 100644
-index 0000000..8a1dd89
+index 0000000..dd4bff2
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
-@@ -0,0 +1,994 @@
+@@ -0,0 +1,998 @@
+/*
+ * Copyright (C) 2008 Maarten Maathuis.
+ * All Rights Reserved.
@@ -33737,27 +33760,31 @@ index 0000000..8a1dd89
+ * that enables things.
+ */
+ /* CRTC? */
-+ nv_wr32(dev, 0x00610190 + 0 * 0x10, nv_rd32(dev, 0x00616100 + 0 * 0x800));
-+ nv_wr32(dev, 0x00610190 + 1 * 0x10, nv_rd32(dev, 0x00616100 + 1 * 0x800));
-+ nv_wr32(dev, 0x00610194 + 0 * 0x10, nv_rd32(dev, 0x00616104 + 0 * 0x800));
-+ nv_wr32(dev, 0x00610194 + 1 * 0x10, nv_rd32(dev, 0x00616104 + 1 * 0x800));
-+ nv_wr32(dev, 0x00610198 + 0 * 0x10, nv_rd32(dev, 0x00616108 + 0 * 0x800));
-+ nv_wr32(dev, 0x00610198 + 1 * 0x10, nv_rd32(dev, 0x00616108 + 1 * 0x800));
-+ nv_wr32(dev, 0x0061019c + 0 * 0x10, nv_rd32(dev, 0x0061610c + 0 * 0x800));
-+ nv_wr32(dev, 0x0061019c + 1 * 0x10, nv_rd32(dev, 0x0061610c + 1 * 0x800));
++ for (i = 0; i < 2; i++) {
++ val = nv_rd32(dev, 0x00616100 + (i * 0x800));
++ nv_wr32(dev, 0x00610190 + (i * 0x10), val);
++ val = nv_rd32(dev, 0x00616104 + (i * 0x800));
++ nv_wr32(dev, 0x00610194 + (i * 0x10), val);
++ val = nv_rd32(dev, 0x00616108 + (i * 0x800));
++ nv_wr32(dev, 0x00610198 + (i * 0x10), val);
++ val = nv_rd32(dev, 0x0061610c + (i * 0x800));
++ nv_wr32(dev, 0x0061019c + (i * 0x10), val);
++ }
+ /* DAC */
-+ nv_wr32(dev, 0x006101d0 + 0 * 0x4, nv_rd32(dev, 0x0061a000 + 0 * 0x800));
-+ nv_wr32(dev, 0x006101d0 + 1 * 0x4, nv_rd32(dev, 0x0061a000 + 1 * 0x800));
-+ nv_wr32(dev, 0x006101d0 + 2 * 0x4, nv_rd32(dev, 0x0061a000 + 2 * 0x800));
++ for (i = 0; i < 3; i++) {
++ val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
++ nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
++ }
+ /* SOR */
-+ nv_wr32(dev, 0x006101e0 + 0 * 0x4, nv_rd32(dev, 0x0061c000 + 0 * 0x800));
-+ nv_wr32(dev, 0x006101e0 + 1 * 0x4, nv_rd32(dev, 0x0061c000 + 1 * 0x800));
-+ nv_wr32(dev, 0x006101e0 + 2 * 0x4, nv_rd32(dev, 0x0061c000 + 2 * 0x800));
-+ nv_wr32(dev, 0x006101e0 + 3 * 0x4, nv_rd32(dev, 0x0061c000 + 3 * 0x800));
++ for (i = 0; i < 4; i++) {
++ val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
++ nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
++ }
+ /* Something not yet in use, tv-out maybe. */
-+ nv_wr32(dev, 0x006101f0 + 0 * 0x4, nv_rd32(dev, 0x0061e000 + 0 * 0x800));
-+ nv_wr32(dev, 0x006101f0 + 1 * 0x4, nv_rd32(dev, 0x0061e000 + 1 * 0x800));
-+ nv_wr32(dev, 0x006101f0 + 2 * 0x4, nv_rd32(dev, 0x0061e000 + 2 * 0x800));
++ for (i = 0; i < 3; i++) {
++ val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
++ nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
++ }
+
+ for (i = 0; i < 3; i++) {
+ nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
@@ -35485,10 +35512,10 @@ index 0000000..77ae1aa
+
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
new file mode 100644
-index 0000000..eef3ebd
+index 0000000..7ff54c8
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
-@@ -0,0 +1,479 @@
+@@ -0,0 +1,470 @@
+/*
+ * Copyright (C) 2007 Ben Skeggs.
+ * All Rights Reserved.
@@ -35844,32 +35871,23 @@ index 0000000..eef3ebd
+ return nv50_graph_do_load_context(chan->dev, inst);
+}
+
-+static int
-+nv50_graph_do_save_context(struct drm_device *dev, uint32_t inst)
++int
++nv50_graph_unload_context(struct drm_device *dev)
+{
-+ uint32_t fifo = nv_rd32(dev, 0x400500);
++ uint32_t inst, fifo = nv_rd32(dev, 0x400500);
++
++ inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
++ if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
++ return 0;
++ inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
+
+ nv_wr32(dev, 0x400500, fifo & ~1);
+ nv_wr32(dev, 0x400784, inst);
+ nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
+ nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
+ nouveau_wait_for_idle(dev);
-+
+ nv_wr32(dev, 0x400500, fifo);
-+ return 0;
-+}
+
-+int
-+nv50_graph_unload_context(struct drm_device *dev)
-+{
-+ uint32_t inst;
-+ int ret;
-+
-+ inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
-+ if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
-+ return 0;
-+ inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
-+ ret = nv50_graph_do_save_context(dev, inst);
+ nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
+ return 0;
+}
@@ -63369,7 +63387,7 @@ index 0000000..e0a9c3f
+}
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
new file mode 100644
-index 0000000..019a1bf
+index 0000000..ef9dc02
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -0,0 +1,269 @@
@@ -63530,7 +63548,7 @@ index 0000000..019a1bf
+
+ switch (nv_encoder->dcb->type) {
+ case OUTPUT_TMDS:
-+ if (nv_encoder->dcb->tmdsconf.sor_link & 1) {
++ if (nv_encoder->dcb->sorconf.link & 1) {
+ if (adjusted_mode->clock < 165000)
+ mode_ctl = 0x0100;
+ else
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-12/kernel.spec,v
retrieving revision 1.1948
retrieving revision 1.1949
diff -u -p -r1.1948 -r1.1949
--- kernel.spec 4 Dec 2009 04:38:00 -0000 1.1948
+++ kernel.spec 4 Dec 2009 04:48:59 -0000 1.1949
@@ -2167,6 +2167,14 @@ fi
# and build.
%changelog
+* Fri Dec 04 2009 Ben Skeggs <bskeggs at redhat.com> 2.6.31.6-163
+- nouveau: reduce debug level of some warning messages (rh#543883)
+- nouveau: modesetting fixes on nva5/nva8
+- nouveau: suspend/resume fixes on nva5/nva8 (bios opcode 0x8d)
+- nouveau: cleanup chipset/arch handling, fail init on unknown chipsets
+- nouveau: fix failure to detect some outputs when dcb table is odd
+- nouveau: eliminate unnecessary cursor state changes on nv50
+
* Thu Dec 03 2009 Kyle McMartin <kyle at redhat.com> 2.6.31.6-162
- ipv4-fix-null-ptr-deref-in-ip_fragment.patch: null ptr deref
bug fix.
More information about the fedora-extras-commits
mailing list