rpms/kernel/devel drm-nouveau.patch, 1.9, 1.10 kernel.spec, 1.1345, 1.1346
Ben Skeggs
bskeggs at fedoraproject.org
Fri Feb 27 05:23:34 UTC 2009
Author: bskeggs
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv16741
Modified Files:
drm-nouveau.patch kernel.spec
Log Message:
* Fri Feb 27 2009 Ben Skeggs <bskeggs at redhat.com>
- Bring in nouveau update
- "getting there" nv50 modesetting rework
- nv50 stability improvements
- support for >512MiB VRAM on nv50
- nv40/nv50 backlight support
drm-nouveau.patch:
View full diff with command:
/usr/bin/cvs -f diff -kk -u -N -r 1.9 -r 1.10 drm-nouveau.patch
Index: drm-nouveau.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-nouveau.patch,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -r1.9 -r1.10
--- drm-nouveau.patch 27 Feb 2009 03:05:19 -0000 1.9
+++ drm-nouveau.patch 27 Feb 2009 05:23:02 -0000 1.10
@@ -1,8 +1,8 @@
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
-index 0d87bfc..433bd8b 100644
+index a74980b..36582ff 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
-@@ -134,3 +134,9 @@ config DRM_SAVAGE
+@@ -133,3 +133,18 @@ config DRM_SAVAGE
help
Choose this option if you have a Savage3D/4/SuperSavage/Pro/Twister
chipset. If M is selected the module will be called savage.
@@ -12,6 +12,15 @@
+ depends on DRM
+ help
+ Choose this option for open-source nVidia support.
++
++config DRM_NOUVEAU_KMS
++ bool "Enable modesetting on nouveau by default"
++ depends on DRM_NOUVEAU
++ help
++ Choose this option if you want kernel modesetting enabled by default,
++ and you have a new enough userspace to support this. Running old
++ userspaces with this enabled will cause pain.
++
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 9aba961..954fd51 100644
--- a/drivers/gpu/drm/Makefile
@@ -31,7 +40,7 @@
EXPORT_SYMBOL(drm_get_resource_len);
-static struct drm_map_list *drm_find_matching_map(struct drm_device *dev,
-- struct drm_local_map *map)
+- drm_local_map_t *map)
+struct drm_map_list *drm_find_matching_map(struct drm_device *dev,
+ drm_local_map_t *map)
{
@@ -45,11 +54,11 @@
static int drm_map_handle(struct drm_device *dev, struct drm_hash_item *hash,
unsigned long user_token, int hashed_handle)
-diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
+diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index c6ade45..969b372 100644
---- a/drivers/gpu/drm/drm_stub.c
-+++ b/drivers/gpu/drm/drm_stub.c
-@@ -327,11 +327,10 @@ void drm_put_dev(struct drm_device * dev)
+--- a/drivers/gpu/drm/drm_drv.c
++++ b/drivers/gpu/drm/drm_drv.c
+@@ -327,11 +327,10 @@ static void drm_cleanup(struct drm_device * dev)
dev->agp = NULL;
}
@@ -63,12 +72,25 @@
if (drm_core_check_feature(dev, DRIVER_MODESET))
drm_put_minor(&dev->control);
+diff --git a/drivers/gpu/drm/drm_fence.c b/drivers/gpu/drm/drm_fence.c
+index f1c386c..fd62fd9 100644
+--- a/drivers/gpu/drm/drm_fence.c
++++ b/drivers/gpu/drm/drm_fence.c
+@@ -369,7 +369,7 @@ int drm_fence_object_wait(struct drm_fence_object *fence,
+ struct drm_fence_manager *fm = &dev->fm;
+ struct drm_fence_class_manager *fc = &fm->fence_class[fence->fence_class];
+ int ret = 0;
+- unsigned long _end = 3 * DRM_HZ;
++ unsigned long _end = jiffies + 3 * DRM_HZ;
+
+ if (mask & ~fence->type) {
+ DRM_ERROR("Wait trying to extend fence type"
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
new file mode 100644
-index 0000000..d8a32e0
+index 0000000..d2cbeb3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/Makefile
-@@ -0,0 +1,24 @@
+@@ -0,0 +1,25 @@
+#
+# Makefile for the drm device driver. This driver provides support for the
+# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
@@ -78,7 +100,8 @@
+ nouveau_object.o nouveau_irq.o nouveau_notifier.o \
+ nouveau_swmthd.o nouveau_sgdma.o nouveau_dma.o \
+ nouveau_bo.o nouveau_fence.o nouveau_gem.o \
-+ nouveau_bios.o \
++ nouveau_bios.o nouveau_display.o nouveau_fbcon.o \
++ nouveau_backlight.o \
+ nv04_timer.o \
+ nv04_mc.o nv40_mc.o nv50_mc.o \
+ nv04_fb.o nv10_fb.o nv40_fb.o \
@@ -88,11 +111,173 @@
+ nv04_instmem.o nv50_instmem.o \
+ nv50_crtc.o nv50_dac.o nv50_sor.o nv50_connector.o \
+ nv50_lut.o nv50_cursor.o nv50_i2c.o nv50_display.o \
-+ nv50_fbcon.o nv50_fbcon_accel.o
++ nv50_fbcon.o
+
+nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
+
+obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o
+diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
+new file mode 100644
+index 0000000..3fc521e
+--- /dev/null
++++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
+@@ -0,0 +1,156 @@
++/*
++ * Copyright (C) 2009 Red Hat <mjg at redhat.com>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining
++ * a copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sublicense, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial
++ * portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
++ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
++ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
++ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++/*
++ * Authors:
++ * Matthew Garrett <mjg at redhat.com>
++ *
++ * Register locations derived from NVClock by Roderick Colenbrander
++ */
++
++#include <linux/backlight.h>
++
++#include "drmP.h"
++#include "nouveau_drv.h"
++#include "nouveau_drm.h"
++#include "nouveau_reg.h"
++
++static int nv40_get_intensity(struct backlight_device *bd)
++{
++ struct drm_device *dev = bl_get_data(bd);
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++ int val = (nv_rd32(NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK) >> 16;
++
++ return val;
++}
++
++static int nv40_set_intensity(struct backlight_device *bd)
++{
++ struct drm_device *dev = bl_get_data(bd);
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++ int val = bd->props.brightness;
++ int reg = nv_rd32(NV40_PMC_BACKLIGHT);
++
++ nv_wr32(NV40_PMC_BACKLIGHT,
++ (val << 16) | (reg & ~NV40_PMC_BACKLIGHT_MASK));
++
++ return 0;
++}
++
++static struct backlight_ops nv40_bl_ops = {
++ .options = BL_CORE_SUSPENDRESUME,
++ .get_brightness = nv40_get_intensity,
++ .update_status = nv40_set_intensity,
++};
++
++static int nv50_get_intensity(struct backlight_device *bd)
++{
++ struct drm_device *dev = bl_get_data(bd);
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++
++ return nv_rd32(NV50_PDISPLAY_BACKLIGHT);
++}
++
++static int nv50_set_intensity(struct backlight_device *bd)
++{
++ struct drm_device *dev = bl_get_data(bd);
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++ int val = bd->props.brightness;
++
++ nv_wr32(NV50_PDISPLAY_BACKLIGHT, val | NV50_PDISPLAY_BACKLIGHT_ENABLE);
++
++ return 0;
++}
++
[...51492 lines suppressed...]
++ 0x70000 | ((mode->clock > limit) ? 0x101 : 0));
+
+ return 0;
+}
+
-+static int nv50_sor_set_power_mode(struct nv50_output *output, int mode)
++static void nv50_sor_dpms(struct drm_encoder *drm_encoder, int mode)
+{
-+ struct drm_nouveau_private *dev_priv = output->base.dev->dev_private;
++ struct drm_device *dev = drm_encoder->dev;
++ struct drm_nouveau_private *dev_priv = dev->dev_private;
++ struct nouveau_encoder *encoder = to_nouveau_encoder(drm_encoder);
+ uint32_t val;
-+ int or = output->or;
++ int or = encoder->or;
+
-+ DRM_DEBUG("or %d\n", output->or);
++ DRM_DEBUG("or %d\n", encoder->or);
+
+ /* wait for it to be done */
-+ while (nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
++ if (!nv_wait(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or),
++ NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING, 0)) {
++ DRM_ERROR("timeout: SOR_DPMS_CTRL_PENDING(%d) == 0\n", or);
++ DRM_ERROR("SOR_DPMS_CTRL(%d) = 0x%08x\n", or,
++ nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)));
++ }
+
+ val = nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or));
+
@@ -35883,24 +42608,98 @@
+ else
+ val &= ~NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON;
+
-+ nv_wr32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
++ nv_wr32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or), val |
++ NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
++}
+
-+ return 0;
++static void nv50_sor_save(struct drm_encoder *drm_encoder)
++{
++ DRM_ERROR("!!\n");
++}
++
++static void nv50_sor_restore(struct drm_encoder *drm_encoder)
++{
++ DRM_ERROR("!!\n");
++}
++
++static struct nouveau_connector *
++nouveau_encoder_connector_get(struct nouveau_encoder *encoder)
++{
++ struct drm_device *dev = encoder->base.dev;
++ struct drm_connector *drm_connector;
++
++ list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) {
++ if (drm_connector->encoder == &encoder->base)
++ return to_nouveau_connector(drm_connector);
++ }
++
++ return NULL;
++}
++
++static bool nv50_sor_mode_fixup(struct drm_encoder *drm_encoder,
++ struct drm_display_mode *mode,
++ struct drm_display_mode *adjusted_mode)
++{
++ struct nouveau_encoder *encoder = to_nouveau_encoder(drm_encoder);
++ struct nouveau_connector *connector;
++
++ connector = nouveau_encoder_connector_get(encoder);
++ if (!connector)
++ return false;
++
++ if ((connector->scaling_mode != DRM_MODE_SCALE_NON_GPU &&
++ connector->scaling_mode != DRM_MODE_SCALE_NO_SCALE) &&
++ connector->native_mode)
++ *adjusted_mode = *connector->native_mode;
++
++ return true;
+}
+
++static void nv50_sor_prepare(struct drm_encoder *drm_encoder)
++{
++ struct nouveau_encoder *encoder = to_nouveau_encoder(drm_encoder);
++
++ nv50_sor_dpms(drm_encoder, DRM_MODE_DPMS_OFF);
++ nv50_sor_disconnect(encoder);
++}
++
++static void nv50_sor_commit(struct drm_encoder *drm_encoder)
++{
++ nv50_sor_dpms(drm_encoder, DRM_MODE_DPMS_ON);
++}
++
++static void nv50_sor_mode_set(struct drm_encoder *drm_encoder,
++ struct drm_display_mode *mode,
++ struct drm_display_mode *adjusted_mode)
++{
++ struct nouveau_encoder *encoder = to_nouveau_encoder(drm_encoder);
++
++ nv50_sor_execute_mode(encoder, adjusted_mode);
++}
++
++static const struct drm_encoder_helper_funcs nv50_sor_helper_funcs = {
++ .dpms = nv50_sor_dpms,
++ .save = nv50_sor_save,
++ .restore = nv50_sor_restore,
++ .mode_fixup = nv50_sor_mode_fixup,
++ .prepare = nv50_sor_prepare,
++ .commit = nv50_sor_commit,
++ .mode_set = nv50_sor_mode_set,
++ .detect = NULL
++};
++
+static void nv50_sor_destroy(struct drm_encoder *drm_encoder)
+{
-+ struct nv50_output *output = to_nv50_output(drm_encoder);
++ struct nouveau_encoder *encoder = to_nouveau_encoder(drm_encoder);
+
+ DRM_DEBUG("\n");
+
+ if (!drm_encoder)
+ return;
+
-+ drm_encoder_cleanup(&output->base);
++ drm_encoder_cleanup(&encoder->base);
+
-+ kfree(output->native_mode);
-+ kfree(output);
++ kfree(encoder);
+}
+
+static const struct drm_encoder_funcs nv50_sor_encoder_funcs = {
@@ -35910,7 +42709,7 @@
+int nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
-+ struct nv50_output *output = NULL;
++ struct nouveau_encoder *encoder = NULL;
+ int type;
+
+ DRM_DEBUG("\n");
@@ -35928,35 +42727,26 @@
+ return -EINVAL;
+ }
+
-+ output = kzalloc(sizeof(*output), GFP_KERNEL);
-+ if (!output)
-+ return -ENOMEM;
-+
-+ output->native_mode = kzalloc(sizeof(*output->native_mode), GFP_KERNEL);
-+ if (!output->native_mode) {
-+ kfree(output);
++ encoder = kzalloc(sizeof(*encoder), GFP_KERNEL);
++ if (!encoder)
+ return -ENOMEM;
-+ }
+
-+ output->dcb_entry = entry;
-+ output->or = ffs(entry->or) - 1;
++ encoder->dcb_entry = entry;
++ encoder->or = ffs(entry->or) - 1;
+
+ /* Set function pointers. */
-+ output->validate_mode = nv50_sor_validate_mode;
-+ output->execute_mode = nv50_sor_execute_mode;
-+ output->set_clock_mode = nv50_sor_set_clock_mode;
-+ output->set_power_mode = nv50_sor_set_power_mode;
-+ output->detect = NULL;
++ encoder->set_clock_mode = nv50_sor_set_clock_mode;
+
-+ drm_encoder_init(dev, &output->base, &nv50_sor_encoder_funcs, type);
++ drm_encoder_init(dev, &encoder->base, &nv50_sor_encoder_funcs, type);
++ drm_encoder_helper_add(&encoder->base, &nv50_sor_helper_funcs);
+
+ /* I've never seen possible crtc's restricted. */
-+ output->base.possible_crtcs = 3;
-+ output->base.possible_clones = 0;
++ encoder->base.possible_crtcs = 3;
++ encoder->base.possible_clones = 0;
+
+ /* Some default state, unknown what it precisely means. */
-+ if (output->base.encoder_type == DRM_MODE_ENCODER_TMDS) {
-+ int or = output->or;
++ if (encoder->base.encoder_type == DRM_MODE_ENCODER_TMDS) {
++ int or = encoder->or;
+
+ nv_wr32(NV50_PDISPLAY_SOR_REGS_UNK_00C(or), 0x03010700);
+ nv_wr32(NV50_PDISPLAY_SOR_REGS_UNK_010(or), 0x0000152f);
@@ -35976,7 +42766,7 @@
unifdef-y += via_drm.h
+unifdef-y += nouveau_drm.h
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
-index 67cadab..4e2c0c8 100644
+index c963f25..7c6d668 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1206,6 +1206,8 @@ extern void drm_idlelock_release(struct drm_lock_data *lock_data);
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1345
retrieving revision 1.1346
diff -u -r1.1345 -r1.1346
--- kernel.spec 27 Feb 2009 03:12:57 -0000 1.1345
+++ kernel.spec 27 Feb 2009 05:23:03 -0000 1.1346
@@ -1788,6 +1788,13 @@
# and build.
%changelog
+* Fri Feb 27 2009 Ben Skeggs <bskeggs at redhat.com>
+- Bring in nouveau update
+ - "getting there" nv50 modesetting rework
+ - nv50 stability improvements
+ - support for >512MiB VRAM on nv50
+ - nv40/nv50 backlight support
+
* Fri Feb 27 2009 Dave Airlie <airlied at redhat.com>
- agp-set_memory_ucwb.patch - enable GEM/KMS on PAE hopefully
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