rpms/msp430-binutils/devel 01-binutils-2.19.patch, NONE, 1.1 import.log, NONE, 1.1 msp430-binutils.spec, NONE, 1.1 .cvsignore, 1.1, 1.2 sources, 1.1, 1.2
Robert Spanton
rspanton at fedoraproject.org
Mon Jan 26 12:52:40 UTC 2009
Author: rspanton
Update of /cvs/pkgs/rpms/msp430-binutils/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv18823/devel
Modified Files:
.cvsignore sources
Added Files:
01-binutils-2.19.patch import.log msp430-binutils.spec
Log Message:
* Mon 26 Jan 2009 Rob Spanton rspanton at zepler.net 2.19-2
- Import SRPM into devel branch
01-binutils-2.19.patch:
--- NEW FILE 01-binutils-2.19.patch ---
diff -rNU 5 binutils-2.19-orig/bfd/archures.c binutils-2.19-msp/bfd/archures.c
--- binutils-2.19-orig/bfd/archures.c 2008-08-09 15:35:12.000000000 +1000
+++ binutils-2.19-msp/bfd/archures.c 2009-01-02 15:28:42.000000000 +1100
@@ -383,18 +383,28 @@
.#define bfd_mach_msp12 12
.#define bfd_mach_msp13 13
.#define bfd_mach_msp14 14
.#define bfd_mach_msp15 15
.#define bfd_mach_msp16 16
+.#define bfd_mach_msp20 20
.#define bfd_mach_msp21 21
+.#define bfd_mach_msp22 22
+.#define bfd_mach_msp23 23
+.#define bfd_mach_msp24 24
+.#define bfd_mach_msp241 241
+.#define bfd_mach_msp26 26
.#define bfd_mach_msp31 31
.#define bfd_mach_msp32 32
.#define bfd_mach_msp33 33
.#define bfd_mach_msp41 41
.#define bfd_mach_msp42 42
.#define bfd_mach_msp43 43
.#define bfd_mach_msp44 44
+.#define bfd_mach_msp46 46
+.#define bfd_mach_msp47 47
+.#define bfd_mach_msp471 471
+.#define bfd_mach_msp54 54
. bfd_arch_xc16x, {* Infineon's XC16X Series. *}
.#define bfd_mach_xc16x 1
.#define bfd_mach_xc16xl 2
.#define bfd_mach_xc16xs 3
. bfd_arch_xtensa, {* Tensilica's Xtensa cores. *}
diff -rNU 5 binutils-2.19-orig/bfd/bfd-in2.h binutils-2.19-msp/bfd/bfd-in2.h
--- binutils-2.19-orig/bfd/bfd-in2.h 2008-08-21 09:28:57.000000000 +1000
+++ binutils-2.19-msp/bfd/bfd-in2.h 2009-01-02 15:28:42.000000000 +1100
@@ -2005,18 +2005,28 @@
#define bfd_mach_msp12 12
#define bfd_mach_msp13 13
#define bfd_mach_msp14 14
#define bfd_mach_msp15 15
#define bfd_mach_msp16 16
+#define bfd_mach_msp20 20
#define bfd_mach_msp21 21
+#define bfd_mach_msp22 22
+#define bfd_mach_msp23 23
+#define bfd_mach_msp24 24
+#define bfd_mach_msp241 241
+#define bfd_mach_msp26 26
#define bfd_mach_msp31 31
#define bfd_mach_msp32 32
#define bfd_mach_msp33 33
#define bfd_mach_msp41 41
#define bfd_mach_msp42 42
#define bfd_mach_msp43 43
#define bfd_mach_msp44 44
+#define bfd_mach_msp46 46
+#define bfd_mach_msp47 47
+#define bfd_mach_msp471 471
+#define bfd_mach_msp54 54
bfd_arch_xc16x, /* Infineon's XC16X Series. */
#define bfd_mach_xc16x 1
#define bfd_mach_xc16xl 2
#define bfd_mach_xc16xs 3
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
@@ -4282,10 +4292,29 @@
BFD_RELOC_MSP430_16,
BFD_RELOC_MSP430_16_PCREL_BYTE,
BFD_RELOC_MSP430_16_BYTE,
BFD_RELOC_MSP430_2X_PCREL,
BFD_RELOC_MSP430_RL_PCREL,
+ BFD_RELOC_MSP430X_SRC_BYTE,
+ BFD_RELOC_MSP430X_SRC,
+ BFD_RELOC_MSP430X_DST_BYTE,
+ BFD_RELOC_MSP430X_DST,
+ BFD_RELOC_MSP430X_DST_2ND_BYTE,
+ BFD_RELOC_MSP430X_DST_2ND,
+ BFD_RELOC_MSP430X_PCREL_SRC_BYTE,
+ BFD_RELOC_MSP430X_PCREL_SRC,
+ BFD_RELOC_MSP430X_PCREL_DST_BYTE,
+ BFD_RELOC_MSP430X_PCREL_DST,
+ BFD_RELOC_MSP430X_PCREL_DST_2ND,
+ BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE,
+ BFD_RELOC_MSP430X_S_BYTE,
+ BFD_RELOC_MSP430X_S,
+ BFD_RELOC_MSP430X_D_BYTE,
+ BFD_RELOC_MSP430X_D,
+ BFD_RELOC_MSP430X_PCREL_D,
+ BFD_RELOC_MSP430X_INDXD,
+ BFD_RELOC_MSP430X_PCREL_INDXD,
/* IQ2000 Relocations. */
BFD_RELOC_IQ2000_OFFSET_16,
BFD_RELOC_IQ2000_OFFSET_21,
BFD_RELOC_IQ2000_UHI16,
diff -rNU 5 binutils-2.19-orig/bfd/cpu-msp430.c binutils-2.19-msp/bfd/cpu-msp430.c
--- binutils-2.19-orig/bfd/cpu-msp430.c 2007-07-04 00:26:40.000000000 +1000
+++ binutils-2.19-msp/bfd/cpu-msp430.c 2009-01-02 15:28:42.000000000 +1100
@@ -63,33 +63,64 @@
N (16, bfd_mach_msp15, "msp:15", FALSE, & arch_info_struct[6]),
/* msp430x16x. */
N (16, bfd_mach_msp16, "msp:16", FALSE, & arch_info_struct[7]),
+ /* msp430x20x. */
+ N (16, bfd_mach_msp20, "msp:20", FALSE, & arch_info_struct[8]),
+
/* msp430x21x. */
- N (16, bfd_mach_msp21, "msp:21", FALSE, & arch_info_struct[8]),
+ N (16, bfd_mach_msp21, "msp:21", FALSE, & arch_info_struct[9]),
+
+ /* msp430x22x. */
+ N (16, bfd_mach_msp22, "msp:22", FALSE, & arch_info_struct[10]),
+
+ /* msp430x23x0. */
+ N (16, bfd_mach_msp23, "msp:23", FALSE, & arch_info_struct[11]),
+
+ /* msp430x24x including msp430x2410 */
+ N (16, bfd_mach_msp24, "msp:24", FALSE, & arch_info_struct[12]),
+
+ /* msp430x241x except msp430x2410 (extended address range) */
+ N (20, bfd_mach_msp241, "msp:241", FALSE, & arch_info_struct[13]),
+
+ /* msp430x26x. */
+ N (20, bfd_mach_msp26, "msp:26", FALSE, & arch_info_struct[14]),
/* msp430x31x. */
- N (16, bfd_mach_msp31, "msp:31", FALSE, & arch_info_struct[9]),
+ N (16, bfd_mach_msp31, "msp:31", FALSE, & arch_info_struct[15]),
/* msp430x32x. */
- N (16, bfd_mach_msp32, "msp:32", FALSE, & arch_info_struct[10]),
+ N (16, bfd_mach_msp32, "msp:32", FALSE, & arch_info_struct[16]),
/* msp430x33x. */
- N (16, bfd_mach_msp33, "msp:33", FALSE, & arch_info_struct[11]),
+ N (16, bfd_mach_msp33, "msp:33", FALSE, & arch_info_struct[17]),
/* msp430x41x. */
- N (16, bfd_mach_msp41, "msp:41", FALSE, & arch_info_struct[12]),
+ N (16, bfd_mach_msp41, "msp:41", FALSE, & arch_info_struct[18]),
/* msp430x42x. */
- N (16, bfd_mach_msp42, "msp:42", FALSE, & arch_info_struct[13]),
+ N (16, bfd_mach_msp42, "msp:42", FALSE, & arch_info_struct[19]),
/* msp430x43x. */
- N (16, bfd_mach_msp43, "msp:43", FALSE, & arch_info_struct[14]),
+ N (16, bfd_mach_msp43, "msp:43", FALSE, & arch_info_struct[20]),
/* msp430x44x. */
- N (16, bfd_mach_msp43, "msp:44", FALSE, NULL)
+ N (16, bfd_mach_msp44, "msp:44", FALSE, & arch_info_struct[21]),
+
+ /* msp430x46xx. */
+ N (20, bfd_mach_msp46, "msp:46", FALSE, & arch_info_struct[22]),
+
+ /* msp430x47x3, 47x4. */
+ N (16, bfd_mach_msp47, "msp:47", FALSE, & arch_info_struct[23]),
+
+ /* msp430x471x6, 471x7. */
+ N (20, bfd_mach_msp471, "msp:471", FALSE, & arch_info_struct[24]),
+
+ /* msp430x54xx. */
+ N (20, bfd_mach_msp54, "msp:54", FALSE, NULL)
+
};
const bfd_arch_info_type bfd_msp430_arch =
N (16, bfd_mach_msp14, "msp:14", TRUE, & arch_info_struct[0]);
diff -rNU 5 binutils-2.19-orig/bfd/doc/archures.texi binutils-2.19-msp/bfd/doc/archures.texi
--- binutils-2.19-orig/bfd/doc/archures.texi 2008-09-10 17:50:16.000000000 +1000
+++ binutils-2.19-msp/bfd/doc/archures.texi 2009-01-02 15:28:42.000000000 +1100
@@ -348,18 +348,24 @@
#define bfd_mach_msp12 12
#define bfd_mach_msp13 13
#define bfd_mach_msp14 14
#define bfd_mach_msp15 15
#define bfd_mach_msp16 16
+#define bfd_mach_msp20 20
#define bfd_mach_msp21 21
+#define bfd_mach_msp22 22
+#define bfd_mach_msp24 24
+#define bfd_mach_msp241 241
+#define bfd_mach_msp26 26
#define bfd_mach_msp31 31
#define bfd_mach_msp32 32
#define bfd_mach_msp33 33
#define bfd_mach_msp41 41
#define bfd_mach_msp42 42
#define bfd_mach_msp43 43
#define bfd_mach_msp44 44
+#define bfd_mach_msp46 46
bfd_arch_xc16x, /* Infineon's XC16X Series. */
#define bfd_mach_xc16x 1
#define bfd_mach_xc16xl 2
#define bfd_mach_xc16xs 3
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
@@ -605,6 +611,5 @@
[...6939 lines suppressed...]
+ {"", "", ".b", ".a" };
+
insn = msp430dis_opcode (addr, info);
- sprintf (dinfo, "0x%04x", insn);
- if (((int) addr & 0xffff) > 0xffdf)
+ if (info->mach == 241 || info->mach == 26 || info->mach == 46 || info->mach == 471)
+ {
+ core = CORE_430X;
+ }
+ else if (info->mach == 54)
+ {
+ core = CORE_430X2;
+ }
+
+ if ( (core == CORE_430 && ((int) addr & 0xffff) >= 0xffe0)
+ || ( core == CORE_430X && (((int) addr & 0xfffff) >= 0xffc0) && ((int) addr & 0xfffff) < 0x10000)
+ || ( core == CORE_430X2 && (((int) addr & 0xfffff) >= 0xff80) && ((int) addr & 0xfffff) < 0x10000)
+ )
{
(*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn);
return 2;
}
+ if (core > CORE_430 && ((insn & 0xf800) == 0x1800)) // Extended instruction
+ insn |= msp430dis_opcode(addr + 2, info) << 16;
+
*comm1 = 0;
*comm2 = 0;
for (opcode = msp430_opcodes; opcode->name; opcode++)
{
if ((insn & opcode->bin_mask) == opcode->bin_opcode
- && opcode->bin_opcode != 0x9300)
+// && opcode->bin_opcode != 0x9300 // was disasm tst instruction as cmp #0, dst?
+ )
{
*op1 = 0;
*op2 = 0;
*comm1 = 0;
*comm2 = 0;
- /* r0 as destination. Ad should be zero. */
- if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0
- && (0x0080 & insn) == 0)
+ /* unsupported instruction */
+ if(opcode_format(opcode) >= FMT_X && core < CORE_430X)
+ break;
+
+ /* r0 as destination. Ad should be zero. Rdst=0 and Ad=0 are encoded in opcode & opcode_mask */
+ if (opcode_format(opcode) == FMT_EMULATED && opcode_variant(opcode) == V_BR)
{
cmd_len =
- msp430_branchinstr (info, opcode, addr, insn, op1, comm1,
- &cycles);
+ msp430_branchinstr (info, opcode, addr, insn, op1, comm1);
if (cmd_len)
break;
}
-
- switch (opcode->insn_opnumb)
- {
- case 0:
- cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);
- break;
- case 2:
- cmd_len =
- msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
- comm1, comm2, &cycles);
- if (insn & BYTE_OPERATION)
- bc = ".b";
- break;
- case 1:
- cmd_len =
- msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
- &cycles);
- if (insn & BYTE_OPERATION && opcode->fmt != 3)
- bc = ".b";
- break;
- default:
- break;
- }
+ if(opcode_format(opcode) < FMT_X)
+ switch (opcode->insn_opnumb)
+ {
+ case 0:
+ cmd_len = msp430_nooperands (opcode, addr, insn, comm1);
+ break;
+ case 2:
+ cmd_len =
+ msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
+ comm1, comm2);
+ if (insn & BYTE_OPERATION)
+ op_width = BYTE_OP;
+ break;
+ case 1:
+ cmd_len =
+ msp430_singleoperand (info, opcode, addr, insn, op1, comm1);
+ if (insn & BYTE_OPERATION && opcode_format(opcode) != FMT_JUMP)
+ op_width = BYTE_OP;
+ break;
+ default:
+ break;
+ }
+ else // 430x instruction
+ switch(opcode_format(opcode))
+ {
+ case FMT_X_SINGLE_OPERAND:
+ if( opcode_variant(opcode) == V_SWPSXT // swpbx, sxtx
+ && (insn & (NON_ADDR_OPERATION | BYTE_OPERATION_X)) == 0) // .a, special case
+ insn ^= BYTE_OPERATION_X; // make A/L, B/W as ordinary
+
+ op_width = msp430x_opwidth(insn);
+
+ if( opcode_variant(opcode) == V_SWPSXT && op_width == BYTE_OP) // swpbx, sxtx
+ strcpy (comm1, _("Illegal A/L, B/W bits setting"));
+
+ cmd_len = msp430x_singleoperand (info, opcode, addr, insn, op1, comm1,
+ &repeats);
+ break;
+ case FMT_X_EXCEPTION:
+ cmd_len = msp430x_exception (info, opcode, addr, insn, op1, op2,
+ comm1, comm2, &op_width);
+ break;
+ case FMT_X_DOUBLE_OPERAND:
+ cmd_len = msp430x_doubleoperand (info, opcode, addr, insn, op1, op2,
+ comm1, comm2, &op_width, &repeats);
+ break;
+ case FMT_X_EMULATED:
+ cmd_len = msp430x_emulated (info, opcode, addr, insn, op1,
+ comm1, &op_width, &repeats);
+ break;
+
+ case FMT_X_ADDRESS:
+ cmd_len = msp430x_address (info, addr, insn, op1, op2,
+ comm1, comm2);
+ break;
+ default:
+ break;
+ }
}
if (cmd_len)
break;
}
- dinfo[5] = 0;
-
if (cmd_len < 1)
{
/* Unknown opcode, or invalid combination of operands. */
- (*prin) (stream, ".word 0x%04x; ????", PS (insn));
+ (*prin) (stream, ".word 0x%04x; ????\t%s%s", PS (insn), comm1, comm2);
return 2;
}
- (*prin) (stream, "%s%s", opcode->name, bc);
+
+ if (repeats)
+ {
+ if (repeats < 0)
+ (*prin) (stream, ".rpt\t#%d\n\t\t\t\t", 0 - repeats);
+ else
+ (*prin) (stream, ".rpt\tr%d\n\t\t\t\t", repeats);
+ }
+
+ (*prin) (stream, "%s%s", opcode->name, width_modifier[op_width]);
if (*op1)
(*prin) (stream, "\t%s", op1);
if (*op2)
(*prin) (stream, ",");
@@ -763,25 +822,13 @@
if (strlen (op2) < 8)
(*prin) (stream, "\t");
if (*comm1 || *comm2)
(*prin) (stream, ";");
- else if (cycles)
- {
- if (*op2)
- (*prin) (stream, ";");
- else
- {
- if (strlen (op1) < 7)
- (*prin) (stream, ";");
- else
- (*prin) (stream, "\t;");
- }
- }
if (*comm1)
(*prin) (stream, "%s", comm1);
if (*comm1 && *comm2)
- (*prin) (stream, ",");
+ (*prin) (stream, ", ");
if (*comm2)
- (*prin) (stream, " %s", comm2);
+ (*prin) (stream, "%s", comm2);
return cmd_len;
}
--- NEW FILE import.log ---
msp430-binutils-2_19-2_fc10:HEAD:msp430-binutils-2.19-2.fc10.src.rpm:1232974270
--- NEW FILE msp430-binutils.spec ---
%define target msp430
Name: %{target}-binutils
Version: 2.19
Release: 2%{?dist}
Summary: Cross Compiling GNU binutils targeted at %{target}
Group: Development/Tools
License: GPLv2+
URL: http://www.gnu.org/software/binutils/
Source0: http://ftp.gnu.org/gnu/binutils/binutils-%{version}.tar.bz2
# I have attempted to get this patch upstream.
# See mailing list post: http://article.gmane.org/gmane.comp.gnu.binutils/39694
Patch0: 01-binutils-2.19.patch
BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n)
BuildRequires: texinfo
%description
This is a Cross Compiling version of GNU binutils, which can be used to
assemble and link binaries for the %{target} platform, instead of for the
native %{_arch} platform.
%prep
%setup -q -c -n msp430-binutils
pushd binutils-%{version}
%patch0 -p1
popd
%build
mkdir -p build
cd build
CFLAGS="$RPM_OPT_FLAGS" ../binutils-%{version}/configure --prefix=%{_prefix} \
--libdir=%{_libdir} --mandir=%{_mandir} --infodir=%{_infodir} \
--target=%{target} --disable-werror --disable-nls
make %{?_smp_mflags}
%install
cd build
rm -rf $RPM_BUILD_ROOT
make install DESTDIR=$RPM_BUILD_ROOT
# these are for win targets only
rm -f $RPM_BUILD_ROOT%{_mandir}/man1/%{target}-{dlltool,nlmconv,windres,windmc}.1
# we don't want these as this is a cross-compiler
rm -rf $RPM_BUILD_ROOT%{_infodir}
rm -f $RPM_BUILD_ROOT%{_libdir}/libiberty.a
%clean
rm -rf $RPM_BUILD_ROOT
%files
%defattr(-,root,root,-)
%{_prefix}/%{target}
%{_bindir}/%{target}-*
%{_mandir}/man1/%{target}-*.1.gz
%changelog
* Thu Jan 15 2009 Rob Spanton rspanton at zepler.net 2.19-2
- Add comment about getting patch upstream.
* Tue Jan 13 2009 Rob Spanton rspanton at zepler.net 2.19-1
- Bump up to binutils 2.19.
- Use the bundled 2.19 patch from mspgcc packaging.
- Don't install man pages about windows utilities.
- Reduce a number of lines from the files section to just one line.
- Don't delete the debug information.
* Thu Aug 28 2007 Rob Spanton rspanton at zepler.net 2.18-1
- Initial release
Index: .cvsignore
===================================================================
RCS file: /cvs/pkgs/rpms/msp430-binutils/devel/.cvsignore,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -r1.1 -r1.2
--- .cvsignore 23 Jan 2009 23:32:06 -0000 1.1
+++ .cvsignore 26 Jan 2009 12:52:10 -0000 1.2
@@ -0,0 +1 @@
+binutils-2.19.tar.bz2
Index: sources
===================================================================
RCS file: /cvs/pkgs/rpms/msp430-binutils/devel/sources,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -r1.1 -r1.2
--- sources 23 Jan 2009 23:32:06 -0000 1.1
+++ sources 26 Jan 2009 12:52:10 -0000 1.2
@@ -0,0 +1 @@
+17a52219dee5a76c1a9d9b0bfd337d66 binutils-2.19.tar.bz2
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