rpms/gcc/devel gcc44-atom.patch, NONE, 1.1 gcc44-pr39226.patch, NONE, 1.1 gcc44-pr39358.patch, NONE, 1.1 .cvsignore, 1.257, 1.258 gcc.spec, 1.24, 1.25 sources, 1.260, 1.261 gcc44-pr39240.patch, 1.1, NONE
Jakub Jelinek
jakub at fedoraproject.org
Wed Mar 4 13:55:39 UTC 2009
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Author: jakub
Update of /cvs/pkgs/rpms/gcc/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv19687
Modified Files:
.cvsignore gcc.spec sources
Added Files:
gcc44-atom.patch gcc44-pr39226.patch gcc44-pr39358.patch
Removed Files:
gcc44-pr39240.patch
Log Message:
4.4.0-0.22
gcc44-atom.patch:
--- NEW FILE gcc44-atom.patch ---
2009-02-05 Joey Ye <joey.ye at intel.com>
Xuepeng Guo <xuepeng.guo at intel.com>
H.J. Lu <hongjiu.lu at intel.com>
Atom pipeline model, tuning and insn selection.
* rtlanal.c (reg_mentioned_by_mem_p_1): New function.
(reg_mentioned_by_mem_p): New function.
(reg_dep_by_addr_p): New function.
* rtl.h (reg_mentioned_by_mem_p): Declare new function.
(reg_dep_by_addr_p): Likewise.
* config.gcc (atom): Add atom config options and target.
* config/i386/i386.h (TARGET_ATOM): New target macro.
(X86_TUNE_OPT_AGU): New tuning flag.
(TARGET_OPT_AGU): New target option.
(TARGET_CPU_DEFAULT_atom): New CPU default.
(PROCESSOR_ATOM): New processor.
* config/i386/i386-c.c (ix86_target_macros_internal): New case
PROCESSOR_ATOM.
(ix86_target_macros_internal): Likewise.
* config/i386/i386-protos.h (ix86_lea_for_add_ok): Declare new
function.
(ix86_dep_by_shift_count): Likewise.
(ix86_agi_dependent): Likewise.
* config/i386/i386.c (atom_cost): New cost.
(m_ATOM): New macro flag.
(initial_ix86_tune_fe): Set m_ATOM.
(x86_accumulate_outgoing_args): Likewise.
(x86_arch_always_fancy_math_387): Likewise.
(processor_target): Add Atom cost.
(cpu_names): Add Atom cpu name.
(override_options): Set Atom ISA.
(LEA_SEARCH_THRESHOLD): New macro.
(distance_non_agu_define): New function.
(distance_agu_use): Likewise.
(ix86_lea_for_add_ok): Likewise.
(ix86_dep_by_shift_count): Likewise.
(ix86_agi_dependent): Make it global.
(ix86_issue_rate): New case PROCESSOR_ATOM.
(ix86_adjust_cost): Likewise.
* config/i386/i386.md (cpu): Add new value "atom".
(atom.md): Include atom.md.
(use_carry, movu): New attr.
(adddi3_carry_rex64): Set attr "use_carry".
(addqi3_carry): Likewise.
(addhi3_carry): Likewise.
(addsi3_carry): Likewise.
(*addsi3_carry_zext): Likewise.
(subdi3_carry_rex64): Likewise.
(subqi3_carry): Likewise.
(subhi3_carry): Likewise.
(subsi3_carry): Likewise.
(x86_movdicc_0_m1_rex64): Likewise.
(*x86_movdicc_0_m1_se): Likewise.
(x86_movsicc_0_m1): Likewise.
(*x86_movsicc_0_m1_se): Likewise.
(*adddi_1_rex64): Emit add insn as much as possible.
(*addsi_1): Likewise.
(return_internal): Set atom_unit.
(return_internal_long): Likewise.
(return_pop_internal): Likewise.
(*rcpsf2_sse): Set atom_sse_attr attr.
(*qrt<mode>2_sse): Likewise.
(*prefetch_sse): Likewise.
* config/i386/sse.md (cpu): Set attr "atom_sse_attr".
(*prefetch_sse_rex): Likewise.
(sse_rcpv4sf2): Likewise.
(sse_vmrcpv4sf2): Likewise.
(sse_sqrtv4sf2): Likewise.
(<sse>_vmsqrt<mode>2): Likewise.
(sse_ldmxcsr): Likewise.
(sse_stmxcsr): Likewise.
(*sse_sfence): Likewise.
(sse2_clflush): Likewise.
(*sse2_mfence): Likewise.
(*sse2_lfence): Likewise.
(avx_movup<avxmodesuffixf2c><avxmodesuffix>): Set attr "movu".
(<sse>_movup<ssemodesuffixf2c>): Likewise.
(avx_movdqu<avxmodesuffix>): Likewise.
(avx_lddqu<avxmodesuffix>): Likewise.
(sse2_movntv2di): Change attr "type" to "ssemov".
(sse2_movntsi): Likewise.
(rsqrtv8sf2): Change attr "type" to "sseadd".
(sse3_addsubv2df3): Set attr "atom_unit".
(sse3_h<plusminus_insn>v4sf3): Likewise.
(*sse2_pmaddwd): Likewise.
(*vec_extractv2di_1_rex64): Likewise.
(*vec_extractv2di_1_avx): Likewise.
(sse2_psadbw): Likewise.
(ssse3_phaddwv8hi3): Likewise.
(ssse3_phaddwv4hi3): Likewise.
(ssse3_phadddv4si3): Likewise.
(ssse3_phadddv2si3): Likewise.
(ssse3_phaddswv8hi3): Likewise.
(ssse3_phaddswv4hi3): Likewise.
(ssse3_phsubwv8hi3): Likewise.
(ssse3_phsubwv4hi3): Likewise.
(ssse3_phsubdv4si3): Likewise.
(ssse3_phsubdv2si3): Likewise.
(ssse3_phsubswv8hi3): Likewise.
(ssse3_phsubswv4hi3): Likewise.
(ssse3_pmaddubsw128): Likewise.
(sse3_pmaddubsw: Likewise.
(ssse3_palignrti): Likewise.
(ssse3_palignrdi): Likewise.
* config/i386/atom.md: New.
2009-02-05 H.J. Lu <hongjiu.lu at intel.com>
* config/i386/i386.c (ix86_agi_dependent): Remove the third
argument. Swap the first 2 arguments.
(ix86_adjust_cost): Updated.
2009-01-30 Vladimir Makarov <vmakarov at redhat.com>
* genautomata.c: Add a new year to the copyright. Add a new
reference.
(struct insn_reserv_decl): Add comments for member bypass_list.
(find_bypass): Remove.
(insert_bypass): New.
(process_decls): Use insert_bypass.
(output_internal_insn_latency_func): Output all bypasses with the
same input insn in one switch case.
* rtl.def (define_bypass): Describe bypass choice.
* doc/md.texi (define_bypass): Ditto.
--- gcc/doc/md.texi (.../trunk) (revision 144460)
+++ gcc/doc/md.texi (.../branches/ix86/atom) (revision 144601)
@@ -7506,6 +7506,11 @@ be ignored for this case. The additiona
recognize complicated bypasses, e.g.@: when the consumer is only an address
of insn @samp{store} (not a stored value).
+If there are more one bypass with the same output and input insns, the
+chosen bypass is the first bypass with a guard in description whose
+guard function returns nonzero. If there is no such bypass, then
+bypass without the guard function is chosen.
+
@findex exclusion_set
@findex presence_set
@findex final_presence_set
--- gcc/rtlanal.c (.../trunk) (revision 144460)
+++ gcc/rtlanal.c (.../branches/ix86/atom) (revision 144601)
@@ -728,6 +728,129 @@ reg_mentioned_p (const_rtx reg, const_rt
}
return 0;
}
+
+static int
+reg_mentioned_by_mem_p_1 (const_rtx reg, const_rtx in,
+ bool *mem_p)
+{
+ const char *fmt;
+ int i;
+ enum rtx_code code;
+
+ if (in == 0)
+ return 0;
+
+ if (reg == in)
+ return 1;
+
+ if (GET_CODE (in) == LABEL_REF)
+ return reg == XEXP (in, 0);
+
+ code = GET_CODE (in);
+
+ switch (code)
+ {
+ /* Compare registers by number. */
+ case REG:
+ return REG_P (reg) && REGNO (in) == REGNO (reg);
+
+ /* These codes have no constituent expressions
+ and are unique. */
+ case SCRATCH:
+ case CC0:
+ case PC:
+ return 0;
+
+ case CONST_INT:
+ case CONST_VECTOR:
+ case CONST_DOUBLE:
+ case CONST_FIXED:
+ /* These are kept unique for a given value. */
+ return 0;
+
+ default:
+ break;
+ }
+
[...2433 lines suppressed...]
+ USE_INSN. */
+
+bool
+ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
+{
+ rtx set_pattern = PATTERN (set_insn);
+ rtx set_dest;
+ rtx shift_rtx;
+ rtx use_pattern;
+
+ /* Retrieve destination of set_insn */
+ switch (GET_CODE (set_pattern))
+ {
+ case SET:
+ set_dest = SET_DEST (set_pattern);
+ break;
+ case PARALLEL:
+ set_pattern = XVECEXP (set_pattern, 0, 0);
+ if (GET_CODE (set_pattern ) == SET)
+ {
+ set_dest = SET_DEST (set_pattern);
+ break;
+ }
+ default:
+ set_dest = NULL;
+ break;
+ }
+ if (!set_dest || !REG_P (set_dest))
+ return false;
+
+ /* Retrieve shift count of use_insn */
+ use_pattern = PATTERN (use_insn);
+ switch (GET_CODE (use_pattern))
+ {
+ case SET:
+ shift_rtx = XEXP (use_pattern, 1);
+ break;
+ case PARALLEL:
+ set_pattern = XVECEXP (use_pattern, 0, 0);
+ if (GET_CODE (set_pattern) == SET)
+ {
+ shift_rtx = XEXP (set_pattern, 1);
+ break;
+ }
+ default:
+ shift_rtx = NULL;
+ break;
+ }
+
+ if (shift_rtx
+ && (GET_CODE (shift_rtx) == ASHIFT
+ || GET_CODE (shift_rtx) == LSHIFTRT
+ || GET_CODE (shift_rtx) == ASHIFTRT
+ || GET_CODE (shift_rtx) == ROTATE
+ || GET_CODE (shift_rtx) == ROTATERT))
+ {
+ rtx shift_count = XEXP (shift_rtx, 1);
+ gcc_assert (shift_count);
+
+ /* Return true if shift count is dest of set_insn */
+ if (REG_P (shift_count)
+ && true_regnum (set_dest) == true_regnum (shift_count))
+ return true;
+ }
+
+ return false;
+}
+
/* Return TRUE or FALSE depending on whether the unary operator meets the
appropriate constraints. */
@@ -18985,6 +19333,7 @@ ix86_issue_rate (void)
switch (ix86_tune)
{
case PROCESSOR_PENTIUM:
+ case PROCESSOR_ATOM:
case PROCESSOR_K6:
return 2;
@@ -19051,41 +19400,21 @@ ix86_flags_dependent (rtx insn, rtx dep_
return 1;
}
-/* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
- address with operands set by DEP_INSN. */
+/* Return true iff USE_INSN has a memory address with operands set by
+ SET_INSN. */
-static int
-ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
+bool
+ix86_agi_dependent (rtx set_insn, rtx use_insn)
{
- rtx addr;
-
- if (insn_type == TYPE_LEA
- && TARGET_PENTIUM)
- {
- addr = PATTERN (insn);
-
- if (GET_CODE (addr) == PARALLEL)
- addr = XVECEXP (addr, 0, 0);
-
- gcc_assert (GET_CODE (addr) == SET);
-
- addr = SET_SRC (addr);
- }
- else
- {
- int i;
- extract_insn_cached (insn);
- for (i = recog_data.n_operands - 1; i >= 0; --i)
- if (MEM_P (recog_data.operand[i]))
- {
- addr = XEXP (recog_data.operand[i], 0);
- goto found;
- }
- return 0;
- found:;
- }
-
- return modified_in_p (addr, dep_insn);
+ int i;
+ extract_insn_cached (use_insn);
+ for (i = recog_data.n_operands - 1; i >= 0; --i)
+ if (MEM_P (recog_data.operand[i]))
+ {
+ rtx addr = XEXP (recog_data.operand[i], 0);
+ return modified_in_p (addr, set_insn) != 0;
+ }
+ return false;
}
static int
@@ -19113,8 +19442,19 @@ ix86_adjust_cost (rtx insn, rtx link, rt
{
case PROCESSOR_PENTIUM:
/* Address Generation Interlock adds a cycle of latency. */
- if (ix86_agi_dependent (insn, dep_insn, insn_type))
- cost += 1;
+ if (insn_type == TYPE_LEA)
+ {
+ rtx addr = PATTERN (insn);
+
+ if (GET_CODE (addr) == PARALLEL)
+ addr = XVECEXP (addr, 0, 0);
+
+ gcc_assert (GET_CODE (addr) == SET);
+
+ addr = SET_SRC (addr);
+ if (modified_in_p (addr, dep_insn))
+ cost += 1;
+ }
/* ??? Compares pair with jump/setcc. */
if (ix86_flags_dependent (insn, dep_insn, insn_type))
@@ -19123,7 +19463,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt
/* Floating point stores require value to be ready one cycle earlier. */
if (insn_type == TYPE_FMOV
&& get_attr_memory (insn) == MEMORY_STORE
- && !ix86_agi_dependent (insn, dep_insn, insn_type))
+ && !ix86_agi_dependent (dep_insn, insn))
cost += 1;
break;
@@ -19146,7 +19486,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
- && !ix86_agi_dependent (insn, dep_insn, insn_type))
+ && !ix86_agi_dependent (dep_insn, insn))
{
/* Claim moves to take one cycle, as core can issue one load
at time and the next load can start cycle later. */
@@ -19175,7 +19515,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
- && !ix86_agi_dependent (insn, dep_insn, insn_type))
+ && !ix86_agi_dependent (dep_insn, insn))
{
/* Claim moves to take one cycle, as core can issue one load
at time and the next load can start cycle later. */
@@ -19192,6 +19532,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt
case PROCESSOR_ATHLON:
case PROCESSOR_K8:
case PROCESSOR_AMDFAM10:
+ case PROCESSOR_ATOM:
case PROCESSOR_GENERIC32:
case PROCESSOR_GENERIC64:
memory = get_attr_memory (insn);
@@ -19200,7 +19541,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
- && !ix86_agi_dependent (insn, dep_insn, insn_type))
+ && !ix86_agi_dependent (dep_insn, insn))
{
enum attr_unit unit = get_attr_unit (insn);
int loadcost = 3;
gcc44-pr39226.patch:
--- NEW FILE gcc44-pr39226.patch ---
2009-03-03 Jakub Jelinek <jakub at redhat.com>
PR target/39226
* config/rs6000/rs6000.md (andsi3_internal5_nomc,
anddi3_internal2_nomc, anddi3_internal3_nomc): Removed.
(booldi3_internal3): Use boolean_or_operator instead of
boolean_operator.
* gcc.dg/pr39226.c: New test.
--- gcc/config/rs6000/rs6000.md.jj 2009-03-02 18:09:02.000000000 +0100
+++ gcc/config/rs6000/rs6000.md 2009-03-03 10:02:37.771461086 +0100
@@ -2999,20 +2999,6 @@
[(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
(set_attr "length" "8,4,4,4,8,8,8,8")])
-(define_insn "*andsi3_internal5_nomc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y,??y,??y,?y")
- (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,r,K,L,T"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
- (and:SI (match_dup 1)
- (match_dup 2)))
- (clobber (match_scratch:CC 4 "=X,X,x,x,X"))]
- "TARGET_64BIT && !rs6000_gen_cell_microcode"
- "#"
- [(set_attr "type" "compare")
- (set_attr "length" "8,8,8,8,8")])
-
(define_split
[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -7684,18 +7670,6 @@
[(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
-(define_insn "*anddi3_internal2_nomc"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y,?y,??y,??y,?y")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "t,r,S,K,J,t"))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r,r,r,r,r"))
- (clobber (match_scratch:CC 4 "=X,X,X,x,x,X"))]
- "TARGET_64BIT && !rs6000_gen_cell_microcode"
- "#"
- [(set_attr "type" "delayed_compare,compare,compare,compare,compare,compare")
- (set_attr "length" "8,8,8,8,8,12")])
-
(define_split
[(set (match_operand:CC 0 "cc_reg_operand" "")
(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
@@ -7747,18 +7721,6 @@
[(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
-(define_insn "*anddi3_internal3_nomc"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y,?y,??y,??y,?y")
- (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
- (match_operand:DI 2 "and64_2_operand" "t,r,S,K,J,t"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
- (and:DI (match_dup 1) (match_dup 2)))
- (clobber (match_scratch:CC 4 "=X,X,X,x,x,X"))]
- "TARGET_64BIT && !rs6000_gen_cell_microcode"
- "#"
- [(set_attr "type" "delayed_compare,compare,compare,compare,compare,compare")
- (set_attr "length" "8,8,8,8,8,12")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
@@ -7915,7 +7877,7 @@
(define_insn "*booldi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (match_operator:DI 4 "boolean_operator"
+ (compare:CC (match_operator:DI 4 "boolean_or_operator"
[(match_operand:DI 1 "gpc_reg_operand" "%r,r")
(match_operand:DI 2 "gpc_reg_operand" "r,r")])
(const_int 0)))
--- gcc/testsuite/gcc.dg/pr39226.c.jj 2009-03-02 23:27:03.398459808 +0100
+++ gcc/testsuite/gcc.dg/pr39226.c 2009-03-02 23:26:19.696462209 +0100
@@ -0,0 +1,25 @@
+/* PR target/39226 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-options "-O2 -mtune=cell -mminimal-toc" { target { powerpc*-*-* && lp64 } } } */
+
+struct A
+{
+ char *a;
+ unsigned int b : 1;
+ unsigned int c : 31;
+};
+
+struct B
+{
+ struct A *d;
+};
+
+void
+foo (struct B *x, unsigned long y)
+{
+ if (x->d[y].c)
+ return;
+ if (x->d[y].b)
+ x->d[y].a = 0;
+}
gcc44-pr39358.patch:
--- NEW FILE gcc44-pr39358.patch ---
2009-03-04 Richard Guenther <rguenther at suse.de>
PR tree-optimization/39358
* tree-ssa-structalias.c (do_sd_constraint): Fix check for
escaped_id and callused_id.
(solve_graph): Likewise.
* g++.dg/warn/Wstrict-aliasing-bogus-escape-2.C: New testcase.
* g++.dg/warn/Wstrict-aliasing-bogus-escape-3.C: Likewise.
--- gcc/tree-ssa-structalias.c (revision 144601)
+++ gcc/tree-ssa-structalias.c (revision 144602)
@@ -1524,8 +1524,8 @@ do_sd_constraint (constraint_graph_t gra
of a variable can also reach all other fields of the variable
we simply have to expand the solution to contain all sub-fields
if one sub-field is contained. */
- if (c->rhs.var == escaped_id
- || c->rhs.var == callused_id)
+ if (c->rhs.var == find (escaped_id)
+ || c->rhs.var == find (callused_id))
{
bitmap vars = NULL;
/* In a first pass record all variables we need to add all
@@ -1594,9 +1594,10 @@ do_sd_constraint (constraint_graph_t gra
/* Merging the solution from ESCAPED needlessly increases
the set. Use ESCAPED as representative instead.
Same for CALLUSED. */
- else if (get_varinfo (t)->id == escaped_id
- || get_varinfo (t)->id == callused_id)
- flag |= bitmap_set_bit (sol, get_varinfo (t)->id);
+ else if (get_varinfo (t)->id == find (escaped_id))
+ flag |= bitmap_set_bit (sol, escaped_id);
+ else if (get_varinfo (t)->id == find (callused_id))
+ flag |= bitmap_set_bit (sol, callused_id);
else if (add_graph_edge (graph, lhs, t))
flag |= bitmap_ior_into (sol, get_varinfo (t)->solution);
}
@@ -2516,8 +2517,8 @@ solve_graph (constraint_graph_t graph)
if (!solution_empty
/* Do not propagate the ESCAPED/CALLUSED solutions. */
- && i != escaped_id
- && i != callused_id)
+ && i != find (escaped_id)
+ && i != find (callused_id))
{
bitmap_iterator bi;
--- gcc/testsuite/g++.dg/warn/Wstrict-aliasing-bogus-escape-2.C (revision 0)
+++ gcc/testsuite/g++.dg/warn/Wstrict-aliasing-bogus-escape-2.C (revision 144602)
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wstrict-aliasing" } */
+
+#include<list>
+
+struct A
+{
+ virtual ~A();
+};
+
+A* foo();
+
+void bar(std::list<int> x)
+{
+ std::list<int> y = x;
+ if (*y.rbegin())
+ delete foo();
+}
+
--- gcc/testsuite/g++.dg/warn/Wstrict-aliasing-bogus-escape-3.C (revision 0)
+++ gcc/testsuite/g++.dg/warn/Wstrict-aliasing-bogus-escape-3.C (revision 144602)
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wstrict-aliasing" } */
+
+struct Node_base {};
+
+struct Node : Node_base
+{
+ int data;
+};
+
+struct List
+{
+ Node_base node, *prev;
+
+ List() : prev(&node) { xyz(); }
+
+ void xyz();
+
+ int back() { return static_cast<Node*>(prev)->data; }
+};
+
+struct A
+{
+ virtual ~A();
+};
+
+A* foo();
+
+void bar()
+{
+ List y;
+ if (y.back())
+ delete foo();
+}
+
Index: .cvsignore
===================================================================
RCS file: /cvs/pkgs/rpms/gcc/devel/.cvsignore,v
retrieving revision 1.257
retrieving revision 1.258
diff -u -r1.257 -r1.258
--- .cvsignore 19 Feb 2009 16:45:44 -0000 1.257
+++ .cvsignore 4 Mar 2009 13:55:08 -0000 1.258
@@ -1,3 +1,3 @@
fastjar-0.97.tar.gz
-gcc-4.4.0-20090219.tar.bz2
+gcc-4.4.0-20090304.tar.bz2
cloog-ppl-0.15.tar.gz
Index: gcc.spec
===================================================================
RCS file: /cvs/pkgs/rpms/gcc/devel/gcc.spec,v
retrieving revision 1.24
retrieving revision 1.25
diff -u -r1.24 -r1.25
--- gcc.spec 24 Feb 2009 19:45:36 -0000 1.24
+++ gcc.spec 4 Mar 2009 13:55:08 -0000 1.25
@@ -1,9 +1,9 @@
-%define DATE 20090219
-%define SVNREV 144300
+%define DATE 20090304
+%define SVNREV 144601
%define gcc_version 4.4.0
# Note, gcc_release must be integer, if you want to add suffixes to
# %{release}, append them after %{gcc_release} on Release: line.
-%define gcc_release 0.21
+%define gcc_release 0.22
%define _unpackaged_files_terminate_build 0
%define multilib_64_archs sparc64 ppc64 s390x x86_64
%define include_gappletviewer 1
@@ -35,7 +35,7 @@
Summary: Various compilers (C, C++, Objective-C, Java, ...)
Name: gcc
Version: %{gcc_version}
-Release: %{gcc_release}.1
+Release: %{gcc_release}
# libgcc, libgfortran, libmudflap and crtstuff have an exception which allows
# linking it into any kind of programs or shared libraries without
# restrictions.
@@ -144,7 +144,9 @@
Patch21: gcc44-cloog-dl.patch
Patch22: gcc44-raw-string.patch
Patch23: gcc44-pr39175.patch
-Patch24: gcc44-pr39240.patch
+Patch24: gcc44-atom.patch
+Patch25: gcc44-pr39226.patch
+Patch26: gcc44-pr39358.patch
Patch1000: fastjar-0.97-segfault.patch
@@ -432,7 +434,9 @@
%endif
%patch22 -p0 -b .raw-string~
%patch23 -p0 -b .pr39175~
-%patch24 -p0 -b .pr39240~
+%patch24 -p0 -b .atom~
+%patch25 -p0 -b .pr39226~
+%patch26 -p0 -b .pr39358~
# This testcase doesn't compile.
rm libjava/testsuite/libjava.lang/PR35020*
@@ -1767,8 +1771,27 @@
%doc rpm.doc/changelogs/libmudflap/ChangeLog*
%changelog
-* Tue Feb 24 2009 Fedora Release Engineering <rel-eng at lists.fedoraproject.org> - 4.4.0-0.21.1
-- Rebuilt for https://fedoraproject.org/wiki/Fedora_11_Mass_Rebuild
+* Wed Mar 4 2009 Jakub Jelinek <jakub at redhat.com> 4.4.0-0.22
+- update from trunk
+ - PRs ada/39172, ada/39264, bootstrap/39257, c++/36411, c++/37789,
+ c++/38880, c++/39225, c++/39242, c/12245, classpath/38417,
+ classpath/38912, debug/39267, debug/39285, fortran/38914,
+ fortran/39292, fortran/39295, fortran/39309, fortran/39354,
+ libgcj/38861, middle-end/10109, middle-end/34443,
+ middle-end/39157, middle-end/39272, middle-end/39308,
+ middle-end/39335, middle-end/39345, rtl-optimization/39241,
+ target/33785, target/35965, target/39256, target/39261,
+ target/39327, testsuite/38164, tree-optimization/37709,
+ tree-optimization/39248, tree-optimization/39259,
+ tree-optimization/39260, tree-optimization/39318,
+ tree-optimization/39331, tree-optimizations/39259,
+ tree-optimization/39358
+ - fix ivopts (#486088, PR tree-optimization/39233)
+ - fix SRA (#487795, PR tree-optimization/39339)
+ - fix __builtin_object_size with unions (#487702,
+ PR tree-optimization/39343)
+- fix ppc -m64 -O2 -mtune=cell and patterns (#485067, PR target/39226)
+- -march=atom/-mtune=atom support from ix86/atom branch
* Thu Feb 19 2009 Jakub Jelinek <jakub at redhat.com> 4.4.0-0.21
- update from trunk
Index: sources
===================================================================
RCS file: /cvs/pkgs/rpms/gcc/devel/sources,v
retrieving revision 1.260
retrieving revision 1.261
diff -u -r1.260 -r1.261
--- sources 19 Feb 2009 16:45:44 -0000 1.260
+++ sources 4 Mar 2009 13:55:08 -0000 1.261
@@ -1,3 +1,3 @@
2659f09c2e43ef8b7d4406321753f1b2 fastjar-0.97.tar.gz
-67b7f59414d468df2d68a8b6dadd0153 gcc-4.4.0-20090219.tar.bz2
+75f2e4ab9717342f13146245d58fa160 gcc-4.4.0-20090304.tar.bz2
716b7a0823f96c9d02c1703a9c47d387 cloog-ppl-0.15.tar.gz
--- gcc44-pr39240.patch DELETED ---
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