rpms/binutils/devel binutils-2.20.51.0.2-ifunc-ld-s.patch, NONE, 1.1 binutils-2.20.51.0.2-lwp.patch, NONE, 1.1 binutils.spec, 1.178, 1.179

Jakub Jelinek jakub at fedoraproject.org
Mon Nov 9 10:01:05 UTC 2009


Author: jakub

Update of /cvs/pkgs/rpms/binutils/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv30525

Modified Files:
	binutils.spec 
Added Files:
	binutils-2.20.51.0.2-ifunc-ld-s.patch 
	binutils-2.20.51.0.2-lwp.patch 
Log Message:
2.20.51.0.2-4

binutils-2.20.51.0.2-ifunc-ld-s.patch:
 bfd/elflink.c                        |    4 +++-
 ld/testsuite/ld-ifunc/ifunc-4a-x86.d |    8 ++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

--- NEW FILE binutils-2.20.51.0.2-ifunc-ld-s.patch ---
2009-11-08  H.J. Lu  <hongjiu.lu at intel.com>

	PR ld/10911
	* elflink.c (elf_link_output_extsym): Don't return on
	STT_GNU_IFUNC symbol when stripping.

	* ld-ifunc/ifunc-4a-x86.d: New.

--- bfd/elflink.c
+++ bfd/elflink.c
@@ -8639,9 +8639,11 @@ elf_link_output_extsym (struct elf_link_hash_entry *h, void *data)
     strip = FALSE;
 
   /* If we're stripping it, and it's not a dynamic symbol, there's
-     nothing else to do unless it is a forced local symbol.  */
+     nothing else to do unless it is a forced local symbol or a
+     STT_GNU_IFUNC symbol.  */
   if (strip
       && h->dynindx == -1
+      && h->type != STT_GNU_IFUNC
       && !h->forced_local)
     return TRUE;
 
--- ld/testsuite/ld-ifunc/ifunc-4a-x86.d
+++ ld/testsuite/ld-ifunc/ifunc-4a-x86.d
@@ -0,0 +1,8 @@
+#ld: -s
+#readelf: -r --wide
+#target: x86_64-*-* i?86-*-*
+#source: ifunc-4-x86.s
+
+#...
+[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_[_0-9A-Z]+_IRELATIVE[ ]*[0-9a-f]*
+#pass

binutils-2.20.51.0.2-lwp.patch:
 gas/config/tc-i386.c                 |   45 
 gas/doc/c-i386.texi                  |   22 
 gas/testsuite/gas/i386/fma4.d        |  168 
 gas/testsuite/gas/i386/i386.exp      |    2 
 gas/testsuite/gas/i386/lwp.d         |  137 
 gas/testsuite/gas/i386/lwp.s         |  141 
 gas/testsuite/gas/i386/x86-64-fma4.d |  115 
 gas/testsuite/gas/i386/x86-64-lwp.d  |  393 +
 gas/testsuite/gas/i386/x86-64-lwp.s  |  397 +
 opcodes/i386-dis.c                   |  938 ++-
 opcodes/i386-gen.c                   |    8 
 opcodes/i386-init.h                  |  137 
 opcodes/i386-opc.h                   |   19 
 opcodes/i386-opc.tbl                 |   15 
 opcodes/i386-tbl.h                   | 9624 +++++++++++++++++------------------
 15 files changed, 7071 insertions(+), 5090 deletions(-)

--- NEW FILE binutils-2.20.51.0.2-lwp.patch ---
opcodes/
2009-11-06  Sebastian Pop  <sebastian.pop at amd.com>

	* i386-dis.c (reg_table): Add XOP_8F_TABLE (XOP_09) to
	reg_table[REG_8F][1]: for XOP instructions, ModRM.reg first points to
	B.mm in the RXB.mmmmm byte, and so when B is set, we still should use
	the xop_table.
	(get_valid_dis386): Removed unused condition (from cut/n/paste) for
	XOP instructions.

2009-11-05  Sebastian Pop  <sebastian.pop at amd.com>
	    Quentin Neill  <quentin.neill at amd.com>

	* i386-dis.c (OP_LWPCB_E): New.
	(OP_LWP_E): New.
	(OP_LWP_I): New.
	(USE_XOP_8F_TABLE): New.
	(XOP_8F_TABLE): New.
	(REG_XOP_LWPCB): New.
	(REG_XOP_LWP): New.
	(XOP_09): New.
	(XOP_0A): New.
	(reg_table): Redirect REG_8F to XOP_8F_TABLE.
	Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
	(xop_table): New.
	(get_valid_dis386): Handle USE_XOP_8F_TABLE.
	Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
	to access to the vex_table.
	(OP_LWPCB_E): New.
	(OP_LWP_E): New.
	(OP_LWP_I): New.
	* opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
	(cpu_flags): Add CpuLWP.
	(opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
	* opcodes/i386-opc.h (CpuLWP): New.
	(i386_cpu_flags): Add bit cpulwp.
	(VexLWP): New.
	(XOP09): New.
	(XOP0A): New.
	(i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
	* opcodes/i386-opc.tbl (llwpcb): Added.
	(lwpval): Added.
	(lwpins): Added.

2009-10-29  Sebastian Pop  <sebastian.pop at amd.com>

	* i386-dis.c (OP_VEX_FMA): Removed.
	(VexFMA): Removed.
	(Vex128FMA): Removed.
	(prefix_table): First source operand of FMA4 insns is decoded
	with Vex not with VexFMA.
	(OP_EX_VexW): Second source operand is decoded with get_vex_imm8
	when vex.w is set.  Third source operand is decoded with

gas/
2009-11-06  H.J. Lu  <hongjiu.lu at intel.com>

	* doc/c-i386.texi: Move .lwp.

2009-11-05  Sebastian Pop  <sebastian.pop at amd.com>
	    Quentin Neill  <quentin.neill at amd.com>

	* config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS.
	(build_vex_prefix): Handle xop09 and xop0a.
	(build_modrm_byte): Handle vexlwp.
	(md_show_usage): Add lwp.
	* doc/c-i386.texi (i386-LWP): New section.

2009-10-29  Sebastian Pop  <sebastian.pop at amd.com>

	* config/tc-i386.c (build_modrm_byte): Do not swap REG and
	NDS operands for FMA4.

gas/testsuite/
2009-11-06  Sebastian Pop  <sebastian.pop at amd.com>

	* gas/i386/x86-64-lwp.s: Updated to also contain patterns
	with r[8-15] registers.
	* gas/i386/x86-64-lwp.d: Same.

2009-11-05  Sebastian Pop  <sebastian.pop at amd.com>
	    Quentin Neill  <quentin.neill at amd.com>

	* gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode,
	run lwp in 32-bit mode.
	* gas/i386/x86-64-lwp.d: New.
	* gas/i386/x86-64-lwp.s: New.
	* gas/i386/lwp.d: New.
	* gas/i386/lwp.s: New.

2009-10-29  Sebastian Pop  <sebastian.pop at amd.com>

	* gas/i386/fma4.d: Updated patterns.
	* gas/i386/x86-64-fma4.d: Same.

--- opcodes/i386-dis.c	20 Oct 2009 22:18:19 -0000	1.205
+++ opcodes/i386-dis.c	6 Nov 2009 23:17:26 -0000	1.208
@@ -93,7 +93,6 @@ static void OP_MS (int, int);
 static void OP_XS (int, int);
 static void OP_M (int, int);
 static void OP_VEX (int, int);
-static void OP_VEX_FMA (int, int);
 static void OP_EX_Vex (int, int);
 static void OP_EX_VexW (int, int);
 static void OP_XMM_Vex (int, int);
@@ -115,6 +114,9 @@ static void REP_Fixup (int, int);
 static void CMPXCHG8B_Fixup (int, int);
 static void XMM_Fixup (int, int);
 static void CRC32_Fixup (int, int);
+static void OP_LWPCB_E (int, int);
+static void OP_LWP_E (int, int);
+static void OP_LWP_I (int, int);
 
 static void MOVBE_Fixup (int, int);
 
@@ -363,8 +365,6 @@ fetch_data (struct disassemble_info *inf
 #define Vex128 { OP_VEX, vex128_mode }
 #define Vex256 { OP_VEX, vex256_mode }
 #define VexI4 { VEXI4_Fixup, 0}
-#define VexFMA { OP_VEX_FMA, vex_mode }
-#define Vex128FMA { OP_VEX_FMA, vex128_mode }
 #define EXdVex { OP_EX_Vex, d_mode }
 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 #define EXqVex { OP_EX_Vex, q_mode }
@@ -515,7 +515,8 @@ fetch_data (struct disassemble_info *inf
 #define USE_PREFIX_TABLE	(USE_RM_TABLE + 1)
 #define USE_X86_64_TABLE	(USE_PREFIX_TABLE + 1)
 #define USE_3BYTE_TABLE		(USE_X86_64_TABLE + 1)
-#define USE_VEX_C4_TABLE	(USE_3BYTE_TABLE + 1)
+#define USE_XOP_8F_TABLE	(USE_3BYTE_TABLE + 1)
+#define USE_VEX_C4_TABLE	(USE_XOP_8F_TABLE + 1)
 #define USE_VEX_C5_TABLE	(USE_VEX_C4_TABLE + 1)
 #define USE_VEX_LEN_TABLE	(USE_VEX_C5_TABLE + 1)
 
@@ -528,6 +529,7 @@ fetch_data (struct disassemble_info *inf
 #define PREFIX_TABLE(I)		DIS386 (USE_PREFIX_TABLE, (I))
 #define X86_64_TABLE(I)		DIS386 (USE_X86_64_TABLE, (I))
 #define THREE_BYTE_TABLE(I)	DIS386 (USE_3BYTE_TABLE, (I))
+#define XOP_8F_TABLE(I)		DIS386 (USE_XOP_8F_TABLE, (I))
 #define VEX_C4_TABLE(I)		DIS386 (USE_VEX_C4_TABLE, (I))
 #define VEX_C5_TABLE(I)		DIS386 (USE_VEX_C5_TABLE, (I))
 #define VEX_LEN_TABLE(I)	DIS386 (USE_VEX_LEN_TABLE, (I))
@@ -564,6 +566,8 @@ fetch_data (struct disassemble_info *inf
 #define REG_VEX_72		(REG_VEX_71 + 1)
 #define REG_VEX_73		(REG_VEX_72 + 1)
 #define REG_VEX_AE		(REG_VEX_73 + 1)
+#define REG_XOP_LWPCB		(REG_VEX_AE + 1)
+#define REG_XOP_LWP		(REG_XOP_LWPCB + 1)
 
 #define MOD_8D			0
 #define MOD_0F01_REG_0		(MOD_8D + 1)
@@ -1050,6 +1054,9 @@ fetch_data (struct disassemble_info *inf
 #define THREE_BYTE_0F3A		(THREE_BYTE_0F38 + 1)
 #define THREE_BYTE_0F7A		(THREE_BYTE_0F3A + 1)
 
+#define XOP_09			0
+#define XOP_0A			(XOP_09 + 1)
+
 #define VEX_0F			0
 #define VEX_0F38		(VEX_0F + 1)
 #define VEX_0F3A		(VEX_0F38 + 1)
@@ -2092,11 +2099,11 @@ static const struct dis386 reg_table[][8
   /* REG_8F */
   {
     { "popU",	{ stackEv } },
+    { XOP_8F_TABLE (XOP_09) },
     { "(bad)",	{ XX } },
     { "(bad)",	{ XX } },
     { "(bad)",	{ XX } },
-    { "(bad)",	{ XX } },
-    { "(bad)",	{ XX } },
+    { XOP_8F_TABLE (XOP_09) },
     { "(bad)",	{ XX } },
     { "(bad)",	{ XX } },
   },
@@ -2408,6 +2415,28 @@ static const struct dis386 reg_table[][8
     { "(bad)",	{ XX } },
     { "(bad)",	{ XX } },
   },
+  /* REG_XOP_LWPCB */
+  {
+    { "llwpcb", { { OP_LWPCB_E, 0 } } },
+    { "slwpcb",	{ { OP_LWPCB_E, 0 } } },
+    { "(bad)",	{ XX } },
+    { "(bad)",	{ XX } },
+    { "(bad)",	{ XX } },
+    { "(bad)",	{ XX } },
+    { "(bad)",	{ XX } },
+    { "(bad)",	{ XX } },
+  },
+  /* REG_XOP_LWP */
+  {
+    { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
+    { "lwpval",	{ { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
+    { "(bad)",	{ XX } },
+    { "(bad)",	{ XX } },
+    { "(bad)",	{ XX } },
+    { "(bad)",	{ XX } },
+    { "(bad)",	{ XX } },
[...32819 lines suppressed...]
+	lwpval $0x12345678, %esp, %r12
+	lwpval $0x12345678, %ebp, %r13
+	lwpval $0x12345678, %esi, %r14
+	lwpval $0x12345678, %edi, %r15
+
+	lwpins $0x1234, (%eax), %ax
+	lwpins $0x1234, (%ecx), %cx
+	lwpins $0x1234, (%edx), %dx
+	lwpins $0x1234, (%ebx), %bx
+	lwpins $0x1234, (%esp), %sp
+	lwpins $0x1234, (%ebp), %bp
+	lwpins $0x1234, (%esi), %si
+	lwpins $0x1234, (%edi), %di
+	lwpins $0x1234, (%r8d), %r8w
+	lwpins $0x1234, (%r9d), %r9w
+	lwpins $0x1234, (%r10d), %r10w
+	lwpins $0x1234, (%r11d), %r11w
+	lwpins $0x1234, (%r12d), %r12w
+	lwpins $0x1234, (%r13d), %r13w
+	lwpins $0x1234, (%r14d), %r14w
+	lwpins $0x1234, (%r15d), %r15w
+	lwpins $0x12345678, (%r15d), %eax
+	lwpins $0x12345678, (%r14d), %ecx
+	lwpins $0x12345678, (%r13d), %edx
+	lwpins $0x12345678, (%r12d), %ebx
+	lwpins $0x12345678, (%r11d), %esp
+	lwpins $0x12345678, (%r10d), %ebp
+	lwpins $0x12345678, (%r9d), %esi
+	lwpins $0x12345678, (%r8d), %edi
+	lwpins $0x12345678, (%edi), %r8d
+	lwpins $0x12345678, (%esi), %r9d
+	lwpins $0x12345678, (%ebp), %r10d
+	lwpins $0x12345678, (%esp), %r11d
+	lwpins $0x12345678, (%ebx), %r12d
+	lwpins $0x12345678, (%edx), %r13d
+	lwpins $0x12345678, (%ecx), %r14d
+	lwpins $0x12345678, (%eax), %r15d
+	lwpins $0x12345678, (%r15d), %rax
+	lwpins $0x12345678, (%r14d), %rcx
+	lwpins $0x12345678, (%r13d), %rdx
+	lwpins $0x12345678, (%r12d), %rbx
+	lwpins $0x12345678, (%r11d), %rsp
+	lwpins $0x12345678, (%r10d), %rbp
+	lwpins $0x12345678, (%r9d), %rsi
+	lwpins $0x12345678, (%r8d), %rdi
+	lwpins $0x12345678, (%eax), %r8
+	lwpins $0x12345678, (%ecx), %r9
+	lwpins $0x12345678, (%edx), %r10
+	lwpins $0x12345678, (%ebx), %r11
+	lwpins $0x12345678, (%esp), %r12
+	lwpins $0x12345678, (%ebp), %r13
+	lwpins $0x12345678, (%esi), %r14
+	lwpins $0x12345678, (%edi), %r15
+
+	lwpval $0x1234, (%eax), %ax
+	lwpval $0x1234, (%ecx), %cx
+	lwpval $0x1234, (%edx), %dx
+	lwpval $0x1234, (%ebx), %bx
+	lwpval $0x1234, (%esp), %sp
+	lwpval $0x1234, (%ebp), %bp
+	lwpval $0x1234, (%esi), %si
+	lwpval $0x1234, (%edi), %di
+	lwpval $0x1234, (%r8d), %r8w
+	lwpval $0x1234, (%r9d), %r9w
+	lwpval $0x1234, (%r10d), %r10w
+	lwpval $0x1234, (%r11d), %r11w
+	lwpval $0x1234, (%r12d), %r12w
+	lwpval $0x1234, (%r13d), %r13w
+	lwpval $0x1234, (%r14d), %r14w
+	lwpval $0x1234, (%r15d), %r15w
+	lwpval $0x12345678, (%r15d), %eax
+	lwpval $0x12345678, (%r14d), %ecx
+	lwpval $0x12345678, (%r13d), %edx
+	lwpval $0x12345678, (%r12d), %ebx
+	lwpval $0x12345678, (%r11d), %esp
+	lwpval $0x12345678, (%r10d), %ebp
+	lwpval $0x12345678, (%r9d), %esi
+	lwpval $0x12345678, (%r8d), %edi
+	lwpval $0x12345678, (%edi), %r8d
+	lwpval $0x12345678, (%esi), %r9d
+	lwpval $0x12345678, (%ebp), %r10d
+	lwpval $0x12345678, (%esp), %r11d
+	lwpval $0x12345678, (%ebx), %r12d
+	lwpval $0x12345678, (%edx), %r13d
+	lwpval $0x12345678, (%ecx), %r14d
+	lwpval $0x12345678, (%eax), %r15d
+	lwpval $0x12345678, (%r15d), %rax
+	lwpval $0x12345678, (%r14d), %rcx
+	lwpval $0x12345678, (%r13d), %rdx
+	lwpval $0x12345678, (%r12d), %rbx
+	lwpval $0x12345678, (%r11d), %rsp
+	lwpval $0x12345678, (%r10d), %rbp
+	lwpval $0x12345678, (%r9d), %rsi
+	lwpval $0x12345678, (%r8d), %rdi
+	lwpval $0x12345678, (%eax), %r8
+	lwpval $0x12345678, (%ecx), %r9
+	lwpval $0x12345678, (%edx), %r10
+	lwpval $0x12345678, (%ebx), %r11
+	lwpval $0x12345678, (%esp), %r12
+	lwpval $0x12345678, (%ebp), %r13
+	lwpval $0x12345678, (%esi), %r14
+	lwpval $0x12345678, (%edi), %r15
+
+	lwpins $0x1234, 0xcafe(%eax), %ax
+	lwpins $0x1234, 0xcafe(%ecx), %cx
+	lwpins $0x1234, 0xcafe(%edx), %dx
+	lwpins $0x1234, 0xcafe(%ebx), %bx
+	lwpins $0x1234, 0xcafe(%esp), %sp
+	lwpins $0x1234, 0xcafe(%ebp), %bp
+	lwpins $0x1234, 0xcafe(%esi), %si
+	lwpins $0x1234, 0xcafe(%edi), %di
+	lwpins $0x1234, 0xcafe(%r8d), %r8w
+	lwpins $0x1234, 0xcafe(%r9d), %r9w
+	lwpins $0x1234, 0xcafe(%r10d), %r10w
+	lwpins $0x1234, 0xcafe(%r11d), %r11w
+	lwpins $0x1234, 0xcafe(%r12d), %r12w
+	lwpins $0x1234, 0xcafe(%r13d), %r13w
+	lwpins $0x1234, 0xcafe(%r14d), %r14w
+	lwpins $0x1234, 0xcafe(%r15d), %r15w
+	lwpins $0x12345678, 0xcafe(%r15d), %eax
+	lwpins $0x12345678, 0xcafe(%r14d), %ecx
+	lwpins $0x12345678, 0xcafe(%r13d), %edx
+	lwpins $0x12345678, 0xcafe(%r12d), %ebx
+	lwpins $0x12345678, 0xcafe(%r11d), %esp
+	lwpins $0x12345678, 0xcafe(%r10d), %ebp
+	lwpins $0x12345678, 0xcafe(%r9d), %esi
+	lwpins $0x12345678, 0xcafe(%r8d), %edi
+	lwpins $0x12345678, 0xcafe(%edi), %r8d
+	lwpins $0x12345678, 0xcafe(%esi), %r9d
+	lwpins $0x12345678, 0xcafe(%ebp), %r10d
+	lwpins $0x12345678, 0xcafe(%esp), %r11d
+	lwpins $0x12345678, 0xcafe(%ebx), %r12d
+	lwpins $0x12345678, 0xcafe(%edx), %r13d
+	lwpins $0x12345678, 0xcafe(%ecx), %r14d
+	lwpins $0x12345678, 0xcafe(%eax), %r15d
+	lwpins $0x12345678, 0xcafe(%r15d), %rax
+	lwpins $0x12345678, 0xcafe(%r14d), %rcx
+	lwpins $0x12345678, 0xcafe(%r13d), %rdx
+	lwpins $0x12345678, 0xcafe(%r12d), %rbx
+	lwpins $0x12345678, 0xcafe(%r11d), %rsp
+	lwpins $0x12345678, 0xcafe(%r10d), %rbp
+	lwpins $0x12345678, 0xcafe(%r9d), %rsi
+	lwpins $0x12345678, 0xcafe(%r8d), %rdi
+	lwpins $0x12345678, 0xcafe(%eax), %r8
+	lwpins $0x12345678, 0xcafe(%ecx), %r9
+	lwpins $0x12345678, 0xcafe(%edx), %r10
+	lwpins $0x12345678, 0xcafe(%ebx), %r11
+	lwpins $0x12345678, 0xcafe(%esp), %r12
+	lwpins $0x12345678, 0xcafe(%ebp), %r13
+	lwpins $0x12345678, 0xcafe(%esi), %r14
+	lwpins $0x12345678, 0xcafe(%edi), %r15
+
+	lwpval $0x1234, 0xcafe(%eax), %ax
+	lwpval $0x1234, 0xcafe(%ecx), %cx
+	lwpval $0x1234, 0xcafe(%edx), %dx
+	lwpval $0x1234, 0xcafe(%ebx), %bx
+	lwpval $0x1234, 0xcafe(%esp), %sp
+	lwpval $0x1234, 0xcafe(%ebp), %bp
+	lwpval $0x1234, 0xcafe(%esi), %si
+	lwpval $0x1234, 0xcafe(%edi), %di
+	lwpval $0x1234, 0xcafe(%r8d), %r8w
+	lwpval $0x1234, 0xcafe(%r9d), %r9w
+	lwpval $0x1234, 0xcafe(%r10d), %r10w
+	lwpval $0x1234, 0xcafe(%r11d), %r11w
+	lwpval $0x1234, 0xcafe(%r12d), %r12w
+	lwpval $0x1234, 0xcafe(%r13d), %r13w
+	lwpval $0x1234, 0xcafe(%r14d), %r14w
+	lwpval $0x1234, 0xcafe(%r15d), %r15w
+	lwpval $0x12345678, 0xcafe(%r15d), %eax
+	lwpval $0x12345678, 0xcafe(%r14d), %ecx
+	lwpval $0x12345678, 0xcafe(%r13d), %edx
+	lwpval $0x12345678, 0xcafe(%r12d), %ebx
+	lwpval $0x12345678, 0xcafe(%r11d), %esp
+	lwpval $0x12345678, 0xcafe(%r10d), %ebp
+	lwpval $0x12345678, 0xcafe(%r9d), %esi
+	lwpval $0x12345678, 0xcafe(%r8d), %edi
+	lwpval $0x12345678, 0xcafe(%edi), %r8d
+	lwpval $0x12345678, 0xcafe(%esi), %r9d
+	lwpval $0x12345678, 0xcafe(%ebp), %r10d
+	lwpval $0x12345678, 0xcafe(%esp), %r11d
+	lwpval $0x12345678, 0xcafe(%ebx), %r12d
+	lwpval $0x12345678, 0xcafe(%edx), %r13d
+	lwpval $0x12345678, 0xcafe(%ecx), %r14d
+	lwpval $0x12345678, 0xcafe(%eax), %r15d
+	lwpval $0x12345678, 0xcafe(%r15d), %rax
+	lwpval $0x12345678, 0xcafe(%r14d), %rcx
+	lwpval $0x12345678, 0xcafe(%r13d), %rdx
+	lwpval $0x12345678, 0xcafe(%r12d), %rbx
+	lwpval $0x12345678, 0xcafe(%r11d), %rsp
+	lwpval $0x12345678, 0xcafe(%r10d), %rbp
+	lwpval $0x12345678, 0xcafe(%r9d), %rsi
+	lwpval $0x12345678, 0xcafe(%r8d), %rdi
+	lwpval $0x12345678, 0xcafe(%eax), %r8
+	lwpval $0x12345678, 0xcafe(%ecx), %r9
+	lwpval $0x12345678, 0xcafe(%edx), %r10
+	lwpval $0x12345678, 0xcafe(%ebx), %r11
+	lwpval $0x12345678, 0xcafe(%esp), %r12
+	lwpval $0x12345678, 0xcafe(%ebp), %r13
+	lwpval $0x12345678, 0xcafe(%esi), %r14
+	lwpval $0x12345678, 0xcafe(%edi), %r15


Index: binutils.spec
===================================================================
RCS file: /cvs/pkgs/rpms/binutils/devel/binutils.spec,v
retrieving revision 1.178
retrieving revision 1.179
diff -u -p -r1.178 -r1.179
--- binutils.spec	5 Nov 2009 18:33:17 -0000	1.178
+++ binutils.spec	9 Nov 2009 10:01:04 -0000	1.179
@@ -17,7 +17,7 @@
 Summary: A GNU collection of binary utilities
 Name: %{?cross}binutils%{?_with_debug:-debug}
 Version: 2.20.51.0.2
-Release: 3%{?dist}
+Release: 4%{?dist}
 License: GPLv3+
 Group: Development/Tools
 URL: http://sources.redhat.com/binutils
@@ -31,6 +31,8 @@ Patch05: binutils-2.20.51.0.2-version.pa
 Patch06: binutils-2.20.51.0.2-set-long-long.patch
 Patch07: binutils-2.20.51.0.2-build-id.patch
 Patch08: binutils-2.20.51.0.2-add-needed.patch
+Patch09: binutils-2.20.51.0.2-ifunc-ld-s.patch
+Patch10: binutils-2.20.51.0.2-lwp.patch
 
 %if 0%{?_with_debug:1}
 # Define this if you want to skip the strip step and preserve debug info.
@@ -103,6 +105,8 @@ to consider using libelf instead of BFD.
 %patch06 -p0 -b .set-long-long~
 %patch07 -p0 -b .build-id~
 %patch08 -p0 -b .add-needed~
+%patch09 -p0 -b .ifunc-ld-s~
+%patch10 -p0 -b .lwp~
 
 # We cannot run autotools as there is an exact requirement of autoconf-2.59.
 
@@ -370,6 +374,10 @@ exit 0
 %endif # %{isnative}
 
 %changelog
+* Mon Nov  9 2009 Jakub Jelinek <jakub at redhat.com> 2.20.51.0.2-4
+- Fix ld -s with IRELATIVE relocations.  (BZ 533321, PR ld/10911)
+- Add AMD Orochi LWP support, fix FMA4 support.
+
 * Thu Nov 05 2009 Nick CLifton <nickc at redhat.com> 2.20.51.0.2-3
 - Rename --add-needed to --copy-dt-needed-entries and improve error message about unresolved symbols in DT_NEEDED DSOs.
 




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