[Bug 248649] New: Review Request: alliance - Alliance VLSI CAD Sytem

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https://bugzilla.redhat.com/bugzilla/show_bug.cgi?id=248649

           Summary: Review Request: alliance -  Alliance VLSI CAD Sytem
           Product: Fedora
           Version: devel
          Platform: All
        OS/Version: Linux
            Status: NEW
          Severity: medium
          Priority: medium
         Component: Package Review
        AssignedTo: nobody at fedoraproject.org
        ReportedBy: cgoorah at yahoo.com.au
         QAContact: extras-qa at fedoraproject.org
                CC: fedora-package-review at redhat.com,notting at redhat.com


Spec URL: http://tux.u-strasbg.fr/~chit/alliance/F-8/alliance.spec
SRPM URL: http://tux.u-strasbg.fr/~chit/alliance/F-8/alliance-5.0-1.fc8.src.rpm
Description:
Alliance is a complete set of free CAD tools and portable libraries for
VLSI design. It includes a VHDL compiler and simulator, logic synthesis
tools, and automatic place and route tools.

A complete set of portable CMOS libraries is provided, including a RAM
generator, a ROM generator and a data-path compiler.

Alliance is the result of more than ten years effort spent at ASIM department
of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

Alliance has been used for research projects such as the 875 000 transistors
StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
Router.

Alliance provides CAD tools covering most of all the digital design flow:

 * VHDL Compilation and Simulation
 * Model checking and formal proof
 * RTL and Logic synthesis
 * Data-Path compilation
 * Macro-cells generation
 * Place and route
 * Layout edition
 * Netlist extraction and verification
 * Design rules checking

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