[Bug 468516] New: Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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Summary: Review Request: verilator - A fast simulator of synthesizable Verilog HDL

https://bugzilla.redhat.com/show_bug.cgi?id=468516

           Summary: Review Request: verilator - A fast simulator of
                    synthesizable Verilog HDL
           Product: Fedora
           Version: rawhide
          Platform: All
        OS/Version: Linux
            Status: NEW
          Severity: medium
          Priority: medium
         Component: Package Review
        AssignedTo: nobody at fedoraproject.org
        ReportedBy: dirjud at gmail.com
         QAContact: extras-qa at fedoraproject.org
                CC: notting at redhat.com, fedora-package-review at redhat.com
   Estimated Hours: 0.0
    Classification: Fedora


Spec URL: http://brooks.nu/~lane/verilator.spec
SRPM URL: http://brooks.nu/~lane/verilator-3.680-2.fc10.src.rpm
Description: 
Verilator is the fastest free Verilog HDL simulator. It compiles
synthesizable Verilog (not test-bench code!), plus some PSL,
SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of
primary concern, and is especially well suited to create executable
models of CPUs for embedded software design teams.

Because of systemc licensing issues, the verilator dependancies on
systemc are not included with this package.  This means the
perl-verilog, perl-systemc, and systemc functionality that is
integrated into verilator will only work if those packages are
installed separately.  This package, therefore, supports the verilog
features of verilator (including vcd generation via the --trace
option).

This is my first Fedora package.  Chitlesh Goorah will sponsor this package as
it will become part of FEL.

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