[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #16 from manuel wolfshant <wolfy at nobugconsulting.ro>  2009-01-02 14:43:26 EDT ---
The suggestion was to package the example files (i.e. the content of
/usr/share/verilator/examples), which needed two steps
- move the folder /usr/share/verilator/examples directly below $BUILDROOT
- use the "%doc" directive to include the above mentioned folder

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