[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #18 from Lane <dirjud at gmail.com>  2009-01-02 15:23:18 EDT ---
I updated the spec file to move the examples from the data directory to the doc
directory.

You can download the updates from:
Spec URL: http://brooks.nu/~lane/verilator.spec
SRPM URL: http://brooks.nu/~lane/verilator-3.681-2.fc10.src.rpm

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