[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #22 from Chitlesh GOORAH <cgoorah at yahoo.com.au>  2009-01-04 06:16:28 EDT ---
(In reply to comment #21)
> If you are
> packaging the one from Wilson Snyder, then I can remove these files.

Yes, I'll package the ones from Wilson Snyder.
I'm also trying to package everything from veripool for F-11.

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