[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #26 from Chitlesh GOORAH <cgoorah at yahoo.com.au>  2009-01-09 13:05:10 EDT ---


in file (of verilator) src/V3Options.cpp: 

&& !V3Options::fileStatNormal(var+"/src/systemperl.h")) {

if you remove /src, I believe it should pull systemperl.h from
perl-SystemPerl-devel. Can you check if please ?


in the 3.700 release notes, you are listed for:
- Add limited support for tristate inouts. Written by Lane Brooks. This allows
common pad ring and tristate-mux structures to be Verilated. See the
documentation for more information on supported constructs.

- Fix 'bad select range' warning missing some cases, bug43. [Lane Brooks]

good job Lane.

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