[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #39 from Jason Tibbitts <tibbs at math.uh.edu>  2009-07-10 23:19:56 EDT ---
Since the package is approved, it is up to the submitter of the ticket to take
the next step, that being a CVS request so the package can be imported, built
and pushed out.

The procedure is fully documented in
  http://fedoraproject.org/wiki/PackageMaintainers/Join
Every new packager should read over that before submitting packages.

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