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[libvirt] [PATCH v2 0/8] cpu: modularize the CPU map data file



Currently we have a cpu_map.xml file that contains all the features and
CPU models for all architectures in one place. I frequently find myself
wondering about the differences between CPU models, but it is hard to
compare them as the list of features is huge.

With this patch series we end up with a large set of small files, one
per named CPU model, along with one for the feature and vendor
definitions

   cpu_map/index.xml
   cpu_map/ppc64_POWER6.xml
   cpu_map/ppc64_POWER7.xml
   cpu_map/ppc64_POWER8.xml
   cpu_map/ppc64_POWER9.xml
   cpu_map/ppc64_POWERPC_e5500.xml
   cpu_map/ppc64_POWERPC_e6500.xml
   cpu_map/ppc64_vendors.xml
   cpu_map/x86_486.xml
   cpu_map/x86_athlon.xml
   cpu_map/x86_Broadwell-IBRS.xml
   cpu_map/x86_Broadwell-noTSX-IBRS.xml
   cpu_map/x86_Broadwell-noTSX.xml
   cpu_map/x86_Broadwell.xml
   cpu_map/x86_Conroe.xml
   cpu_map/x86_core2duo.xml
   cpu_map/x86_coreduo.xml
   cpu_map/x86_cpu64-rhel5.xml
   cpu_map/x86_cpu64-rhel6.xml
   cpu_map/x86_EPYC-IBRS.xml
   cpu_map/x86_EPYC.xml
   cpu_map/x86_features.xml
   cpu_map/x86_Haswell-IBRS.xml
   cpu_map/x86_Haswell-noTSX-IBRS.xml
   cpu_map/x86_Haswell-noTSX.xml
   cpu_map/x86_Haswell.xml
   cpu_map/x86_IvyBridge-IBRS.xml
   cpu_map/x86_IvyBridge.xml
   cpu_map/x86_kvm32.xml
   cpu_map/x86_kvm64.xml
   cpu_map/x86_n270.xml
   cpu_map/x86_Nehalem-IBRS.xml
   cpu_map/x86_Nehalem.xml
   cpu_map/x86_Opteron_G1.xml
   cpu_map/x86_Opteron_G2.xml
   cpu_map/x86_Opteron_G3.xml
   cpu_map/x86_Opteron_G4.xml
   cpu_map/x86_Opteron_G5.xml
   cpu_map/x86_Penryn.xml
   cpu_map/x86_pentium2.xml
   cpu_map/x86_pentium3.xml
   cpu_map/x86_pentiumpro.xml
   cpu_map/x86_pentium.xml
   cpu_map/x86_phenom.xml
   cpu_map/x86_qemu32.xml
   cpu_map/x86_qemu64.xml
   cpu_map/x86_SandyBridge-IBRS.xml
   cpu_map/x86_SandyBridge.xml
   cpu_map/x86_Skylake-Client-IBRS.xml
   cpu_map/x86_Skylake-Client.xml
   cpu_map/x86_Skylake-Server-IBRS.xml
   cpu_map/x86_Skylake-Server.xml
   cpu_map/x86_vendors.xml
   cpu_map/x86_Westmere-IBRS.xml
   cpu_map/x86_Westmere.xml

The main cpu_map/index.xml file is now just a list of <include filename="XXX"/>
statements to pull in the individual files

Now we can easily see the differences in each model:

    $ diff cpu_map/x86_Broadwell.xml cpu_map/x86_Skylake-Client.xml
    2,3c2,3
    <   <model name='Broadwell'>
    <     <signature family='6' model='61'/>
    ---
    >   <model name='Skylake-Client'>
    >     <signature family='6' model='94'/>
    5a6
    >     <feature name='abm'/>
    8a10
    >     <feature name='arat'/>
    18a21
    >     <feature name='f16c'/>
    30a34
    >     <feature name='mpx'/>
    42a47
    >     <feature name='rdrand'/>
    56a62
    >     <feature name='vme'/>
    57a64
    >     <feature name='xgetbv1'/>
    58a66,67
    >     <feature name='xsavec'/>
    >     <feature name='xsaveopt'/>

Changed in v2:

 - Moved all XML files into a new src/cpu_map/ directory
 - Simplify the goto labels for error code paths.
 - Code style fixes

Daniel P. Berrangé (8):
  cpu: allow include files for CPU definition
  cpu: fix cleanup when signature parsing fails
  cpu: push more parsing logic into common code
  cpu: simplify failure cleanup paths
  cpu: move the CPU map data files into a src/cpu_map directory
  cpu: split PPC64 map data into separate files
  cpu: split x86 map data into separate files
  xml: report the filename (if any) when parsing files

 libvirt.spec.in                          |    2 +-
 mingw-libvirt.spec.in                    |    4 +-
 src/Makefile.am                          |    7 +-
 src/cpu/cpu_map.c                        |  161 +-
 src/cpu/cpu_map.h                        |   22 +-
 src/cpu/cpu_map.xml                      | 2382 ----------------------
 src/cpu/cpu_ppc64.c                      |  142 +-
 src/cpu/cpu_x86.c                        |  255 +--
 src/cpu_map/Makefile.inc.am              |   61 +
 src/cpu_map/index.xml                    |   75 +
 src/cpu_map/ppc64_POWER6.xml             |    6 +
 src/cpu_map/ppc64_POWER7.xml             |    7 +
 src/cpu_map/ppc64_POWER8.xml             |    8 +
 src/cpu_map/ppc64_POWER9.xml             |    6 +
 src/cpu_map/ppc64_POWERPC_e5500.xml      |    6 +
 src/cpu_map/ppc64_POWERPC_e6500.xml      |    6 +
 src/cpu_map/ppc64_vendors.xml            |    4 +
 src/cpu_map/x86_486.xml                  |    7 +
 src/cpu_map/x86_Broadwell-IBRS.xml       |   61 +
 src/cpu_map/x86_Broadwell-noTSX-IBRS.xml |   59 +
 src/cpu_map/x86_Broadwell-noTSX.xml      |   58 +
 src/cpu_map/x86_Broadwell.xml            |   60 +
 src/cpu_map/x86_Conroe.xml               |   33 +
 src/cpu_map/x86_EPYC-IBRS.xml            |   73 +
 src/cpu_map/x86_EPYC.xml                 |   72 +
 src/cpu_map/x86_Haswell-IBRS.xml         |   57 +
 src/cpu_map/x86_Haswell-noTSX-IBRS.xml   |   55 +
 src/cpu_map/x86_Haswell-noTSX.xml        |   54 +
 src/cpu_map/x86_Haswell.xml              |   56 +
 src/cpu_map/x86_IvyBridge-IBRS.xml       |   51 +
 src/cpu_map/x86_IvyBridge.xml            |   50 +
 src/cpu_map/x86_Nehalem-IBRS.xml         |   38 +
 src/cpu_map/x86_Nehalem.xml              |   37 +
 src/cpu_map/x86_Opteron_G1.xml           |   31 +
 src/cpu_map/x86_Opteron_G2.xml           |   35 +
 src/cpu_map/x86_Opteron_G3.xml           |   40 +
 src/cpu_map/x86_Opteron_G4.xml           |   50 +
 src/cpu_map/x86_Opteron_G5.xml           |   53 +
 src/cpu_map/x86_Penryn.xml               |   35 +
 src/cpu_map/x86_SandyBridge-IBRS.xml     |   45 +
 src/cpu_map/x86_SandyBridge.xml          |   44 +
 src/cpu_map/x86_Skylake-Client-IBRS.xml  |   70 +
 src/cpu_map/x86_Skylake-Client.xml       |   69 +
 src/cpu_map/x86_Skylake-Server-IBRS.xml  |   77 +
 src/cpu_map/x86_Skylake-Server.xml       |   76 +
 src/cpu_map/x86_Westmere-IBRS.xml        |   39 +
 src/cpu_map/x86_Westmere.xml             |   38 +
 src/cpu_map/x86_athlon.xml               |   28 +
 src/cpu_map/x86_core2duo.xml             |   33 +
 src/cpu_map/x86_coreduo.xml              |   29 +
 src/cpu_map/x86_cpu64-rhel5.xml          |   29 +
 src/cpu_map/x86_cpu64-rhel6.xml          |   31 +
 src/cpu_map/x86_features.xml             |  440 ++++
 src/cpu_map/x86_kvm32.xml                |   26 +
 src/cpu_map/x86_kvm64.xml                |   30 +
 src/cpu_map/x86_n270.xml                 |   30 +
 src/cpu_map/x86_pentium.xml              |   13 +
 src/cpu_map/x86_pentium2.xml             |   22 +
 src/cpu_map/x86_pentium3.xml             |   23 +
 src/cpu_map/x86_pentiumpro.xml           |   21 +
 src/cpu_map/x86_phenom.xml               |   36 +
 src/cpu_map/x86_qemu32.xml               |   22 +
 src/cpu_map/x86_qemu64.xml               |   40 +
 src/cpu_map/x86_vendors.xml              |    4 +
 src/util/virxml.c                        |    3 +-
 65 files changed, 2819 insertions(+), 2718 deletions(-)
 delete mode 100644 src/cpu/cpu_map.xml
 create mode 100644 src/cpu_map/Makefile.inc.am
 create mode 100644 src/cpu_map/index.xml
 create mode 100644 src/cpu_map/ppc64_POWER6.xml
 create mode 100644 src/cpu_map/ppc64_POWER7.xml
 create mode 100644 src/cpu_map/ppc64_POWER8.xml
 create mode 100644 src/cpu_map/ppc64_POWER9.xml
 create mode 100644 src/cpu_map/ppc64_POWERPC_e5500.xml
 create mode 100644 src/cpu_map/ppc64_POWERPC_e6500.xml
 create mode 100644 src/cpu_map/ppc64_vendors.xml
 create mode 100644 src/cpu_map/x86_486.xml
 create mode 100644 src/cpu_map/x86_Broadwell-IBRS.xml
 create mode 100644 src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
 create mode 100644 src/cpu_map/x86_Broadwell-noTSX.xml
 create mode 100644 src/cpu_map/x86_Broadwell.xml
 create mode 100644 src/cpu_map/x86_Conroe.xml
 create mode 100644 src/cpu_map/x86_EPYC-IBRS.xml
 create mode 100644 src/cpu_map/x86_EPYC.xml
 create mode 100644 src/cpu_map/x86_Haswell-IBRS.xml
 create mode 100644 src/cpu_map/x86_Haswell-noTSX-IBRS.xml
 create mode 100644 src/cpu_map/x86_Haswell-noTSX.xml
 create mode 100644 src/cpu_map/x86_Haswell.xml
 create mode 100644 src/cpu_map/x86_IvyBridge-IBRS.xml
 create mode 100644 src/cpu_map/x86_IvyBridge.xml
 create mode 100644 src/cpu_map/x86_Nehalem-IBRS.xml
 create mode 100644 src/cpu_map/x86_Nehalem.xml
 create mode 100644 src/cpu_map/x86_Opteron_G1.xml
 create mode 100644 src/cpu_map/x86_Opteron_G2.xml
 create mode 100644 src/cpu_map/x86_Opteron_G3.xml
 create mode 100644 src/cpu_map/x86_Opteron_G4.xml
 create mode 100644 src/cpu_map/x86_Opteron_G5.xml
 create mode 100644 src/cpu_map/x86_Penryn.xml
 create mode 100644 src/cpu_map/x86_SandyBridge-IBRS.xml
 create mode 100644 src/cpu_map/x86_SandyBridge.xml
 create mode 100644 src/cpu_map/x86_Skylake-Client-IBRS.xml
 create mode 100644 src/cpu_map/x86_Skylake-Client.xml
 create mode 100644 src/cpu_map/x86_Skylake-Server-IBRS.xml
 create mode 100644 src/cpu_map/x86_Skylake-Server.xml
 create mode 100644 src/cpu_map/x86_Westmere-IBRS.xml
 create mode 100644 src/cpu_map/x86_Westmere.xml
 create mode 100644 src/cpu_map/x86_athlon.xml
 create mode 100644 src/cpu_map/x86_core2duo.xml
 create mode 100644 src/cpu_map/x86_coreduo.xml
 create mode 100644 src/cpu_map/x86_cpu64-rhel5.xml
 create mode 100644 src/cpu_map/x86_cpu64-rhel6.xml
 create mode 100644 src/cpu_map/x86_features.xml
 create mode 100644 src/cpu_map/x86_kvm32.xml
 create mode 100644 src/cpu_map/x86_kvm64.xml
 create mode 100644 src/cpu_map/x86_n270.xml
 create mode 100644 src/cpu_map/x86_pentium.xml
 create mode 100644 src/cpu_map/x86_pentium2.xml
 create mode 100644 src/cpu_map/x86_pentium3.xml
 create mode 100644 src/cpu_map/x86_pentiumpro.xml
 create mode 100644 src/cpu_map/x86_phenom.xml
 create mode 100644 src/cpu_map/x86_qemu32.xml
 create mode 100644 src/cpu_map/x86_qemu64.xml
 create mode 100644 src/cpu_map/x86_vendors.xml

-- 
2.17.1


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