[libvirt PATCH 0/4] cpu_map: Add more -noTSX x86 CPU models

[Christian Ehrhardt]

On Wed, Mar 18, 2020 at 11:13 AM Jiri Denemark <jdenemar at redhat.com> wrote:

> Christian Ehrhardt (1):
>   cpu_map: Add more -noTSX x86 CPU models
>
> Jiri Denemark (3):
>   cpu_map: Add <decode> element to x86 CPU model definitions
>   cpu_x86: Honor CPU models' <decode> element
>   cpu_map: Don't use new noTSX models for host-model CPUs
>
>
Hi,
for the Ubuntu bug that got all of this started I applied your patches,
built in a PPA and tested the case.

#1 virsh capabilities
Before:
Broadwell-noTSX-IBRS + 33 features

After:
Skylake-Client-noTSX-IBRS +24 features

=> good



#2 virsh domcapabilities
Before:
Skylake-Client-IBRS + 16 features

After:
Skylake-Client-IBRS + 16 features (unchanged as intended for compatibility)

=> good



#3 usable models
Before:
only older types

After:
now added "Skylake-Client-noTSX-IBRS" which is a more modern IBRS type than
the others I had

=> good


#4 use the new types

My system isn't new enough to get the others added, but that is fine as a
test.
Also the type "Skylake-Server-noTSX-IBRS" worked, auto-disabling the avx
features my chip is missing.

I started a guest with such a type through libvirt and it looks as expected:
  -cpu Skylake-Client-noTSX-IBRS

=> good

#5 and finally the adapted tests still ran fien at build time.

Thank you Jiri for the changes, please feel free to add my:

Reviewed-by: Christian Ehrhardt <christian.ehrhardt at canonical.com>
Tested-by: Christian Ehrhardt <christian.ehrhardt at canonical.com>


 src/cpu/cpu_x86.c                             | 65 ++++++++++++-
>  src/cpu_map/Makefile.inc.am                   |  5 +
>  src/cpu_map/index.xml                         |  5 +
>  src/cpu_map/x86_486.xml                       |  1 +
>  src/cpu_map/x86_Broadwell-IBRS.xml            |  1 +
>  src/cpu_map/x86_Broadwell-noTSX-IBRS.xml      |  1 +
>  src/cpu_map/x86_Broadwell-noTSX.xml           |  1 +
>  src/cpu_map/x86_Broadwell.xml                 |  1 +
>  src/cpu_map/x86_Cascadelake-Server-noTSX.xml  | 79 ++++++++++++++++
>  src/cpu_map/x86_Cascadelake-Server.xml        |  1 +
>  src/cpu_map/x86_Conroe.xml                    |  1 +
>  src/cpu_map/x86_Dhyana.xml                    |  1 +
>  src/cpu_map/x86_EPYC-IBPB.xml                 |  1 +
>  src/cpu_map/x86_EPYC.xml                      |  1 +
>  src/cpu_map/x86_Haswell-IBRS.xml              |  1 +
>  src/cpu_map/x86_Haswell-noTSX-IBRS.xml        |  1 +
>  src/cpu_map/x86_Haswell-noTSX.xml             |  1 +
>  src/cpu_map/x86_Haswell.xml                   |  1 +
>  src/cpu_map/x86_Icelake-Client-noTSX.xml      | 82 +++++++++++++++++
>  src/cpu_map/x86_Icelake-Client.xml            |  1 +
>  src/cpu_map/x86_Icelake-Server-noTSX.xml      | 91 +++++++++++++++++++
>  src/cpu_map/x86_Icelake-Server.xml            |  1 +
>  src/cpu_map/x86_IvyBridge-IBRS.xml            |  1 +
>  src/cpu_map/x86_IvyBridge.xml                 |  1 +
>  src/cpu_map/x86_Nehalem-IBRS.xml              |  1 +
>  src/cpu_map/x86_Nehalem.xml                   |  1 +
>  src/cpu_map/x86_Opteron_G1.xml                |  1 +
>  src/cpu_map/x86_Opteron_G2.xml                |  1 +
>  src/cpu_map/x86_Opteron_G3.xml                |  1 +
>  src/cpu_map/x86_Opteron_G4.xml                |  1 +
>  src/cpu_map/x86_Opteron_G5.xml                |  1 +
>  src/cpu_map/x86_Penryn.xml                    |  1 +
>  src/cpu_map/x86_SandyBridge-IBRS.xml          |  1 +
>  src/cpu_map/x86_SandyBridge.xml               |  1 +
>  src/cpu_map/x86_Skylake-Client-IBRS.xml       |  1 +
>  src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 74 +++++++++++++++
>  src/cpu_map/x86_Skylake-Client.xml            |  1 +
>  src/cpu_map/x86_Skylake-Server-IBRS.xml       |  1 +
>  src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 76 ++++++++++++++++
>  src/cpu_map/x86_Skylake-Server.xml            |  1 +
>  src/cpu_map/x86_Westmere-IBRS.xml             |  1 +
>  src/cpu_map/x86_Westmere.xml                  |  1 +
>  src/cpu_map/x86_athlon.xml                    |  1 +
>  src/cpu_map/x86_core2duo.xml                  |  1 +
>  src/cpu_map/x86_coreduo.xml                   |  1 +
>  src/cpu_map/x86_cpu64-rhel5.xml               |  1 +
>  src/cpu_map/x86_cpu64-rhel6.xml               |  1 +
>  src/cpu_map/x86_kvm32.xml                     |  1 +
>  src/cpu_map/x86_kvm64.xml                     |  1 +
>  src/cpu_map/x86_n270.xml                      |  1 +
>  src/cpu_map/x86_pentium.xml                   |  1 +
>  src/cpu_map/x86_pentium2.xml                  |  1 +
>  src/cpu_map/x86_pentium3.xml                  |  1 +
>  src/cpu_map/x86_pentiumpro.xml                |  1 +
>  src/cpu_map/x86_phenom.xml                    |  1 +
>  src/cpu_map/x86_qemu32.xml                    |  1 +
>  src/cpu_map/x86_qemu64.xml                    |  1 +
>  .../x86_64-cpuid-Core-i7-8550U-host.xml       | 11 +--
>  .../domaincapsdata/qemu_4.2.0-q35.x86_64.xml  |  5 +
>  .../domaincapsdata/qemu_4.2.0-tcg.x86_64.xml  |  5 +
>  tests/domaincapsdata/qemu_4.2.0.x86_64.xml    |  5 +
>  .../domaincapsdata/qemu_5.0.0-q35.x86_64.xml  |  5 +
>  .../domaincapsdata/qemu_5.0.0-tcg.x86_64.xml  |  5 +
>  tests/domaincapsdata/qemu_5.0.0.x86_64.xml    |  5 +
>  64 files changed, 552 insertions(+), 15 deletions(-)
>  create mode 100644 src/cpu_map/x86_Cascadelake-Server-noTSX.xml
>  create mode 100644 src/cpu_map/x86_Icelake-Client-noTSX.xml
>  create mode 100644 src/cpu_map/x86_Icelake-Server-noTSX.xml
>  create mode 100644 src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
>  create mode 100644 src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
>
> --
> 2.25.1
>
>

-- 
Christian Ehrhardt
Staff Engineer, Ubuntu Server
Canonical Ltd
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