Red Hat partners with SiFive for a RISC-V developer preview of Red Hat Enterprise Linux 10

Note from the editor: This blog post was originally published on May 20, 2025 and has been updated with new information.

Red Hat has collaborated with SiFive to reveal the developer preview of Red Hat Enterprise Linux (RHEL) 10 on the popular SiFive HiFive Premier P550 platform. The developer preview downloads will be available on June 1, 2025.

SiFive is one of the pioneers of the RISC-V architecture, and a natural partner for Red Hat as we build an implementation of RHEL for the developer community on RISC-V hardware. Offering early access to a developer preview of RHEL on such a popular platform is an example of the innovation that both companies represent to the industry. 

What is RISC-V?

RISC-V is an implementation of reduced instruction set computing, and is an open source instruction set architecture (ISA) that anyone can use as a foundation for a microprocessor. Early adoption of an emerging ISA is unusual for an enterprise vendor such as Red Hat, but collaborative hardware development practices naturally foster an ecosystem of open source software. An open ISA is a cornerstone of an open hardware platform. RISC-V adoption is a choice that the market will make based on each segment's criteria, and Red Hat supports that choice and is following our mission to enable open source.

Why Red Hat and SiFive have collaborated for RISC-V

The intention of making a developer preview release of RHEL 10 on the SiFive platform is twofold:

1. Customers evaluating RISC-V will be able to use this developer preview to assess the relevance of this technology to their IT infrastructure, enterprise workloads, as well as edge or embedded applications.
2. The release of the developer preview, the binary image, the source code of our implementation of the Linux 6.12 kernel, plus all our upstream contributions and commits, is a stimulus to all Linux developers building RISC-V based solutions. 

In keeping with our commitment to fully open and transparent enterprise software development, we're providing a version of the CentOS Stream 10 source code that supports RISC-V. This version is in the process of being released within the CentOS ISA special interest group (SIG). Watch the CentOS blog for more information.

Developer preview availability

RISC-V is a quickly emerging technology that iterates upon an already proven concept. RISC processors already power consumer electronics, edge devices, and servers. RISC-V is an open source evolution of hardware design, and the SiFive HiFive Premier P550 development board is the easiest way to run the RHEL 10 developer preview on RISC-V. 

Following up on our announcement last week of the developer preview of RHEL 10 on RISC-V, the downloads are now available at developers.redhat.com/products/rhel-riscv.

There are a total of three files

1. Documentation on how to set up the hardware prior to the RHEL boot.
2. The binary image. (< 3GB)
3. The source tarball. (< 15GB)

Please note that to access the downloads you must be logged in to your developers.redhat account.

At this time Red Hat would like to stress that we have not performed implementation work on any other hardware than the SiFive HiFive Premier P550. 

For future development, updates and to engage with the project please connect with us via the CentOS Stream community.